From patchwork Mon Oct 31 18:40:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13409 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2480251wru; Mon, 31 Oct 2022 11:45:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4vLrK+rqXd5xahwMVuEysy/bUmyZty/d2z3mTViDaWEuC1YyElIkzD7nLKgnxx+U6Z2ldn X-Received: by 2002:a17:903:41cb:b0:183:1648:be0f with SMTP id u11-20020a17090341cb00b001831648be0fmr15646831ple.18.1667241918550; Mon, 31 Oct 2022 11:45:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667241918; cv=none; d=google.com; s=arc-20160816; b=C8hVRsZw+ijMrCyu3Iy6pB8TQQYsPGLXOTAd7XVw6HAlizrJ4Z154OpEPYdcoWFKIU fvWnF8smlfXCsEZo2cdt+G2lRt1fSdopM2MWvXDgRNYtElvYyT4auUHWTuvaYU+hIwPX V+C4U4DU2DBIPmwq2hXvQLIOxyQKYwt84HRa/81rWCMqwq0ym2bBmMoF23d2F86sguwv Ia9w3qeKDu0tYM+KrFElqw4aD5W4TPczzfo9o86QzihJWA1au5/SinaklMsq5VRoy+Gc VbJ+smbs3Pc6Cooh/1WXjXfonYVMe/k3REB1CVdh8w33gA2SUAfvBo/cCcVY9PN0Wuaw oS0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=pf0wqcQ2vn6wyNNf67PgKqcbfJEkj1r+s1XXcU5BuM8=; b=YRxAI0FIGH1LVU+q3uTJv8Remg1yfnGPlyxO/IIpgjJxAntyljKV06vBC1jKEzDLvt GWSM9btE61ugCMsQe3R1VDfisCuoW9FEnerosdmu5Bw85fsglbD5iMYhzEusPAd+C5s+ BqTPQZFVX3oP5zin08jxIq1EfY2YtAD9pKzdKcTQ2sA+7Dz+7ZwRqucW42cJ8q+9U17F YIte2veUfgRA7e9NF/0o6bKWCs3kAZscYf90VlKH+dBst2PmbQPamlqnRUnm8GNrjxKK nm5msnKTIYyLBewXStxDIho4NcLEv97EvukWO3z50X5hoc1J2uiuuaslp2SCPKoc9hO+ borw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=NmkDIJZq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.8.167]) by smtp.gmail.com with ESMTPSA id k18-20020a05600c081200b003b4935f04a4sm8525887wmp.5.2022.10.31.11.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:40:47 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Jiri Slaby , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: serial: ingenic: Add support for the JZ4750/55 SoCs Date: Mon, 31 Oct 2022 21:40:39 +0300 Message-Id: <20221031184041.1338129-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221031184041.1338129-1-lis8215@gmail.com> References: <20221031184041.1338129-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748229862224037002?= X-GMAIL-MSGID: =?utf-8?q?1748229862224037002?= These SoCs UART block are the same as JZ4725b' one, the difference is outside of the block - it is in the clock generation unit (CGU). The difference requires to make a quirk for early console init. Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml index 9ca7a18ec..315ceb722 100644 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml @@ -20,6 +20,7 @@ properties: oneOf: - enum: - ingenic,jz4740-uart + - ingenic,jz4750-uart - ingenic,jz4760-uart - ingenic,jz4780-uart - ingenic,x1000-uart @@ -31,6 +32,9 @@ properties: - items: - const: ingenic,jz4725b-uart - const: ingenic,jz4740-uart + - items: + - const: ingenic,jz4755-uart + - const: ingenic,jz4750-uart reg: maxItems: 1 From patchwork Mon Oct 31 18:40:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13410 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2480298wru; Mon, 31 Oct 2022 11:45:25 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5HwixmnZJxkdJrFBXBZDO5Jai3WrwGYSnLurqmMB/P+Ff07a4gXWnvXXKaFo4fAyIPOiUz X-Received: by 2002:a17:903:2308:b0:186:95bd:dc21 with SMTP id d8-20020a170903230800b0018695bddc21mr15638915plh.135.1667241925370; Mon, 31 Oct 2022 11:45:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667241925; cv=none; d=google.com; s=arc-20160816; b=JTZ+K9psmxveuZG/3O1whgFYv82Lhvy6v1FqWEAfFeG57GsFDil5AP27pwj+1MQRm3 MewLU35ra4cuag5d/F5ajOk9lpq/Q/OobSGXMpQvuFPvb4lwNuxLr1bnvS5j/2g8xAJR LZIS4hQinhkDh6lEiYZF6V02bi05r3KsujqwnBEuhliY2XJJfIlZXIE9YJYh4GnD1GJV vyXa6RPXQ4Q8+nFToL+A3v9hhxsM6A5DEubmZm/YbZa2fvUPyh3VJ3fe1aIBIGyJeVYl EPvTvo6JkMAKM/fXQzC1vpq0IwFsPC2KAXklYH7BpkD8c5FGLA3sxsvwmrXRTP3pYSHr 6F5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=4l/rQiBjU2EDqlLswcve2tJlyY/XQgWJ8y1LR4isvn0=; b=ieDGPlF/zjpQRmCw24ey+oaD6gah0Dl61GF0zwXKAomm39W8uJaV/HfVXVARYTArzx MO8iqcX+Z360eAZayNJmi4LOUnpNECGJ7mcGgrz4ZzOB3lSPby+9GLLjkggMk7QpR3st CnLkEjjEWAHdUxiaHirykXJEL7PUumrEZJ8RmjCm2lO3iMbTWszrXotfc44K1nxShOen yi3+bcohk4PFjbyVqKTqNKjpStvK9y3Avq8tpCV3pfrKgQqYOPV2TnLYRvuUOl3OQC0g ZYR3rCr0hyPTtlMIE/madw9j9WDz9pQRq+bTuzQcYVmfSkNyvUwbpow9PBIsRAUW903W 5USw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b="DjG/2ufk"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.8.167]) by smtp.gmail.com with ESMTPSA id k18-20020a05600c081200b003b4935f04a4sm8525887wmp.5.2022.10.31.11.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 11:40:48 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Jiri Slaby , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v4 2/2] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 Date: Mon, 31 Oct 2022 21:40:40 +0300 Message-Id: <20221031184041.1338129-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221031184041.1338129-1-lis8215@gmail.com> References: <20221031184041.1338129-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748229869028207204?= X-GMAIL-MSGID: =?utf-8?q?1748229869028207204?= JZ4750/55/60 (but not JZ4760b) have an optional /2 divider between the EXT oscillator and some peripherals including UART, which will be enabled if using a 24 MHz oscillator, and disabled when using a 12 MHz oscillator. This behavior relies on hardware differences: most boards (if not all) with those SoCs have 12 or 24 MHz oscillators but many peripherals want 12Mhz to operate properly (AIC and USB-PHY at least). The 16MHz threshold looks arbitrary but used in vendor's bootloader code for enable the divider. The patch doesn't affect JZ4760's behavior as it is subject for another patchset with re-classification of all supported ingenic UARTs. Link: https://github.com/carlos-wong/uboot_jz4755/blob/master/cpu/mips/jz_serial.c#L158 Signed-off-by: Siarhei Volkau --- drivers/tty/serial/8250/8250_ingenic.c | 32 +++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c index 2b2f5d8d2..617b8ce60 100644 --- a/drivers/tty/serial/8250/8250_ingenic.c +++ b/drivers/tty/serial/8250/8250_ingenic.c @@ -87,7 +87,7 @@ static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev dev->port.uartclk = be32_to_cpup(prop); } -static int __init ingenic_early_console_setup(struct earlycon_device *dev, +static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev, const char *opt) { struct uart_port *port = &dev->port; @@ -103,8 +103,6 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev, uart_parse_options(opt, &baud, &parity, &bits, &flow); } - ingenic_early_console_setup_clock(dev); - if (dev->baud) baud = dev->baud; divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud); @@ -129,9 +127,36 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev, return 0; } +static int __init ingenic_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ + ingenic_early_console_setup_clock(dev); + + return ingenic_earlycon_setup_tail(dev, opt); +} + +static int __init jz4750_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ + /* + * JZ4750/55/60 have an optional /2 divider between the EXT + * oscillator and some peripherals including UART, which will + * be enabled if using a 24 MHz oscillator, and disabled when + * using a 12 MHz oscillator. + */ + ingenic_early_console_setup_clock(dev); + if (dev->port.uartclk >= 16000000) + dev->port.uartclk /= 2; + + return ingenic_earlycon_setup_tail(dev, opt); +} + OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart", ingenic_early_console_setup); +OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart", + jz4750_early_console_setup); + OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart", ingenic_early_console_setup); @@ -328,6 +353,7 @@ static const struct ingenic_uart_config x1000_uart_config = { static const struct of_device_id of_match[] = { { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config }, + { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },