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Wed, 19 Jul 2023 14:23:25 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH 1/2] PCI, AER: Export and make pcie_aer_is_native() global Date: Wed, 19 Jul 2023 19:23:12 +0000 Message-ID: <20230719192313.38591-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT023:EE_|CY8PR12MB7316:EE_ X-MS-Office365-Filtering-Correlation-Id: d8291a6b-0dbb-4aee-4b1c-08db888da0f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Smita Koralahalli Acked-by: Bjorn Helgaas Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/portdrv.h | 2 -- include/linux/aer.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index f6c24ded134c..87d90dbda023 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -229,6 +229,7 @@ int pcie_aer_is_native(struct pci_dev *dev) return pcie_ports_native || host->native_aer; } +EXPORT_SYMBOL_GPL(pcie_aer_is_native); int pci_enable_pcie_error_reporting(struct pci_dev *dev) { diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 58a2b1a1cae4..1f3803bde7ee 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -29,10 +29,8 @@ extern bool pcie_ports_dpc_native; #ifdef CONFIG_PCIEAER int pcie_aer_init(void); -int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pcie_aer_init(void) { return 0; } -static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif #ifdef CONFIG_HOTPLUG_PCI_PCIE diff --git a/include/linux/aer.h b/include/linux/aer.h index 3a3ab05e13fd..94ce49a5f8d5 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -45,6 +45,7 @@ struct aer_capability_regs { int pci_enable_pcie_error_reporting(struct pci_dev *dev); int pci_disable_pcie_error_reporting(struct pci_dev *dev); int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +int pcie_aer_is_native(struct pci_dev *dev); #else static inline int pci_enable_pcie_error_reporting(struct pci_dev *dev) { @@ -58,6 +59,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { return -EINVAL; } +static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif void cper_print_aer(struct pci_dev *dev, int aer_severity, From patchwork Wed Jul 19 19:23:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 122792 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2676538vqt; Wed, 19 Jul 2023 13:05:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlHUjnpLGIs9u+gY35nkZxol2/Ux1l7wi8xF6ZBCc9tXYMiOy5P3Ucf/IPMAkjwEVONae+GI X-Received: by 2002:ac2:5498:0:b0:4fb:96ed:93b3 with SMTP id t24-20020ac25498000000b004fb96ed93b3mr609136lfk.65.1689797121961; Wed, 19 Jul 2023 13:05:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689797121; cv=pass; d=google.com; s=arc-20160816; b=RWMZ5T1vX6j6yrHiFstshO5EPXrlKDCMqCvU5YCbPnAL9w1qoa2Ns10I/EX+sKi+g/ KjsQGRMiwSvEwScUS/9JUjV9UBl+lNY8L2EwIaoZaDbJN0kbvaSaxco7uz5zNUXPUN5E 7WR7nbY1O77Y3cI3t0QJgKKYFf6XBK/idezGekz01oNdOEXLkng+zOs4SvIRExNkrkgv XJ+5Yp1f8edczUODge3zCze9NDslZY3z5gCOCzzHKfqFHuVIiUVAyRVPxo43Pnw3Mdvh n/JFZqtsFd5SygDDBtERFu0/YRSLjHqPJ5S921Zowu8dnHFyGoeFcNlWHwaYZOuceO2Q HKzg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=lLPmOOeyh7gR9cySHSNk9ED1GEJZkTIqXjs3KmPK5Bc=; fh=XsftW3UEsKVDpg34R8O86oa1udFTwHG6Ldr3ac/pbNM=; b=x8fj6mHZtBj3SSgty/ZfxNYcCuFo2jifvStq4OnsFpk6SV5EvXQHfYN8/+sWgwOV2s hUxZKC/cP9gLJL7YsfNtsApgpEcVicgh1l572qce+0SSi5BWIfYKruwyFDlWTvJI0Qh2 YPm8K+iGvkbE5GtcfiqDwd+avpAG4us4efa1w8BsgYhW81ACc3p/tRpqgp1igPnUtbj9 F5ntYti7BTm4z02l98hEGbK0Z0P+BvwZpoVeG7HovCSzVUkdk2qqCEXratoinEXJGpcZ mdVlA1gJ3DcDqHut9E98O/GHKnuIPj5c5vVpLV5dIhpSvY2GaVMftTWyz3JXmT4bmPgU uijQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=xFXzh3Zz; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 19 Jul 2023 14:23:25 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH 2/2] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Date: Wed, 19 Jul 2023 19:23:13 +0000 Message-ID: <20230719192313.38591-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230719192313.38591-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT023:EE_|MW3PR12MB4364:EE_ X-MS-Office365-Filtering-Correlation-Id: b33d5df1-9777-4e15-1e40-08db888da14a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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And the CXL RAS Cap registers reported on Protocol errors should check for AER _OSC rather than CXL Memory Error Reporting Control _OSC. The CXL Memory Error Reporting Control _OSC specifically highlights handling Memory Error Logging and Signaling Enhancements. These kinds of errors are reported through a device's mailbox and can be managed independently from CXL Protocol Errors. [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022. Signed-off-by: Smita Koralahalli --- drivers/cxl/pci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1cb1494c28fe..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -541,9 +540,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) return 0; } - /* BIOS has CXL error control */ - if (!host_bridge->native_cxl_error) - return -ENXIO; + /* BIOS has PCIe AER error control */ + if (!pcie_aer_is_native(pdev)) + return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); if (rc)