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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH 1/7] thermal: rockchip: Simplify getting match data Date: Mon, 31 Oct 2022 18:50:52 +0100 Message-Id: <20221031175058.175698-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226618144450604?= X-GMAIL-MSGID: =?utf-8?q?1748226618144450604?= It's possible to directly get the match data in a generic way nowadays. Signed-off-by: Sebastian Reichel Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 819e059cde71..0a0f38c29842 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1353,16 +1353,11 @@ static int rockchip_thermal_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct rockchip_thermal_data *thermal; - const struct of_device_id *match; struct resource *res; int irq; int i; int error; - match = of_match_node(of_rockchip_thermal_match, np); - if (!match) - return -ENXIO; - irq = platform_get_irq(pdev, 0); if (irq < 0) return -EINVAL; @@ -1374,7 +1369,7 @@ static int rockchip_thermal_probe(struct platform_device *pdev) thermal->pdev = pdev; - thermal->chip = (const struct rockchip_tsadc_chip *)match->data; + thermal->chip = (const struct rockchip_tsadc_chip *) device_get_match_data(&pdev->dev); if (!thermal->chip) return -EINVAL; From patchwork Mon Oct 31 17:50:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13372 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2455997wru; Mon, 31 Oct 2022 10:56:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7hfGUEHPV2kedgKrzujpgyk2E8VozcDwesddTX3fP3NqV/cLNYdunGx3jNrwTUXfHY4V6V X-Received: by 2002:a05:6402:5288:b0:457:22e5:8022 with SMTP id en8-20020a056402528800b0045722e58022mr14800528edb.244.1667238962104; Mon, 31 Oct 2022 10:56:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667238962; cv=none; d=google.com; s=arc-20160816; b=mJhgHFgvq32qbSBzzxsGasgxet4CJG1YykQOr41BwxBLmeZa34EvSLZW6Sc8mofmUq 6PsOUoIsJxxe999xauBHjXKalPBKYgPdzWpgUFiF033LLZxYm9NnT2xEy/79NyajRwV3 2KUmnF4xLDEIDi7ldG8Dxy6BoNt4UAG4Q2B+g5mFslWv/KAF8O/b2HQg/TS7eOdS4zb9 8u47UMPMEkfc6rNw7sBQ/q1RyGbY+tHrzm9expzE5OFKOCxkv9Pq6EWrNbh1yq+2Fu7o vWruPItYWYzT6mjULUj03MDWGNW1qSglTyyXgtKZYJ+8RrCDWbtPZrbMVoGBgLoL0Xxy aAGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XzDorxSBoIPExS/6Jb5qai1OYoTsd0nSZ7d3yTkHckk=; b=ktg/dlsuiN3cIgNDCkHh8VlUrR4GrghWgR0/23jAft5wv9JgHL4PY4X2QxPr4MZOdm JGsR/LXoKdkQYJRl+AzyivhXbR+zwtduhQlFeqPxhz2foQN7eIZ8kXrzh8HwLgVoYxlg yMXvIPkjYETJpEfUGq1cjjC4St120cuMldcM4XDSjiyr1jGhhx3Ehk3U5/xCzYUnMxls aJdOvf08HTRRw//9HLa3ukVeQXT3BvsKkbaYKQvD6HDqpMbS/8QKaP+Q6x3kXdvcapSa YW6cVIJ8aSzZsDwXqwQnwSjsIljuErgA8vNUeGECbCK9m+5jg3OulvPlimDRDGHdNc04 lyZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=k32Z1g7z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH 2/7] thermal: rockchip: Simplify clock logic Date: Mon, 31 Oct 2022 18:50:53 +0100 Message-Id: <20221031175058.175698-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226761975226224?= X-GMAIL-MSGID: =?utf-8?q?1748226761975226224?= By using devm_clk_get_enabled() the clock acquisition and enabling can be done in one step with automatic error handling. Signed-off-by: Sebastian Reichel Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 33 +++++------------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 0a0f38c29842..6d680bea0734 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1385,14 +1385,14 @@ static int rockchip_thermal_probe(struct platform_device *pdev) return error; } - thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); + thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); if (IS_ERR(thermal->clk)) { error = PTR_ERR(thermal->clk); dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); return error; } - thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); + thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); if (IS_ERR(thermal->pclk)) { error = PTR_ERR(thermal->pclk); dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", @@ -1400,26 +1400,13 @@ static int rockchip_thermal_probe(struct platform_device *pdev) return error; } - error = clk_prepare_enable(thermal->clk); - if (error) { - dev_err(&pdev->dev, "failed to enable converter clock: %d\n", - error); - return error; - } - - error = clk_prepare_enable(thermal->pclk); - if (error) { - dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); - goto err_disable_clk; - } - rockchip_thermal_reset_controller(thermal->reset); error = rockchip_configure_from_dt(&pdev->dev, np, thermal); if (error) { dev_err(&pdev->dev, "failed to parse device tree data: %d\n", error); - goto err_disable_pclk; + return error; } thermal->chip->initialize(thermal->grf, thermal->regs, @@ -1433,7 +1420,7 @@ static int rockchip_thermal_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register sensor[%d] : error = %d\n", i, error); - goto err_disable_pclk; + return error; } } @@ -1444,7 +1431,7 @@ static int rockchip_thermal_probe(struct platform_device *pdev) if (error) { dev_err(&pdev->dev, "failed to request tsadc irq: %d\n", error); - goto err_disable_pclk; + return error; } thermal->chip->control(thermal->regs, true); @@ -1462,13 +1449,6 @@ static int rockchip_thermal_probe(struct platform_device *pdev) platform_set_drvdata(pdev, thermal); return 0; - -err_disable_pclk: - clk_disable_unprepare(thermal->pclk); -err_disable_clk: - clk_disable_unprepare(thermal->clk); - - return error; } static int rockchip_thermal_remove(struct platform_device *pdev) @@ -1485,9 +1465,6 @@ static int rockchip_thermal_remove(struct platform_device *pdev) thermal->chip->control(thermal->regs, false); - clk_disable_unprepare(thermal->pclk); - clk_disable_unprepare(thermal->clk); - return 0; } From patchwork Mon Oct 31 17:50:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13369 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2455049wru; Mon, 31 Oct 2022 10:54:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM71LgLGyCuK0JonERtyU2glNFtSfgYS919JHbgUAddeORjUe9LRYFyTlu50LAwoO3BOBzI6 X-Received: by 2002:a17:907:80b:b0:77a:86a1:db52 with SMTP id wv11-20020a170907080b00b0077a86a1db52mr14229171ejb.294.1667238852479; Mon, 31 Oct 2022 10:54:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667238852; cv=none; d=google.com; s=arc-20160816; b=ezKlZ1T5nMkb/glruu7cGaqAXVKro9E2JPqP1w1NdZdcNxrexz4tAfiENZg5Q+05+5 YR6Ux3dHzCeFEK056QYeFKjNzuMPnSihpYKr8h5907/coEkadtvPKC0ADMukHLhYw+Qe n8r3ljWY9cpykAsyGH0bd/ZTTcIIrk3AtGURym4fEV3A4IlR+t1GBPd+e7vF6LQsFl2w Dk6bZpGfjxaJPHnJARvzlo4I2XwI+RCaWt6gsiEuSxy+F9mPQ6100UEDq1umtLWn+Tl/ O7MEAyYLN8dJta/PLi9GwRwaldrcgn4DCD7ObSJs5yq6ZuAh4gUBj8SV2uiY2Mb60JIV C1cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MMHkW++QH8UAws0Lj/Y533tx/R5nB9B2w/h9Y1Y6+HM=; b=izN6qvAFLqNQQ0AhJCTIv7JkkwsD3aAoma8ZOdJmaoKYI2Jz1aE/u5vV3GK2vCU172 5tb1pqW57B94MsU6S9GU7psTWhhJDDNK+IWYhfhKs2ZG1h4HXbN/ptT5IR73jG3GiMR1 q5r7JEN8Jxxb5G342v0ahxVtnDd4IrZkbubI0yI2w7lsHE95qB5eC3MPul1fJfDTEpc2 uYEzLu9zWdTgWLh2iBPNoE1gDnKB8LtpVkurlyeHg7fWQYiGR0agLAyy/8elMpbD9Go4 eSBYMMXjFo/zfAAeC71kzIOMaF542s6j38dAxU1DmIjb9VHB31A+dQd/fsLQnhSJSnQY gs7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=in67QW6M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH 3/7] thermal: rockchip: Use dev_err_probe Date: Mon, 31 Oct 2022 18:50:54 +0100 Message-Id: <20221031175058.175698-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226646607804362?= X-GMAIL-MSGID: =?utf-8?q?1748226646607804362?= Use dev_err_probe to simplify error printing in the driver's probe routine. Signed-off-by: Sebastian Reichel Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 50 +++++++++++------------------- 1 file changed, 18 insertions(+), 32 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 6d680bea0734..3dab31f163b3 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1379,35 +1379,26 @@ static int rockchip_thermal_probe(struct platform_device *pdev) return PTR_ERR(thermal->regs); thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); - if (IS_ERR(thermal->reset)) { - error = PTR_ERR(thermal->reset); - dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); - return error; - } + if (IS_ERR(thermal->reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), + "failed to get tsadc reset.\n"); thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); - if (IS_ERR(thermal->clk)) { - error = PTR_ERR(thermal->clk); - dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); - return error; - } + if (IS_ERR(thermal->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk), + "failed to get tsadc clock.\n"); thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); - if (IS_ERR(thermal->pclk)) { - error = PTR_ERR(thermal->pclk); - dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", - error); - return error; - } + if (IS_ERR(thermal->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk), + "failed to get apb_pclk clock.\n"); rockchip_thermal_reset_controller(thermal->reset); error = rockchip_configure_from_dt(&pdev->dev, np, thermal); - if (error) { - dev_err(&pdev->dev, "failed to parse device tree data: %d\n", - error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to parse device tree data\n"); thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); @@ -1416,23 +1407,18 @@ static int rockchip_thermal_probe(struct platform_device *pdev) error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], thermal->chip->chn_id[i]); - if (error) { - dev_err(&pdev->dev, - "failed to register sensor[%d] : error = %d\n", - i, error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to register sensor[%d].\n", i); } error = devm_request_threaded_irq(&pdev->dev, irq, NULL, &rockchip_thermal_alarm_irq_thread, IRQF_ONESHOT, "rockchip_thermal", thermal); - if (error) { - dev_err(&pdev->dev, - "failed to request tsadc irq: %d\n", error); - return error; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to request tsadc irq.\n"); thermal->chip->control(thermal->regs, true); From patchwork Mon Oct 31 17:50:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13367 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2454688wru; Mon, 31 Oct 2022 10:53:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM665HDJQX4QeoocGhpz8U4yhR5NuAACbDrK1vjWy4Ppr3e1vSOmNzRO6rs0e3NtZ2xgJJoc X-Received: by 2002:a17:906:8458:b0:7ac:a48d:a680 with SMTP id e24-20020a170906845800b007aca48da680mr14617965ejy.105.1667238811344; Mon, 31 Oct 2022 10:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667238811; cv=none; d=google.com; s=arc-20160816; b=SaiWtJ32HINrLW3Vthy6pgVfItXojoOfBo1UQoEPtZ7UuObn9iuE5t2Ud1Vrp+9Ec4 pTafJqwwV3EiSOuD5J6csYosACLGqahT+fojXcwhE2QEp9RdbMHeMq0o1REY7Vf/j8G/ 08XSh6oNvS+vpOIzeI9kzwh1l7CBVQr/8oVO7wLCLdJ3yBR2vrF8rUZWB+Y2bYtyRLyi Jj9sVDV/i4z5ck4UDe5O3OU0pHes0uID3xD6OXJBvPjF2F+muEDXEdi5TzI5ChY3BH6x aVr/RN0S2HBo3d/osn8utwTtJ8ZDZjeR+GeNEaa5CvwKv3yqakrMOVdeOrnhcl5FjoyZ Bemg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3i4LpOwKdyZv4RnzDnpjbmlEDwGUGZ1v5tLxxY5is7I=; b=jje55JeYVE9Qb4KZqAZxLYRI2fcq2RK9MjlfmiInP6aS37br3LjMaKjHGP2l5vdR7q qv3iFRpi5JDlasOIXy9YhGOfyiMBQjQBruvGF09ozuBBxloYBF29oR5KzF/qn+ItTS/B YuU9ufTuBakwefhHBHPi8Iim+2/uvZAKGuHKafpCvSzLNBk31aKTI1ulCqomSrxwEfkV Icjf3QGkxuJ7nk/FVOtkKE6rKJ45TI/4EUs2aDCzZp3CESmHypmkdFh23rFgZkhsoasX R/7QtIgdCmaseBlb4hNLyyWK01bF/rOq9dze0P9G9J05rx2OdV8XMjkNlbDbjluUy7pa YVfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=U7W9ExE2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH 4/7] thermal: rockchip: Simplify channel id logic Date: Mon, 31 Oct 2022 18:50:55 +0100 Message-Id: <20221031175058.175698-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226604081742863?= X-GMAIL-MSGID: =?utf-8?q?1748226604081742863?= Replace the channel ID lookup table by a simple offset, since the channel IDs are consecutive. Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 48 +++++++++++++----------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 3dab31f163b3..a547e44e2b64 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -39,15 +39,6 @@ enum tshut_polarity { TSHUT_HIGH_ACTIVE, }; -/* - * The system has two Temperature Sensors. - * sensor0 is for CPU, and sensor1 is for GPU. - */ -enum sensor_id { - SENSOR_CPU = 0, - SENSOR_GPU, -}; - /* * The conversion table has the adc value and temperature. * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) @@ -82,7 +73,7 @@ struct chip_tsadc_table { /** * struct rockchip_tsadc_chip - hold the private data of tsadc chip - * @chn_id: array of sensor ids of chip corresponding to the channel + * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip * @tshut_temp: the hardware-controlled shutdown temperature value * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) @@ -98,7 +89,7 @@ struct chip_tsadc_table { */ struct rockchip_tsadc_chip { /* The sensor id of chip correspond to the ADC channel */ - int chn_id[SOC_MAX_SENSORS]; + int chn_offset; int chn_num; /* The hardware-controlled tshut property */ @@ -925,8 +916,8 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, } static const struct rockchip_tsadc_chip px30_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* 2 channels for tsadc */ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -949,7 +940,8 @@ static const struct rockchip_tsadc_chip px30_tsadc_data = { }; static const struct rockchip_tsadc_chip rv1108_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channel for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -973,7 +965,8 @@ static const struct rockchip_tsadc_chip rv1108_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3228_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channel for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -997,8 +990,8 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3288_tsadc_data = { - .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ - .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ + /* cpu, gpu */ + .chn_offset = 1, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1022,7 +1015,8 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3328_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channels for tsadc */ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -1045,8 +1039,8 @@ static const struct rockchip_tsadc_chip rk3328_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3366_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1070,8 +1064,8 @@ static const struct rockchip_tsadc_chip rk3366_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3368_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1095,8 +1089,8 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3399_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1120,8 +1114,8 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3568_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1406,7 +1400,7 @@ static int rockchip_thermal_probe(struct platform_device *pdev) for (i = 0; i < thermal->chip->chn_num; i++) { error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], - thermal->chip->chn_id[i]); + thermal->chip->chn_offset + i); if (error) return dev_err_probe(&pdev->dev, error, "failed to register sensor[%d].\n", i); From patchwork Mon Oct 31 17:50:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13373 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2456147wru; Mon, 31 Oct 2022 10:56:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM76WuerQdtSR4ZIGgOu1B+tLTh9TA/MTSFJGWQV4mNjDvGGYqdmml61Muku/F8q5xpfIu8H X-Received: by 2002:aa7:ce09:0:b0:461:5406:20e4 with SMTP id d9-20020aa7ce09000000b00461540620e4mr15173896edv.5.1667238977904; Mon, 31 Oct 2022 10:56:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667238977; cv=none; d=google.com; s=arc-20160816; b=YTSf7KSMQyI+QwvO8JogWkv19xtFeUMvsLkeyLoC7RIvCNsmoksETsTZK8ZU5hIQAh 8of+xpkEJrgY4n2uKSwc5xdbZGxQ1ezVWUkSfu1/dfJZitwZzOHdAEjSA+UcM0MZ68iw 3NoDhot7wvngTvtwqI1dvyAFrkdPriWYGFInK0vj3rwWzmWp0eAGTvKG4HxrSY0KqU3n AZ/stoRjQObKzNxat22uDUktwFWOdP8cT2ULzWb/7DfTYqjf+oXj2ws1bo6cVqWTC6OZ TjYWclOBnD2X4U5+Muf70P0I62AFHHc0uZHyoDuuCnaYX3yVcjn/pBRFR0REMhEOPw5E 8zdg== ARC-Message-Signature: i=1; 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH 5/7] thermal: rockchip: Support dynamic sized sensor array Date: Mon, 31 Oct 2022 18:50:56 +0100 Message-Id: <20221031175058.175698-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226778202136385?= X-GMAIL-MSGID: =?utf-8?q?1748226778202136385?= Dynamically allocate the sensors array based on the amount of platform sensors in preparation for rk3588 support, which needs 7 sensors. Signed-off-by: Sebastian Reichel Reviewed-by: Heiko Stuebner --- drivers/thermal/rockchip_thermal.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index a547e44e2b64..c9d04b58a1e5 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -51,12 +51,6 @@ enum adc_sort_mode { #include "thermal_hwmon.h" -/** - * The max sensors is two in rockchip SoCs. - * Two sensors: CPU and GPU sensor. - */ -#define SOC_MAX_SENSORS 2 - /** * struct chip_tsadc_table - hold information about chip-specific differences * @id: conversion table @@ -147,7 +141,7 @@ struct rockchip_thermal_data { struct platform_device *pdev; struct reset_control *reset; - struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; + struct rockchip_thermal_sensor *sensors; struct clk *clk; struct clk *pclk; @@ -1367,6 +1361,11 @@ static int rockchip_thermal_probe(struct platform_device *pdev) if (!thermal->chip) return -EINVAL; + thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num, + sizeof(*thermal->sensors), GFP_KERNEL); + if (!thermal->sensors) + return -ENOMEM; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); thermal->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(thermal->regs)) From patchwork Mon Oct 31 17:50:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2455897wru; Mon, 31 Oct 2022 10:55:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6ulYAyGIwCeJKecY+Y2x0ioawX3IMaR6cfirOIJwbZhAiX6u4DhxS75Oo9TBjr3vsPDD0l X-Received: by 2002:a17:907:2d2c:b0:78d:d289:7efd with SMTP id gs44-20020a1709072d2c00b0078dd2897efdmr14579201ejc.166.1667238952008; Mon, 31 Oct 2022 10:55:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667238952; cv=none; d=google.com; s=arc-20160816; b=b9Xq0qth/vwUrGEeDlV3MeX1nd+WotN5phM9Jn0jzDWh4izOaqfGDzKgQuCK2ELhBK P99oM0FY6msAMVho877Wf3fv614gEewfvoUeHRGxjf1Z0gTOfAjPu7jESxu1rGo2YF8l P4LmiFaq3ZzBXZSJgg32StKZTzVPbSn1ha9R3ePUTrN2GNxr7KRj4AYgZfpT2dXfVIXw AFScl1U6M+QbGBnPQiReWsYho8kV9jT2hfCbm+ftFRwFJj/EF+BqrYBlZ3qaW8vY1PUl 7+wVUOIGDfOXDAn556H7mZ0WX/2V15LZq27zH6pRdubd+V9x52a59q4spxV9l8fqjfSj wdCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u/qXNQsVJpWsKIGxFwBm/pdjo26ZRjWem9Y0io6GiuM=; b=Aa9rFG+sW4qnNtSIYNUoLLNvMP0d+zIsO8232KVh6cWZvxdJ0jMZMoI8S4Hc30dbKA cy3g+u8N2maDA/xj9DkPkfp/zqiE/lusjUi1q4D9dfXJoDFYeLbymDN1bl1NdHK58uT5 Qn3GESU+nTOnkUCAUZKaiQpGhqDEZvx71WGVsxj+lC9EqDQT4vjsiaEeBLK5ZDL8nr+t WbI0u/y6ezB2yGtVMDM66fqipkd+N74HK7CEmkyU8BTtZXpNRRCeNU4Vvnk1h3Ry7f8t KpclT8CarsvHxHg5GJOsl74wky0Ghfu/GO6aigsrvNQkWicg/AZfYqihmdaTx9QHRjrT JxpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ouibv5MO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Finley Xiao , kernel@collabora.com, Sebastian Reichel Subject: [PATCH 6/7] thermal: rockchip: Support RK3588 SoC in the thermal driver Date: Mon, 31 Oct 2022 18:50:57 +0100 Message-Id: <20221031175058.175698-7-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226751637782671?= X-GMAIL-MSGID: =?utf-8?q?1748226751637782671?= From: Finley Xiao The RK3588 SoC has seven temperature sensor ADC channels: - Chip Center - CPU Cluster 1 (Dual A76 "Big" Cores) - CPU Cluster 2 (Dual A76 "Big" Cores) - CPU Cluster 0 (Quad A55 "Little" Cores) - Power Domain Center - Graphics Processing Unit - Neural Processing Unit Signed-off-by: Finley Xiao [rebase, squash fixes] Reviewed-by: Heiko Stuebner Signed-off-by: Sebastian Reichel --- drivers/thermal/rockchip_thermal.c | 177 +++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index c9d04b58a1e5..48e40c3b3de6 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -165,29 +165,49 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_CON 0x04 #define TSADCV2_INT_EN 0x08 #define TSADCV2_INT_PD 0x0c +#define TSADCV3_AUTO_SRC_CON 0x0c +#define TSADCV3_HT_INT_EN 0x14 +#define TSADCV3_HSHUT_GPIO_INT_EN 0x18 +#define TSADCV3_HSHUT_CRU_INT_EN 0x1c +#define TSADCV3_INT_PD 0x24 +#define TSADCV3_HSHUT_PD 0x28 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) +#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) +#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) +#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 +#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c +#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 #define TSADCV2_AUTO_PERIOD 0x68 #define TSADCV2_AUTO_PERIOD_HT 0x6c +#define TSADCV3_AUTO_PERIOD 0x154 +#define TSADCV3_AUTO_PERIOD_HT 0x158 #define TSADCV2_AUTO_EN BIT(0) +#define TSADCV2_AUTO_EN_MASK BIT(16) #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) +#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) +#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn) #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) +#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) #define TSADCV3_AUTO_Q_SEL_EN BIT(1) #define TSADCV2_INT_SRC_EN(chn) BIT(chn) +#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) +#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff #define TSADCV2_DATA_MASK 0xfff #define TSADCV3_DATA_MASK 0x3ff +#define TSADCV4_DATA_MASK 0x1ff #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 @@ -198,6 +218,8 @@ struct rockchip_thermal_data { #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -214,6 +236,12 @@ struct rockchip_thermal_data { #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) +#define RK3588_GRF0_TSADC_CON 0x0100 + +#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0) +#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10) +#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12) + #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) #define GRF_TSADC_VCM_EN_L (0x10001 << 7) @@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_code_table[] = { {TSADCV2_DATA_MASK, 125000}, }; +static const struct tsadc_table rk3588_code_table[] = { + {0, -40000}, + {215, -40000}, + {285, 25000}, + {350, 85000}, + {395, 125000}, + {TSADCV4_DATA_MASK, 125000}, +}; + static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, int temp) { @@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, } } +static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __iomem *regs) writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } +static void rk_tsadcv4_irq_ack(void __iomem *regs) +{ + u32 val; + + val = readl_relaxed(regs + TSADCV3_INT_PD); + writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD); + val = readl_relaxed(regs + TSADCV3_HSHUT_PD); + writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, + regs + TSADCV3_HSHUT_PD); +} + static void rk_tsadcv2_control(void __iomem *regs, bool enable) { u32 val; @@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __iomem *regs, bool enable) writel_relaxed(val, regs + TSADCV2_AUTO_CON); } +static void rk_tsadcv4_control(void __iomem *regs, bool enable) +{ + u32 val; + + if (enable) + val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; + else + val = TSADCV2_AUTO_EN_MASK; + + writel_relaxed(val, regs + TSADCV2_AUTO_CON); +} + static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int *temp) { @@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, return rk_tsadcv2_code_to_temp(table, val, temp); } +static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int *temp) +{ + u32 val; + + val = readl_relaxed(regs + TSADCV3_DATA(chn)); + + return rk_tsadcv2_code_to_temp(table, val, temp); +} + static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, return 0; } +static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 alarm_value; + + /* + * In some cases, some sensors didn't need the trip points, the + * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm + * in the end, ignore this case and disable the high temperature + * interrupt. + */ + if (temp == INT_MAX) { + writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; + } + /* Make sure the value is valid */ + alarm_value = rk_tsadcv2_temp_to_code(table, temp); + if (alarm_value == table->data_mask) + return -ERANGE; + writel_relaxed(alarm_value & table->data_mask, + regs + TSADCV3_COMP_INT(chn)); + writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; +} + static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, return 0; } +static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 tshut_value; + + /* Make sure the value is valid */ + tshut_value = rk_tsadcv2_temp_to_code(table, temp); + if (tshut_value == table->data_mask) + return -ERANGE; + + writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn)); + + /* TSHUT will be valid */ + writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), + regs + TSADCV3_AUTO_SRC_CON); + + return 0; +} + static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, enum tshut_mode mode) { @@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val, regs + TSADCV2_INT_EN); } +static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode == TSHUT_MODE_GPIO) { + val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru = TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { /* cpu, gpu */ .chn_offset = 0, @@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3588_tsadc_data = { + /* top, big_core0, big_core1, little_core, center, gpu, npu */ + .chn_offset = 0, + .chn_num = 7, /* seven channels for tsadc */ + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + .initialize = rk_tsadcv8_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv3_tshut_mode, + .table = { + .id = rk3588_code_table, + .length = ARRAY_SIZE(rk3588_code_table), + .data_mask = TSADCV4_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct of_device_id of_rockchip_thermal_match[] = { { .compatible = "rockchip,px30-tsadc", .data = (void *)&px30_tsadc_data, @@ -1168,6 +1341,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data, }, + { + .compatible = "rockchip,rk3588-tsadc", + .data = (void *)&rk3588_tsadc_data, + }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); From patchwork Mon Oct 31 17:50:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13374 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2456169wru; Mon, 31 Oct 2022 10:56:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4BuxSsn2bBy27jUavtnGjtIVtxh4FGfRK6gvj4lVJVOz78O2ynrqo4TjYA/yEa2BDrx0tg X-Received: by 2002:a17:907:6d29:b0:78d:d12d:15af with SMTP id sa41-20020a1709076d2900b0078dd12d15afmr14371860ejc.53.1667238980282; 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, Krzysztof Kozlowski Subject: [PATCH 7/7] dt-bindings: rockchip-thermal: Support the RK3588 SoC compatible Date: Mon, 31 Oct 2022 18:50:58 +0100 Message-Id: <20221031175058.175698-8-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221031175058.175698-1-sebastian.reichel@collabora.com> References: <20221031175058.175698-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748226781080161590?= X-GMAIL-MSGID: =?utf-8?q?1748226781080161590?= Add a new compatible for the thermal sensor device on RK3588 SoCs. Reviewed-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index f6c1be226aaa..55f8ec0bec01 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3368-tsadc - rockchip,rk3399-tsadc - rockchip,rk3568-tsadc + - rockchip,rk3588-tsadc - rockchip,rv1108-tsadc reg: