From patchwork Wed Jul 19 06:55:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122426 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2253491vqt; Wed, 19 Jul 2023 00:12:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlEMBtHkVWr/qMjqEIXFqNKQtNv7xjxuve2bK9dQnCABDzlqUUufkyrTNVADP2xRwrbguWm2 X-Received: by 2002:a05:6a00:ac3:b0:66c:6678:3776 with SMTP id c3-20020a056a000ac300b0066c66783776mr2673087pfl.7.1689750737715; Wed, 19 Jul 2023 00:12:17 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689750737; cv=pass; d=google.com; s=arc-20160816; b=K0eOPaMNgac1deJ/6Vh4bw+tMghHaX6nfpulXPAw50m50TBsVkNQC5WRRHp0HJTRUG USrcgV0QfjkJHzmHYJtHDNXKA5v/jqnnwZg6pTD6jSqxaWDLcZWeTKU1Fe0oXT3y5vp3 tLyYG/WCH02D+l0mr3e33MtG+Eni7iHIi6wwzpB1sE0Q0cNjTZuS2DBpf6P4mMl6jIg2 muyzE21ciRRmVivc9jkWj8ReIHJyT3nPLk09qO7wwyRbzts1xWFKWWKCLKr0ztzYrwUA hkV/GxDvM94V+InsgSt4NM112XJsYWnZyw3UrMumox5SRhkktR0J9NRkNmf1iewfidjZ Rt9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kPkSd6f1sGDunuQ8Kabb8LAcrnfOmNUxKIyEJD+oLQI=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=GjFFAhpkeJd4j3fgQeu49SBBLfpB0gM71tcYzZJUPzFx81xBuk+VI4PPuUK2SG2yIl oLGBtmAxiuBY8OykXuvJsIDbqccW8WwK+KqQ12t/rKRFFzS78vLHDuH4llQOIFlTkPhY Wh2mlzoSPCCWAob43yDhf5hI68T2Tdisia43N91g5ApIrzAzux9BRywebYNQxw9EDXXy BW0oUWwEIDObP4ZcQtdiXLd4bdyKyxfytMzDDFVdoYRB5ZtEMajHX5w0jYJgZ3pxlZRD DITqGWhXHBk2OhiV3HDhYf6jmDLSCjZw+lIIYguvZL9aWdO1+lx+tT5fw4LBHBD8ECg7 Yihg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Aoznjm3V; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u195-20020a6379cc000000b005577ad28a97si2810972pgc.633.2023.07.19.00.12.04; Wed, 19 Jul 2023 00:12:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Aoznjm3V; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231241AbjGSG4l (ORCPT + 99 others); Wed, 19 Jul 2023 02:56:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230183AbjGSG4j (ORCPT ); Wed, 19 Jul 2023 02:56:39 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 279271FD7; Tue, 18 Jul 2023 23:56:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bt8N5CaQ1lBu/BZP/NW7NLWLELjig+pEL3h+lJ/xypsNM7dyZ4W/IZZK6/HzKP3nXcgmtJyaixi17Fv+JSSiA4eaR+4APWYGRcs0nFtHLMZPWI1VgW4r2+E20tKi9mOz4LaZKBbjpk8xtlsAFax4drCTbkg4fK6hSkWdAaYJe9ujAPX6Iu6XyQI7tmMNLT0Mr3arJHUCHt0Oi3N4d0Lvn/xsqHgPGYIgpw7o53KYCbVnoZdseGkHudjfkVatE83qvstkyH5OpPFC7HfoENrbOQSn4eJmV0zQeW9Mp7oIOh3/cbcTgK8MdhgwHKG06Q99xKwZwKS6xBywycARJbQANA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=kPkSd6f1sGDunuQ8Kabb8LAcrnfOmNUxKIyEJD+oLQI=; b=KTA0dGAVUIIBs2K6PApDQVTw+u2BRqQR14yzDZmkbH5kN4OP6iaCZmLs7UX/ApSe1XePkxIPiY3DbuYcxR6jN5vtYUpV4CU9wSOfNgxF/tH4rPM+PEjcSkePzwHQsi/bfqkxzLUHfmfDP6w+fgw6zZO2Z7EurX6W3YIOyN7GBwLraQU3cJEV6kjIAtqWlRd8O3MCnmy4F706ddSsp07ujrT+bnqZaXKSQe+4xFlJdZurNl3ghUPD+KdSXTuZz/wFZQBpl/6d6Rs9nHaSE9RFWpwJXPgf0cloUr1vmDM/A8f1lfdHT8QypNAWbcDXlTHKBpbZdPWEWQrNRLaFWJKnmw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=kPkSd6f1sGDunuQ8Kabb8LAcrnfOmNUxKIyEJD+oLQI=; b=Aoznjm3VE0LtaacTDyuQulK1W+uTEID3Grvb9Z70g3DKegr1z4BNLVcOz7z1DopIVKdrU440oNNt7iuu2unXqn5pWllm/tkq/ts7iTUN2HEeo0H3wLe/85TN5CxWL6NiNVFUzHv+Y2RCiUBfg/hNjKJ3JRqbpVz0KazgZ+r5WEU= Received: from BN9PR03CA0529.namprd03.prod.outlook.com (2603:10b6:408:131::24) by SJ2PR12MB8881.namprd12.prod.outlook.com (2603:10b6:a03:546::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.37; Wed, 19 Jul 2023 06:56:30 +0000 Received: from BN8NAM11FT024.eop-nam11.prod.protection.outlook.com (2603:10b6:408:131:cafe::1e) by BN9PR03CA0529.outlook.office365.com (2603:10b6:408:131::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.24 via Frontend Transport; Wed, 19 Jul 2023 06:56:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:56:29 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:56:23 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 1/6] perf/x86/amd/uncore: Refactor uncore management Date: Wed, 19 Jul 2023 12:25:36 +0530 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT024:EE_|SJ2PR12MB8881:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b2c5729-eee5-475d-5804-08db8825477c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zkhFROtU/EUpWsVKQ56wf2NOpm+XkO92miW+roNmTchUqR+rnXCdn1PHra5CMvp+5Lq+IV1/s8NEoAFTofeiC/rQ5TrNocQGfDeTMDIVy4nYLyaQe0JA4xhCiMq+4W8AitqCkirO083QX5fyun7ShASPhMmSB8yb/xDuIagYlVNdsR97ERV+vw1DPu6joo7rvpkaNa7JjvHp0u36NP+4ewp4LuKFEEyUeORbLG7Cd3MnlNNG6UvL4UWxV+bDQ3XLLvqHW6MvvsV6Dv6OhsZMFwR6DJzK1OgIF18OS+tqvghjSMHs/MW3iIPOCOxE6Y5l2vD0I6yRe1Y5U0kMCqHHTeFcMJIE9z66TOsajqs6/ZpyKLSTUlx0WPSLY5862ORjBWXPbcDmijgZLfa+BJmHtgrbxbkkLy7yCy+xSKq8RnlJz6rquLNAOUsolx1h+axlV/EhvHtX4RHY03m7Xe8VPOZENjtQ4OTsl8yv37FEFnQRiuMLtTBpR6TwupItlVH8QpHI9nHhLnhbqjLf019AXpF2yyWS8hRymyCGPhdNTNNGNvARi2JegTzEBurPWwDrALl7rLEkI81PvfjRXkgLdmelP4VGvWvMBglorPHYHqw4vSHSgZlTgjV1Y9XFqA9z7mRp1fd9Vav7PfneiqoU+yTOae0wc30sTnhJB7rFqdNVsfdu8oFNciyCfk7vCnMAPlFX8W6+1HjSKq7aMOA/u0YVK9Jcwi7dqofJWXYL8LaEgbvv0G0ppnup7hnQP0WOBA3JuZpJ72DJU4Mhk5mzaA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(396003)(376002)(39860400002)(346002)(82310400008)(451199021)(40470700004)(46966006)(36840700001)(478600001)(6666004)(186003)(36860700001)(81166007)(70206006)(54906003)(40460700003)(36756003)(426003)(2616005)(83380400001)(336012)(86362001)(40480700001)(5660300002)(2906002)(70586007)(30864003)(16526019)(26005)(47076005)(8936002)(356005)(316002)(7416002)(41300700001)(8676002)(82740400003)(44832011)(110136005)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:56:29.7087 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b2c5729-eee5-475d-5804-08db8825477c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771832069558865555 X-GMAIL-MSGID: 1771832069558865555 Since struct amd_uncore is used to manage per-cpu contexts, rename it to amd_uncore_ctx in order to better reflect its purpose. Add a new struct amd_uncore and encapsulate all attributes which are shared by per-cpu contexts for the corresponding PMU. These attributes include the number of counters, active mask, MSR and RDPMC base addresses. Since the struct pmu is now embedded, the corresponding amd_uncore for a given event can be found by simply using container_of(). Finally, move all PMU-specific code to separate functions and use the original event management functions for base functionality. Determining the PMU type (such as DF or L3) is no longer required for applying any customizations or handling any quirks. The motivation is to simplify the management of uncore PMUs. Signed-off-by: Sandipan Das --- arch/x86/events/amd/uncore.c | 711 ++++++++++++++++++----------------- 1 file changed, 366 insertions(+), 345 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 83f15fe411b3..b0afbe6d9eb4 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -27,56 +27,41 @@ #define COUNTER_SHIFT 16 +#define NUM_UNCORES_MAX 2 /* DF (or NB) and L3 (or L2) */ +#define UNCORE_NAME_LEN 16 + #undef pr_fmt #define pr_fmt(fmt) "amd_uncore: " fmt static int pmu_version; -static int num_counters_llc; -static int num_counters_nb; -static bool l3_mask; static HLIST_HEAD(uncore_unused_list); -struct amd_uncore { +struct amd_uncore_ctx { int id; int refcnt; int cpu; - int num_counters; - int rdpmc_base; - u32 msr_base; - cpumask_t *active_mask; - struct pmu *pmu; struct perf_event **events; struct hlist_node node; }; -static struct amd_uncore * __percpu *amd_uncore_nb; -static struct amd_uncore * __percpu *amd_uncore_llc; - -static struct pmu amd_nb_pmu; -static struct pmu amd_llc_pmu; - -static cpumask_t amd_nb_active_mask; -static cpumask_t amd_llc_active_mask; - -static bool is_nb_event(struct perf_event *event) -{ - return event->pmu->type == amd_nb_pmu.type; -} +struct amd_uncore { + char name[UNCORE_NAME_LEN]; + int num_counters; + int rdpmc_base; + u32 msr_base; + cpumask_t active_mask; + struct pmu pmu; + struct amd_uncore_ctx * __percpu *ctx; + int (*id)(unsigned int cpu); +}; -static bool is_llc_event(struct perf_event *event) -{ - return event->pmu->type == amd_llc_pmu.type; -} +static struct amd_uncore uncores[NUM_UNCORES_MAX]; +static int num_uncores __read_mostly; static struct amd_uncore *event_to_amd_uncore(struct perf_event *event) { - if (is_nb_event(event) && amd_uncore_nb) - return *per_cpu_ptr(amd_uncore_nb, event->cpu); - else if (is_llc_event(event) && amd_uncore_llc) - return *per_cpu_ptr(amd_uncore_llc, event->cpu); - - return NULL; + return container_of(event->pmu, struct amd_uncore, pmu); } static void amd_uncore_read(struct perf_event *event) @@ -118,7 +103,7 @@ static void amd_uncore_stop(struct perf_event *event, int flags) hwc->state |= PERF_HES_STOPPED; if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { - amd_uncore_read(event); + event->pmu->read(event); hwc->state |= PERF_HES_UPTODATE; } } @@ -127,14 +112,15 @@ static int amd_uncore_add(struct perf_event *event, int flags) { int i; struct amd_uncore *uncore = event_to_amd_uncore(event); + struct amd_uncore_ctx *ctx = *per_cpu_ptr(uncore->ctx, event->cpu); struct hw_perf_event *hwc = &event->hw; /* are we already assigned? */ - if (hwc->idx != -1 && uncore->events[hwc->idx] == event) + if (hwc->idx != -1 && ctx->events[hwc->idx] == event) goto out; for (i = 0; i < uncore->num_counters; i++) { - if (uncore->events[i] == event) { + if (ctx->events[i] == event) { hwc->idx = i; goto out; } @@ -143,7 +129,7 @@ static int amd_uncore_add(struct perf_event *event, int flags) /* if not, take the first available counter */ hwc->idx = -1; for (i = 0; i < uncore->num_counters; i++) { - if (cmpxchg(&uncore->events[i], NULL, event) == NULL) { + if (cmpxchg(&ctx->events[i], NULL, event) == NULL) { hwc->idx = i; break; } @@ -158,18 +144,8 @@ static int amd_uncore_add(struct perf_event *event, int flags) hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; - /* - * The first four DF counters are accessible via RDPMC index 6 to 9 - * followed by the L3 counters from index 10 to 15. For processors - * with more than four DF counters, the DF RDPMC assignments become - * discontiguous as the additional counters are accessible starting - * from index 16. - */ - if (is_nb_event(event) && hwc->idx >= NUM_COUNTERS_NB) - hwc->event_base_rdpmc += NUM_COUNTERS_L3; - if (flags & PERF_EF_START) - amd_uncore_start(event, PERF_EF_RELOAD); + event->pmu->start(event, PERF_EF_RELOAD); return 0; } @@ -178,54 +154,35 @@ static void amd_uncore_del(struct perf_event *event, int flags) { int i; struct amd_uncore *uncore = event_to_amd_uncore(event); + struct amd_uncore_ctx *ctx = *per_cpu_ptr(uncore->ctx, event->cpu); struct hw_perf_event *hwc = &event->hw; - amd_uncore_stop(event, PERF_EF_UPDATE); + event->pmu->stop(event, PERF_EF_UPDATE); for (i = 0; i < uncore->num_counters; i++) { - if (cmpxchg(&uncore->events[i], event, NULL) == event) + if (cmpxchg(&ctx->events[i], event, NULL) == event) break; } hwc->idx = -1; } -/* - * Return a full thread and slice mask unless user - * has provided them - */ -static u64 l3_thread_slice_mask(u64 config) -{ - if (boot_cpu_data.x86 <= 0x18) - return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) | - ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK); - - /* - * If the user doesn't specify a threadmask, they're not trying to - * count core 0, so we enable all cores & threads. - * We'll also assume that they want to count slice 0 if they specify - * a threadmask and leave sliceid and enallslices unpopulated. - */ - if (!(config & AMD64_L3_F19H_THREAD_MASK)) - return AMD64_L3_F19H_THREAD_MASK | AMD64_L3_EN_ALL_SLICES | - AMD64_L3_EN_ALL_CORES; - - return config & (AMD64_L3_F19H_THREAD_MASK | AMD64_L3_SLICEID_MASK | - AMD64_L3_EN_ALL_CORES | AMD64_L3_EN_ALL_SLICES | - AMD64_L3_COREID_MASK); -} - static int amd_uncore_event_init(struct perf_event *event) { struct amd_uncore *uncore; + struct amd_uncore_ctx *ctx; struct hw_perf_event *hwc = &event->hw; - u64 event_mask = AMD64_RAW_EVENT_MASK_NB; if (event->attr.type != event->pmu->type) return -ENOENT; - if (pmu_version >= 2 && is_nb_event(event)) - event_mask = AMD64_PERFMON_V2_RAW_EVENT_MASK_NB; + if (event->cpu < 0) + return -EINVAL; + + uncore = event_to_amd_uncore(event); + ctx = *per_cpu_ptr(uncore->ctx, event->cpu); + if (!ctx) + return -ENODEV; /* * NB and Last level cache counters (MSRs) are shared across all cores @@ -235,28 +192,14 @@ static int amd_uncore_event_init(struct perf_event *event) * out. So we do not support sampling and per-thread events via * CAP_NO_INTERRUPT, and we do not enable counter overflow interrupts: */ - hwc->config = event->attr.config & event_mask; + hwc->config = event->attr.config; hwc->idx = -1; - if (event->cpu < 0) - return -EINVAL; - - /* - * SliceMask and ThreadMask need to be set for certain L3 events. - * For other events, the two fields do not affect the count. - */ - if (l3_mask && is_llc_event(event)) - hwc->config |= l3_thread_slice_mask(event->attr.config); - - uncore = event_to_amd_uncore(event); - if (!uncore) - return -ENODEV; - /* * since request can come in to any of the shared cores, we will remap * to a single common cpu. */ - event->cpu = uncore->cpu; + event->cpu = ctx->cpu; return 0; } @@ -278,17 +221,10 @@ static ssize_t amd_uncore_attr_show_cpumask(struct device *dev, struct device_attribute *attr, char *buf) { - cpumask_t *active_mask; struct pmu *pmu = dev_get_drvdata(dev); + struct amd_uncore *uncore = container_of(pmu, struct amd_uncore, pmu); - if (pmu->type == amd_nb_pmu.type) - active_mask = &amd_nb_active_mask; - else if (pmu->type == amd_llc_pmu.type) - active_mask = &amd_llc_active_mask; - else - return 0; - - return cpumap_print_to_pagebuf(true, buf, active_mask); + return cpumap_print_to_pagebuf(true, buf, &uncore->active_mask); } static DEVICE_ATTR(cpumask, S_IRUGO, amd_uncore_attr_show_cpumask, NULL); @@ -396,113 +332,57 @@ static const struct attribute_group *amd_uncore_l3_attr_update[] = { NULL, }; -static struct pmu amd_nb_pmu = { - .task_ctx_nr = perf_invalid_context, - .attr_groups = amd_uncore_df_attr_groups, - .name = "amd_nb", - .event_init = amd_uncore_event_init, - .add = amd_uncore_add, - .del = amd_uncore_del, - .start = amd_uncore_start, - .stop = amd_uncore_stop, - .read = amd_uncore_read, - .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, - .module = THIS_MODULE, -}; - -static struct pmu amd_llc_pmu = { - .task_ctx_nr = perf_invalid_context, - .attr_groups = amd_uncore_l3_attr_groups, - .attr_update = amd_uncore_l3_attr_update, - .name = "amd_l2", - .event_init = amd_uncore_event_init, - .add = amd_uncore_add, - .del = amd_uncore_del, - .start = amd_uncore_start, - .stop = amd_uncore_stop, - .read = amd_uncore_read, - .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, - .module = THIS_MODULE, -}; - -static struct amd_uncore *amd_uncore_alloc(unsigned int cpu) -{ - return kzalloc_node(sizeof(struct amd_uncore), GFP_KERNEL, - cpu_to_node(cpu)); -} - -static inline struct perf_event ** -amd_uncore_events_alloc(unsigned int num, unsigned int cpu) -{ - return kzalloc_node(sizeof(struct perf_event *) * num, GFP_KERNEL, - cpu_to_node(cpu)); -} - static int amd_uncore_cpu_up_prepare(unsigned int cpu) { - struct amd_uncore *uncore_nb = NULL, *uncore_llc = NULL; + struct amd_uncore *uncore; + struct amd_uncore_ctx *ctx; + int i; - if (amd_uncore_nb) { - *per_cpu_ptr(amd_uncore_nb, cpu) = NULL; - uncore_nb = amd_uncore_alloc(cpu); - if (!uncore_nb) - goto fail; - uncore_nb->cpu = cpu; - uncore_nb->num_counters = num_counters_nb; - uncore_nb->rdpmc_base = RDPMC_BASE_NB; - uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL; - uncore_nb->active_mask = &amd_nb_active_mask; - uncore_nb->pmu = &amd_nb_pmu; - uncore_nb->events = amd_uncore_events_alloc(num_counters_nb, cpu); - if (!uncore_nb->events) + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + *per_cpu_ptr(uncore->ctx, cpu) = NULL; + ctx = kzalloc_node(sizeof(struct amd_uncore_ctx), GFP_KERNEL, + cpu_to_node(cpu)); + if (!ctx) goto fail; - uncore_nb->id = -1; - *per_cpu_ptr(amd_uncore_nb, cpu) = uncore_nb; - } - if (amd_uncore_llc) { - *per_cpu_ptr(amd_uncore_llc, cpu) = NULL; - uncore_llc = amd_uncore_alloc(cpu); - if (!uncore_llc) - goto fail; - uncore_llc->cpu = cpu; - uncore_llc->num_counters = num_counters_llc; - uncore_llc->rdpmc_base = RDPMC_BASE_LLC; - uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL; - uncore_llc->active_mask = &amd_llc_active_mask; - uncore_llc->pmu = &amd_llc_pmu; - uncore_llc->events = amd_uncore_events_alloc(num_counters_llc, cpu); - if (!uncore_llc->events) + ctx->cpu = cpu; + ctx->events = kzalloc_node(sizeof(struct perf_event *) * + uncore->num_counters, GFP_KERNEL, + cpu_to_node(cpu)); + if (!ctx->events) goto fail; - uncore_llc->id = -1; - *per_cpu_ptr(amd_uncore_llc, cpu) = uncore_llc; + + ctx->id = -1; + *per_cpu_ptr(uncore->ctx, cpu) = ctx; } return 0; fail: - if (uncore_nb) { - kfree(uncore_nb->events); - kfree(uncore_nb); - } + /* Rollback */ + for (; i >= 0; i--) { + uncore = &uncores[i]; + ctx = *per_cpu_ptr(uncore->ctx, cpu); + if (!ctx) + continue; - if (uncore_llc) { - kfree(uncore_llc->events); - kfree(uncore_llc); + kfree(ctx->events); + kfree(ctx); } return -ENOMEM; } -static struct amd_uncore * -amd_uncore_find_online_sibling(struct amd_uncore *this, - struct amd_uncore * __percpu *uncores) +static struct amd_uncore_ctx * +amd_uncore_find_online_sibling(struct amd_uncore_ctx *this, + struct amd_uncore *uncore) { unsigned int cpu; - struct amd_uncore *that; + struct amd_uncore_ctx *that; for_each_online_cpu(cpu) { - that = *per_cpu_ptr(uncores, cpu); + that = *per_cpu_ptr(uncore->ctx, cpu); if (!that) continue; @@ -523,24 +403,16 @@ amd_uncore_find_online_sibling(struct amd_uncore *this, static int amd_uncore_cpu_starting(unsigned int cpu) { - unsigned int eax, ebx, ecx, edx; struct amd_uncore *uncore; + struct amd_uncore_ctx *ctx; + int i; - if (amd_uncore_nb) { - uncore = *per_cpu_ptr(amd_uncore_nb, cpu); - cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - uncore->id = ecx & 0xff; - - uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_nb); - *per_cpu_ptr(amd_uncore_nb, cpu) = uncore; - } - - if (amd_uncore_llc) { - uncore = *per_cpu_ptr(amd_uncore_llc, cpu); - uncore->id = get_llc_id(cpu); - - uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_llc); - *per_cpu_ptr(amd_uncore_llc, cpu) = uncore; + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + ctx = *per_cpu_ptr(uncore->ctx, cpu); + ctx->id = uncore->id(cpu); + ctx = amd_uncore_find_online_sibling(ctx, uncore); + *per_cpu_ptr(uncore->ctx, cpu) = ctx; } return 0; @@ -548,195 +420,359 @@ static int amd_uncore_cpu_starting(unsigned int cpu) static void uncore_clean_online(void) { - struct amd_uncore *uncore; + struct amd_uncore_ctx *ctx; struct hlist_node *n; - hlist_for_each_entry_safe(uncore, n, &uncore_unused_list, node) { - hlist_del(&uncore->node); - kfree(uncore->events); - kfree(uncore); + hlist_for_each_entry_safe(ctx, n, &uncore_unused_list, node) { + hlist_del(&ctx->node); + kfree(ctx->events); + kfree(ctx); } } -static void uncore_online(unsigned int cpu, - struct amd_uncore * __percpu *uncores) +static int amd_uncore_cpu_online(unsigned int cpu) { - struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu); + struct amd_uncore *uncore; + struct amd_uncore_ctx *ctx; + int i; uncore_clean_online(); - if (cpu == uncore->cpu) - cpumask_set_cpu(cpu, uncore->active_mask); + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + ctx = *per_cpu_ptr(uncore->ctx, cpu); + if (cpu == ctx->cpu) + cpumask_set_cpu(cpu, &uncore->active_mask); + } + + return 0; } -static int amd_uncore_cpu_online(unsigned int cpu) +static int amd_uncore_cpu_down_prepare(unsigned int cpu) { - if (amd_uncore_nb) - uncore_online(cpu, amd_uncore_nb); + struct amd_uncore_ctx *this, *that; + struct amd_uncore *uncore; + int i, j; + + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + this = *per_cpu_ptr(uncore->ctx, cpu); + + /* this cpu is going down, migrate to a shared sibling if possible */ + for_each_online_cpu(j) { + that = *per_cpu_ptr(uncore->ctx, j); + + if (cpu == j) + continue; + + if (this == that) { + perf_pmu_migrate_context(&uncore->pmu, cpu, j); + cpumask_clear_cpu(cpu, &uncore->active_mask); + cpumask_set_cpu(j, &uncore->active_mask); + that->cpu = j; + break; + } + } + } + + return 0; +} + +static int amd_uncore_cpu_dead(unsigned int cpu) +{ + struct amd_uncore_ctx *ctx; + struct amd_uncore *uncore; + int i; + + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + ctx = *per_cpu_ptr(uncore->ctx, cpu); + if (cpu == ctx->cpu) + cpumask_clear_cpu(cpu, &uncore->active_mask); + + if (!--ctx->refcnt) { + kfree(ctx->events); + kfree(ctx); + } - if (amd_uncore_llc) - uncore_online(cpu, amd_uncore_llc); + *per_cpu_ptr(uncore->ctx, cpu) = NULL; + } return 0; } -static void uncore_down_prepare(unsigned int cpu, - struct amd_uncore * __percpu *uncores) +static int amd_uncore_df_id(unsigned int cpu) { - unsigned int i; - struct amd_uncore *this = *per_cpu_ptr(uncores, cpu); + unsigned int eax, ebx, ecx, edx; - if (this->cpu != cpu) - return; + cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - /* this cpu is going down, migrate to a shared sibling if possible */ - for_each_online_cpu(i) { - struct amd_uncore *that = *per_cpu_ptr(uncores, i); + return ecx & 0xff; +} - if (cpu == i) - continue; +static int amd_uncore_df_event_init(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + int ret = amd_uncore_event_init(event); - if (this == that) { - perf_pmu_migrate_context(this->pmu, cpu, i); - cpumask_clear_cpu(cpu, that->active_mask); - cpumask_set_cpu(i, that->active_mask); - that->cpu = i; - break; - } - } + if (ret || pmu_version < 2) + return ret; + + hwc->config = event->attr.config & + (pmu_version >= 2 ? AMD64_PERFMON_V2_RAW_EVENT_MASK_NB : + AMD64_RAW_EVENT_MASK_NB); + + return 0; } -static int amd_uncore_cpu_down_prepare(unsigned int cpu) +static int amd_uncore_df_add(struct perf_event *event, int flags) { - if (amd_uncore_nb) - uncore_down_prepare(cpu, amd_uncore_nb); + int ret = amd_uncore_add(event, flags & ~PERF_EF_START); + struct hw_perf_event *hwc = &event->hw; + + if (ret) + return ret; - if (amd_uncore_llc) - uncore_down_prepare(cpu, amd_uncore_llc); + /* + * The first four DF counters are accessible via RDPMC index 6 to 9 + * followed by the L3 counters from index 10 to 15. For processors + * with more than four DF counters, the DF RDPMC assignments become + * discontiguous as the additional counters are accessible starting + * from index 16. + */ + if (hwc->idx >= NUM_COUNTERS_NB) + hwc->event_base_rdpmc += NUM_COUNTERS_L3; + + /* Delayed start after rdpmc base update */ + if (flags & PERF_EF_START) + amd_uncore_start(event, PERF_EF_RELOAD); return 0; } -static void uncore_dead(unsigned int cpu, struct amd_uncore * __percpu *uncores) +static int amd_uncore_df_init(void) { - struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu); + struct attribute **df_attr = amd_uncore_df_format_attr; + struct amd_uncore *uncore = &uncores[num_uncores]; + union cpuid_0x80000022_ebx ebx; + int ret; + + if (!boot_cpu_has(X86_FEATURE_PERFCTR_NB)) + return 0; - if (cpu == uncore->cpu) - cpumask_clear_cpu(cpu, uncore->active_mask); + /* + * For Family 17h and above, the Northbridge counters are repurposed + * as Data Fabric counters. The PMUs are exported based on family as + * either NB or DF. + */ + strncpy(uncore->name, boot_cpu_data.x86 >= 0x17 ? "amd_df" : "amd_nb", + sizeof(uncore->name)); + + uncore->num_counters = NUM_COUNTERS_NB; + uncore->msr_base = MSR_F15H_NB_PERF_CTL; + uncore->rdpmc_base = RDPMC_BASE_NB; + uncore->id = amd_uncore_df_id; + + if (pmu_version >= 2) { + *df_attr++ = &format_attr_event14v2.attr; + *df_attr++ = &format_attr_umask12.attr; + ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); + uncore->num_counters = ebx.split.num_df_pmc; + } else if (boot_cpu_data.x86 >= 0x17) { + *df_attr = &format_attr_event14.attr; + } - if (!--uncore->refcnt) { - kfree(uncore->events); - kfree(uncore); + uncore->ctx = alloc_percpu(struct amd_uncore_ctx *); + if (!uncore->ctx) + return -ENOMEM; + + uncore->pmu = (struct pmu) { + .task_ctx_nr = perf_invalid_context, + .attr_groups = amd_uncore_df_attr_groups, + .name = uncore->name, + .event_init = amd_uncore_df_event_init, + .add = amd_uncore_df_add, + .del = amd_uncore_del, + .start = amd_uncore_start, + .stop = amd_uncore_stop, + .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .module = THIS_MODULE, + }; + + ret = perf_pmu_register(&uncore->pmu, uncore->pmu.name, -1); + if (ret) { + free_percpu(uncore->ctx); + uncore->ctx = NULL; + return ret; } - *per_cpu_ptr(uncores, cpu) = NULL; + pr_info("%d %s %s counters detected\n", uncore->num_counters, + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ? "HYGON" : "", + uncore->pmu.name); + + num_uncores++; + + return 0; } -static int amd_uncore_cpu_dead(unsigned int cpu) +static int amd_uncore_l3_id(unsigned int cpu) +{ + return get_llc_id(cpu); +} + +static int amd_uncore_l3_event_init(struct perf_event *event) { - if (amd_uncore_nb) - uncore_dead(cpu, amd_uncore_nb); + int ret = amd_uncore_event_init(event); + struct hw_perf_event *hwc = &event->hw; + u64 config = event->attr.config; + u64 mask; + + hwc->config = config & AMD64_RAW_EVENT_MASK_NB; + + /* + * SliceMask and ThreadMask need to be set for certain L3 events. + * For other events, the two fields do not affect the count. + */ + if (ret || boot_cpu_data.x86 < 0x17) + return ret; + + mask = config & (AMD64_L3_F19H_THREAD_MASK | AMD64_L3_SLICEID_MASK | + AMD64_L3_EN_ALL_CORES | AMD64_L3_EN_ALL_SLICES | + AMD64_L3_COREID_MASK); + + if (boot_cpu_data.x86 <= 0x18) + mask = ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) | + ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK); - if (amd_uncore_llc) - uncore_dead(cpu, amd_uncore_llc); + /* + * If the user doesn't specify a ThreadMask, they're not trying to + * count core 0, so we enable all cores & threads. + * We'll also assume that they want to count slice 0 if they specify + * a ThreadMask and leave SliceId and EnAllSlices unpopulated. + */ + else if (!(config & AMD64_L3_F19H_THREAD_MASK)) + mask = AMD64_L3_F19H_THREAD_MASK | AMD64_L3_EN_ALL_SLICES | + AMD64_L3_EN_ALL_CORES; + + hwc->config |= mask; return 0; } -static int __init amd_uncore_init(void) +static int amd_uncore_l3_init(void) { - struct attribute **df_attr = amd_uncore_df_format_attr; struct attribute **l3_attr = amd_uncore_l3_format_attr; - union cpuid_0x80000022_ebx ebx; - int ret = -ENODEV; + struct amd_uncore *uncore = &uncores[num_uncores]; + int ret; - if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && - boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) - return -ENODEV; + if (!boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) + return 0; - if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) - return -ENODEV; + /* + * For Family 17h and above, L3 cache counters are available instead + * of L2 cache counters. The PMUs are exported based on family as + * either L2 or L3. + */ + strncpy(uncore->name, boot_cpu_data.x86 >= 0x17 ? "amd_l3" : "amd_l2", + sizeof(uncore->name)); - if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) - pmu_version = 2; + uncore->num_counters = NUM_COUNTERS_L2; + uncore->msr_base = MSR_F16H_L2I_PERF_CTL; + uncore->rdpmc_base = RDPMC_BASE_LLC; + uncore->id = amd_uncore_l3_id; - num_counters_nb = NUM_COUNTERS_NB; - num_counters_llc = NUM_COUNTERS_L2; if (boot_cpu_data.x86 >= 0x17) { - /* - * For F17h and above, the Northbridge counters are - * repurposed as Data Fabric counters. Also, L3 - * counters are supported too. The PMUs are exported - * based on family as either L2 or L3 and NB or DF. - */ - num_counters_llc = NUM_COUNTERS_L3; - amd_nb_pmu.name = "amd_df"; - amd_llc_pmu.name = "amd_l3"; - l3_mask = true; + *l3_attr++ = &format_attr_event8.attr; + *l3_attr++ = &format_attr_umask8.attr; + *l3_attr++ = boot_cpu_data.x86 >= 0x19 ? + &format_attr_threadmask2.attr : + &format_attr_threadmask8.attr; + uncore->num_counters = NUM_COUNTERS_L3; } - if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) { - if (pmu_version >= 2) { - *df_attr++ = &format_attr_event14v2.attr; - *df_attr++ = &format_attr_umask12.attr; - } else if (boot_cpu_data.x86 >= 0x17) { - *df_attr = &format_attr_event14.attr; - } + uncore->ctx = alloc_percpu(struct amd_uncore_ctx *); + if (!uncore->ctx) + return -ENOMEM; + + uncore->pmu = (struct pmu) { + .task_ctx_nr = perf_invalid_context, + .attr_groups = amd_uncore_l3_attr_groups, + .attr_update = amd_uncore_l3_attr_update, + .name = uncore->name, + .event_init = amd_uncore_l3_event_init, + .add = amd_uncore_add, + .del = amd_uncore_del, + .start = amd_uncore_start, + .stop = amd_uncore_stop, + .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .module = THIS_MODULE, + }; + + ret = perf_pmu_register(&uncore->pmu, uncore->pmu.name, -1); + if (ret) { + free_percpu(uncore->ctx); + uncore->ctx = NULL; + return ret; + } - amd_uncore_nb = alloc_percpu(struct amd_uncore *); - if (!amd_uncore_nb) { - ret = -ENOMEM; - goto fail_nb; - } - ret = perf_pmu_register(&amd_nb_pmu, amd_nb_pmu.name, -1); - if (ret) - goto fail_nb; + pr_info("%d %s %s counters detected\n", uncore->num_counters, + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ? "HYGON" : "", + uncore->pmu.name); - if (pmu_version >= 2) { - ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); - num_counters_nb = ebx.split.num_df_pmc; - } + num_uncores++; - pr_info("%d %s %s counters detected\n", num_counters_nb, - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ? "HYGON" : "", - amd_nb_pmu.name); + return 0; +} - ret = 0; - } +static void uncore_free(void) +{ + struct amd_uncore *uncore; + int i; - if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { - if (boot_cpu_data.x86 >= 0x19) { - *l3_attr++ = &format_attr_event8.attr; - *l3_attr++ = &format_attr_umask8.attr; - *l3_attr++ = &format_attr_threadmask2.attr; - } else if (boot_cpu_data.x86 >= 0x17) { - *l3_attr++ = &format_attr_event8.attr; - *l3_attr++ = &format_attr_umask8.attr; - *l3_attr++ = &format_attr_threadmask8.attr; - } + for (i = 0; i < num_uncores; i++) { + uncore = &uncores[i]; + if (!uncore->ctx) + continue; - amd_uncore_llc = alloc_percpu(struct amd_uncore *); - if (!amd_uncore_llc) { - ret = -ENOMEM; - goto fail_llc; - } - ret = perf_pmu_register(&amd_llc_pmu, amd_llc_pmu.name, -1); - if (ret) - goto fail_llc; - - pr_info("%d %s %s counters detected\n", num_counters_llc, - boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ? "HYGON" : "", - amd_llc_pmu.name); - ret = 0; + perf_pmu_unregister(&uncore->pmu); + free_percpu(uncore->ctx); + uncore->ctx = NULL; } + num_uncores = 0; +} + +static int __init amd_uncore_init(void) +{ + int ret; + + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) + return -ENODEV; + + if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) + return -ENODEV; + + if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) + pmu_version = 2; + + ret = amd_uncore_df_init(); + if (ret) + goto fail; + + ret = amd_uncore_l3_init(); + if (ret) + goto fail; + /* * Install callbacks. Core will call them for each online cpu. */ if (cpuhp_setup_state(CPUHP_PERF_X86_AMD_UNCORE_PREP, "perf/x86/amd/uncore:prepare", amd_uncore_cpu_up_prepare, amd_uncore_cpu_dead)) - goto fail_llc; + goto fail; if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, "perf/x86/amd/uncore:starting", @@ -753,12 +789,8 @@ static int __init amd_uncore_init(void) cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING); fail_prep: cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP); -fail_llc: - if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) - perf_pmu_unregister(&amd_nb_pmu); - free_percpu(amd_uncore_llc); -fail_nb: - free_percpu(amd_uncore_nb); +fail: + uncore_free(); return ret; } @@ -768,18 +800,7 @@ static void __exit amd_uncore_exit(void) cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE); cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING); cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP); - - if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC)) { - perf_pmu_unregister(&amd_llc_pmu); - free_percpu(amd_uncore_llc); - amd_uncore_llc = NULL; - } - - if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) { - perf_pmu_unregister(&amd_nb_pmu); - free_percpu(amd_uncore_nb); - amd_uncore_nb = NULL; - } + uncore_free(); } module_init(amd_uncore_init); From patchwork Wed Jul 19 06:55:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122419 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2249601vqt; Wed, 19 Jul 2023 00:04:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlHxjCHpFXJewxb7JRw2ukEicsgCW2rZGJXQGi197HatKEm6KE2H2RSsznmijZqGJ4A5fvRc X-Received: by 2002:a17:90a:3004:b0:265:8184:5903 with SMTP id g4-20020a17090a300400b0026581845903mr1097658pjb.40.1689750249962; Wed, 19 Jul 2023 00:04:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689750249; cv=pass; d=google.com; s=arc-20160816; b=Nqnx5nxQBmMjMaGMLON2Ag3FxdgLIQo61VWGUgflHGMbJLwurt8J/ztPc/oGGglBVE ZarcBnexrbMmQ4cG+teC7hoqAK6dE21BtaJX4A6rHVuIWe6IWTX5TrOrYOjOi9dSsNn6 rQ7Xdd1Wp0I4fGmX6dO9fzgGRLp4sKfeQrsCr2tMeUks0IXRsdsDaLUVZc9RQE3/IPFn ELs4MNwOaRaQyfgzrOgltU2iV22QS67GB+r1eqYEEcuB+d0wxdSimpRoOO8ukGS3mQiw jmGYtAWyXa/QFBb4Cafw4XU1UpVdMMk049gqdclRauXW2DoHCMvXYmeouTDSG2HrtoY9 F5Kg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9rV9NYaI5UnbQD2bHgUaC4mqjQ88OBPiQI4VdbSJBVE=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=Npb42USArrRF+j7qgw1BWP2moYJs2mocHMbZUyhBPgZSAcg9B9LJt2xiiwpXEQFCau Ps2DrZ8IfBiL0tpjZ85Fu37LArBfW/uGRnW5Dawg8pezr9Qr40cierNp9DVye7i9Mlim /iW32v42VgD9owBZviYDGNsd1/2ofg2z7CBJLJE2cw4AhvcTYhuQBmq0MiOb+H06nY8L GyM6EyB5OpGfjBdOg1fMfthV6Oj6gppAwE/WKnpDRQMxoJnJSS2QFAkHZ2QtR01oDmZc /rnAqlfJ+AVMaD9KCmAO9QevfcFotDZkfCk/JypkYm3bfp7/43tfaPt6e1G/y98zow1k pXFQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mIDu2e93; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y23-20020a17090a105700b00263c3a9855csi870771pjd.149.2023.07.19.00.03.54; Wed, 19 Jul 2023 00:04:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mIDu2e93; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231211AbjGSG5K (ORCPT + 99 others); Wed, 19 Jul 2023 02:57:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231259AbjGSG5I (ORCPT ); Wed, 19 Jul 2023 02:57:08 -0400 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2056.outbound.protection.outlook.com [40.107.100.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9347A1FCD; Tue, 18 Jul 2023 23:56:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=k8a5Ro7Vy22jGUiusISdhPFCZ00eacRsOQDVd6cdokTVl3crwf6TQvJ1oyLlVqLBKqfUx8KSfsfvWP6lPUhVJIX0f5nBxt3q9kMBYP+XJ4FUOJi6pX37PpTWYq+aM9JSUzMDUNd5it5WZ3ek89eBW/9lAvhFr2lqzUaIwnCxeK4ka6XAL+rlodghTL1uuaG5q/g6122egLFkbPC23T3FW9LoUfLYkZhRzCOCscf6+IR8Qsd/fUA/d9Pq5NMvQa09/BMxPvhj5a3PW5bJminrcCL0RsLW4Ggb24dBfDHXj4g9Az4RFZi6IJTvrBTXrhl8dF4WxAc0EvC56BKtws8AgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9rV9NYaI5UnbQD2bHgUaC4mqjQ88OBPiQI4VdbSJBVE=; b=TNpcMUjnoJASJskddpxzPIY0RhpcRjaD6xhBQnfokhAy+qrBl3twgwLVyBHKeSyhm47a433wMVIocIFYHDUmvdmhZgs0BxDbyCqGq0ZbWXEfJnSvbpxFnwKHUI8mfu7U4YUjK8K+uLekNjM0Hjyo0jbC8lUZ1W+YePgnmpB3WS4CprgXaWBeiDC/rdYOcOSml6NsCvRDVQMXeLFdVUjCdHdhRCW798xcHSoCg/rXTY7g9kFo+Hz/8aFvxH1oh+OG20lQpdjT7nEZ/ccAQ7WLCGYB8LloWcGiBkVSC78++KeTlv6im/6rNHeUAINEOLw2dQTMoeiHbMPavZwXRm9Rxw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9rV9NYaI5UnbQD2bHgUaC4mqjQ88OBPiQI4VdbSJBVE=; b=mIDu2e93PfPAYR31dvzhqUuKm8LyFnxwzQYwno20PYsiZDRjsBJMY4u0CsJFx+0Tx2zIcYLlv47Uwxh+At5g57M/X4rZTFh4IBu5KB1gQT2SIpLrPRwpdhCfpBsp/kN+2SGlupkaj/gfdzR7uoTHAjrNszbLU8WdNMlTb5mUV0o= Received: from BN9PR03CA0716.namprd03.prod.outlook.com (2603:10b6:408:ef::31) by MW4PR12MB6804.namprd12.prod.outlook.com (2603:10b6:303:20d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.32; Wed, 19 Jul 2023 06:56:55 +0000 Received: from BN8NAM11FT088.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ef:cafe::3c) by BN9PR03CA0716.outlook.office365.com (2603:10b6:408:ef::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.33 via Frontend Transport; Wed, 19 Jul 2023 06:56:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT088.mail.protection.outlook.com (10.13.177.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:56:54 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:56:48 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 2/6] perf/x86/amd/uncore: Use rdmsr if rdpmc is unavailable Date: Wed, 19 Jul 2023 12:25:37 +0530 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT088:EE_|MW4PR12MB6804:EE_ X-MS-Office365-Filtering-Correlation-Id: 37ab0781-7c32-4bb3-7124-08db88255652 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q23gPQJ3+2deyNACQ51Cn6LLM2ksAxGDdEvmQZLTVCrPSN2xlLKEE50Fq4kNCNh1nmveZAIb8EcHyp+jLT+CpGAsgAHBkOwK3r3replTaQ5LFRxxRSLc1QDFWEc5SaGWPdgcnKjeuhcYpn/La5WkxHhbkXawL4EI/BzZzpqVCVK0L9l2xCo2heTT2f8/h3S5WRFLj01fcE4g42aFVSgIPJLgblPi1Mkp5ygDCS2y5iaIe6f3mvk4q4E+C712n9sj/f/1raOV8s1wqH4l3I5Q2bFfCeP3jmFcitnNMB9BQzzxM2UscJbbpfLWdJ0CwwBxSCj3oST22htzg9M+qk+jYhMlpx+CA3p1MOTQL+zPwu/h9jGxlATfDASvTuxLhWlzNFlAMYJlTwvuaP/ObURDMUN1Y1Usj5f44fnZHexORxLpclL5pWob21DacXvpuS4xNAZTuPsMuGuSuLMnQ2CyksedX5ApyM3PKrLd/5lzRVL8jgpd0Gv5KatMaI5aGKNVwTghu86r57tvnjcqIT4Cmy7wB/ONeZYJL+o9t07FRB/iebgytbtwlTk4snrSYEfj7LTdtnmdRE21ayoQGjuAqs7yYGyQ4v9VBiOWNcrYFSLlQGgJRuybebQxB+OUdq95i67nG51im9v6Tg3Gs1B9mKBEVPIwjnFPV15+M0biUREPmK0XeT6oDFJxT4OcPLfEisoRxw6TkO+ktBWuPLQYW+oz5Yg8kpEiS5GnqsTjlmW4G0dbweiej9FtGMJ6CRL0b/KozUSTIzVfsxL0U0EbuA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(396003)(376002)(39860400002)(346002)(82310400008)(451199021)(40470700004)(36840700001)(46966006)(7416002)(8676002)(82740400003)(44832011)(41300700001)(86362001)(5660300002)(8936002)(4326008)(316002)(47076005)(83380400001)(426003)(2616005)(81166007)(356005)(70206006)(70586007)(2906002)(36756003)(110136005)(40460700003)(54906003)(478600001)(16526019)(6666004)(36860700001)(186003)(336012)(26005)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:56:54.6155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37ab0781-7c32-4bb3-7124-08db88255652 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6804 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771831557947849363 X-GMAIL-MSGID: 1771831557947849363 Not all uncore PMUs may support the use of the RDPMC instruction for reading counters. In such cases, read the count from the corresponding PERF_CTR register using the RDMSR instruction. Signed-off-by: Sandipan Das --- arch/x86/events/amd/uncore.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index b0afbe6d9eb4..f17df6574ba5 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -76,7 +76,16 @@ static void amd_uncore_read(struct perf_event *event) */ prev = local64_read(&hwc->prev_count); - rdpmcl(hwc->event_base_rdpmc, new); + + /* + * Some uncore PMUs do not have RDPMC assignments. In such cases, + * read counts directly from the corresponding PERF_CTR. + */ + if (hwc->event_base_rdpmc < 0) + rdmsrl(hwc->event_base, new); + else + rdpmcl(hwc->event_base_rdpmc, new); + local64_set(&hwc->prev_count, new); delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); delta >>= COUNTER_SHIFT; @@ -144,6 +153,9 @@ static int amd_uncore_add(struct perf_event *event, int flags) hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; + if (uncore->rdpmc_base < 0) + hwc->event_base_rdpmc = -1; + if (flags & PERF_EF_START) event->pmu->start(event, PERF_EF_RELOAD); From patchwork Wed Jul 19 06:55:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122418 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2249505vqt; Wed, 19 Jul 2023 00:03:59 -0700 (PDT) X-Google-Smtp-Source: APBJJlFsQoVbfQITE6Mf+DOnIS/QXfM7VjWFndkkESkGZXYQIablyIrCDNumv3y+Z2w6n46BolBg X-Received: by 2002:a05:6a20:918b:b0:132:ce08:1e28 with SMTP id v11-20020a056a20918b00b00132ce081e28mr1826854pzd.22.1689750239454; Wed, 19 Jul 2023 00:03:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689750239; cv=pass; d=google.com; s=arc-20160816; b=sGDyfqFo9LP0Bulx3Yjwl7cVQkooMPQrmX/7LjSWpo1m2B7uHl9HR0AnHAApXGmZ89 GKuBiUSuxQkX03qkRetMmY/76DAxswbgGX0w4PryD4yrZoUVDxQU26E0y99VRcH0mPn5 IudyzDcafmqkp7PZj+F8GgSf+3oEJzbr0XRoIKjrLCvg1BPlt6IZkGcZUpB9EWxP36bx iKkktIcNkWPD8cU9Pwqf8+MEKA+mvF6/8U3FLPKtkzxTVK9J8oFBDuzh/W6el4sEHKEY cniU1L3gy6Lqsv1vDWSf2FdZtK1qgDkSO/tbdGfwUonoz3Gy0Gv1MFQYjV8DQPacLfUw hbYA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=i9pe8Pz4uvzC9jXjKNl0tRB+NGLP0LTS2GUx/M/t2dw=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=nPTe+3rKuB9D4falH61e6PZ4UqCG2+V+zv4JYIvXUaXzXvx10LKl9TwetFKNTiWrvU vr/oLntVwidb5EpOKCIzh6Vf9wYD3/52mHYk8F+2Fkwc1RK5lSqpjYZ0YPOBg6rcENcp MyhEFyR9oYkTiCBeBIkQVpJ/GESUdBsllFWZlQd0A0DNozZyztbSLjkNpnH8W1dcRKBy drHWWuu8MddJSunkbA2Z1W2tVOeO1KWWl7sEOHdUydvPm/nbEm1N369m5liaTZraIf7y aaBkBFJfzhSC2Z7Ke8Ls1jgHXO4yQGhxxaXoQejKkE40HxqXMmimG9LeHDGfimzZbabR TDUA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mQQJ3nr8; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m68-20020a632647000000b0055b52ba0a00si2873893pgm.48.2023.07.19.00.03.45; Wed, 19 Jul 2023 00:03:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mQQJ3nr8; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231263AbjGSG5e (ORCPT + 99 others); Wed, 19 Jul 2023 02:57:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231218AbjGSG5c (ORCPT ); Wed, 19 Jul 2023 02:57:32 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2079.outbound.protection.outlook.com [40.107.223.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EDD41BFC; Tue, 18 Jul 2023 23:57:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EvoNr2IbS8DAH/bJRa9bJq8xRkEeI3Amt9Da+5uxl4G+NvsxTSmWXekG6Zv13xK+aiOAjWKoYneBX9mM86w8xvAcyeYA1c5z5MLNenF53R/xi4gbLK780N4idNrln/QOLkhibD2quxRZ6evnBVYS0lGVzJCRtM0YzMZI0NGWYFkRWoQM7Z6SfWGjjeVqLUGt38XD5f9kEIigtzVPeu1VDJP8dsXGaPRyUdQEAcrwr/bvEjZdOHSzRC5e3MzNfLlmjEw5YQA0XBSxrgt4WQx/8zXkqMscZSxEtTp+cRSWcbOcifq8diXOMzG2cvdO2HTdNC6IYW7Hbdp9xOVbOayL/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=i9pe8Pz4uvzC9jXjKNl0tRB+NGLP0LTS2GUx/M/t2dw=; b=oYQ2Cp0nksbi0DBCkreg8Bp7yAMcFXUbiFMDXW1noQ1MhfNoTJMTp4vwNWEU33FPBbLu1KfDxOjfzWxoWOqCLVnhcCYYzMQv86BgSeEpGk7aT+tWs+0znkzOAwli51caanPNlXIw0KObtPEh4WcgPziRor9Yi83Yk3BguXRHEygVK+09W577APpgnJHGenoYOi6/GYM4dtjdWIaXjfx/2W0KVqJUhI5vlxVTXPYaNqgvSasncjrqDvfqSO3UU19rKy0DBnkGDn140sKwBXMdRWYP9tz2yhQ0e2q6tUpKtuNAvs4xM6fZhcHMMHahkbOkHummInIwjux5vS49T1GnEQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=i9pe8Pz4uvzC9jXjKNl0tRB+NGLP0LTS2GUx/M/t2dw=; b=mQQJ3nr8V1TkYTKAAg1hHAQfwXs/1nhWdiCz9XD/RYgImdF8gSgwBJ4Fp3Q9kRVlTBZYs9tWijPRs+ln+seEQ6k6kDYD74JjwopGZyU6vuMRCh779uw85ozhgG8vtJ7LB9Wyc1TmYVnts0HzuGIzxwTruFy0DO4OKANzvbb1wtM= Received: from BN8PR15CA0027.namprd15.prod.outlook.com (2603:10b6:408:c0::40) by PH7PR12MB8153.namprd12.prod.outlook.com (2603:10b6:510:2b0::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6565.31; Wed, 19 Jul 2023 06:57:28 +0000 Received: from BN8NAM11FT062.eop-nam11.prod.protection.outlook.com (2603:10b6:408:c0:cafe::ce) by BN8PR15CA0027.outlook.office365.com (2603:10b6:408:c0::40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.24 via Frontend Transport; Wed, 19 Jul 2023 06:57:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT062.mail.protection.outlook.com (10.13.177.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:57:27 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:57:07 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 3/6] x86/cpuid: Add smp helper Date: Wed, 19 Jul 2023 12:25:38 +0530 Message-ID: <827723d8f506411700c68bccc5072ec8d918d2de.1689748843.git.sandipan.das@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT062:EE_|PH7PR12MB8153:EE_ X-MS-Office365-Filtering-Correlation-Id: dfdd8ef2-c606-4d12-499a-08db88256a18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bxj97Nqg+CKGgrgn4L3ee6CZDQz9Tesb5PSRlp4GBQYsuKidkZL4brSO35jxbDJVLgOKFjmOoSxeKy/qu8F5QVyASobLxeiOp7W0IqKgs2tN39T9ad4hqGzxqUgw+SGJ7kzXGPKBllu3KE+ZkOfKB883kqZFU6q7YoGqkXtxI8VDLDTj7tkVUHGmGW9EX+VbBzFR/hSnVefuN27YuZdM61b4/LkxK7M65gF/oyO6ryBJ8XvYFY6/Pkrn8eIzPywLa76WSjdfp4WNtTYlJke43a9oUQyuUB2D8lPrq0jTV6ude7MzTa0rk7asflqWplThAugqPnEgE2NJ3g9WOgkq2VPwSE12HtzMx5u/p4Jt4LnN6FR84bzRp8FMdGBElvWMGvYJ+2cZPt+gAvu0aCEkF9/gj7pN6rExuATT2CvDHqfszrVBeTpFmy31oIUKEAh3emOzIO5VxkmIwlwQDNKsFVqiynt9emezMTcqDTFta8qBkYULGGtXuCkpnEgDiu6aQ5VudyrjZOr8uDLH8SaOPT+lk8ht5Sib7YQ4uEPRB7znq4vnVwhhX0toLuaXwV9sBKSf+yKAZ7JJ+HB1UgiF7LEaiPeWUbBAQ4W1PXLFTYHzimpX67Gs4qY43WUvjeTOPH2W2jqm47xEKzthjMVNXGUOyiyI8BuUIvWspGD/GmnvBzv91E861xWI8DsSGsUWN6z1gvDAOa4NiYr5Y79utTatpEos1IMHCM4xn9aBCkeMiki7208MrgTzFVgjblnW9g3VL7av/t1Ii2U/bqnqdQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(346002)(39860400002)(396003)(82310400008)(451199021)(40470700004)(46966006)(36840700001)(40460700003)(82740400003)(2616005)(81166007)(83380400001)(44832011)(26005)(16526019)(426003)(36860700001)(336012)(5660300002)(47076005)(7416002)(2906002)(40480700001)(70206006)(478600001)(110136005)(36756003)(6666004)(54906003)(316002)(8676002)(86362001)(4326008)(186003)(8936002)(41300700001)(70586007)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:57:27.7732 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfdd8ef2-c606-4d12-499a-08db88256a18 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT062.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8153 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771831547064733833 X-GMAIL-MSGID: 1771831547064733833 Depending on which CPU the CPUID instruction is executed, some leaves can report different values. There are cases where it may be required to know all possible values. E.g. for AMD Zen 4 processors, the ActiveUmcMask field from leaf 0x80000022 ECX, which provides a way to determine the active memory controllers, can have different masks on CPUs belonging to different sockets as each socket can follow a different DIMM population scheme. Each memory channel is assigned a memory controller (UMC) and if no DIMMs are attached to a channel, the corresponding memory controller is inactive. There are performance monitoring counters exclusive to each memory controller which need to be represented under separate PMUs. So, it will be necessary to know the active memory controllers on each socket during the initialization of the UMC PMUs irrespective of where the uncore driver's module init runs. Add a new helper that executes CPUID on a particular CPU and returns the EAX, EBX, ECX and EDX values. Signed-off-by: Sandipan Das --- arch/x86/include/asm/cpuid.h | 14 ++++++++++++++ arch/x86/lib/Makefile | 2 +- arch/x86/lib/cpuid-smp.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 arch/x86/lib/cpuid-smp.c diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h index 9bee3e7bf973..17e74d4584f5 100644 --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -150,6 +150,20 @@ static __always_inline bool cpuid_function_is_indexed(u32 function) return false; } +#ifdef CONFIG_SMP +int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx); +#else /* CONFIG_SMP */ +static inline int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + cpuid(op, eax, ebx, ecx, edx); + return 0; +} +#endif /* CONFIG_SMP */ + #define for_each_possible_hypervisor_cpuid_base(function) \ for (function = 0x40000000; function < 0x40010000; function += 0x100) diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index ea3a28e7b613..e0097ae55edf 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -39,7 +39,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c clean-files := inat-tables.c -obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o +obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o cpuid-smp.o lib-y := delay.o misc.o cmdline.o cpu.o lib-y += usercopy_$(BITS).o usercopy.o getuser.o putuser.o diff --git a/arch/x86/lib/cpuid-smp.c b/arch/x86/lib/cpuid-smp.c new file mode 100644 index 000000000000..87340893ff61 --- /dev/null +++ b/arch/x86/lib/cpuid-smp.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +struct cpuid_info { + u32 op; + struct cpuid_regs regs; +}; + +static void __cpuid_smp(void *info) +{ + struct cpuid_info *rv = info; + + cpuid(rv->op, &rv->regs.eax, &rv->regs.ebx, &rv->regs.ecx, &rv->regs.edx); +} + +int cpuid_on_cpu(unsigned int cpu, unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + struct cpuid_info rv; + int err; + + memset(&rv, 0, sizeof(rv)); + + rv.op = op; + err = smp_call_function_single(cpu, __cpuid_smp, &rv, 1); + *eax = rv.regs.eax; + *ebx = rv.regs.ebx; + *ecx = rv.regs.ecx; + *edx = rv.regs.edx; + + return err; +} +EXPORT_SYMBOL(cpuid_on_cpu); From patchwork Wed Jul 19 06:55:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122428 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2258084vqt; Wed, 19 Jul 2023 00:22:42 -0700 (PDT) X-Google-Smtp-Source: APBJJlHYJfxQmFZ+0yi3+EVJDRgSP+1zr8h694FwZrBLqlayimxdCHVoFORg875acfVwMjpLzjH3 X-Received: by 2002:a05:6402:b19:b0:51e:1a3e:1a6 with SMTP id bm25-20020a0564020b1900b0051e1a3e01a6mr1730713edb.20.1689751361986; Wed, 19 Jul 2023 00:22:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689751361; cv=pass; d=google.com; s=arc-20160816; b=SlwjJ3Mb+dezvWza6tgqHKh6iEmE6FcIaahfN57JT8ma0WQLoaVM87f61m0xpwhAmX 10yaXCu0E5AlKkqJ2vGpy/HcnjJMLQv6nQnc4JdsB1M8AcQcKfUOfiKnOdvMR3f4cy0D yLnuOqNqXLYXD3UI+/Rxrgy+/gSjO6Q8Wos7R2dDNVNZaXOjhqGg07D9AZRrDaUMHlqS idABsLPbZH/OApPtDWwAQeLl+sFTqLV2LsJe8+giipQVHAz/2/709MwvPsrOle+8odYD QAWFSyWkEC3WO0qIccVveIZJmn6u3mdKK8TPeVQ5u3ly+sZ14GWG5CkFLDNe4OwKwKkX V9TQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=weOXGP6LbgDsIogCjgxThSVU9bQcyzHQ0DMmYFblQO0=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=hZ1BAZ9A/rSI6z3GFz7qzcgw333kAE+1PDa69Mkqo1I9McZpfDvvehTO+hBLKib1q9 wUrYZoP0yaWEyQ/9Tmx5PnO4n1LjwPXggx0GuiLoM6ogMbcdKPNn/5WuNJwZwepes6Vf nfj8HVeum6wvRTqwxg4C6viKYiI0pTAojGfwz2qRsm8IVi/LRYL4EhPXcx4YWK689M/s x0S5VsiOi2blIwiFIvfOvBxpK653rulgF7ZTSq6EUbjyIsumtIA4RZi7HkswNdYnzgUG Gi0NOiHIvtcQ40+wOoRx/E6hb8lLvsfWokHTteWkAQHMs4rthNSKKtkpEfAqP0nUWuiS 4hdw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=0Nvddeaq; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n8-20020aa7d048000000b0051e029af08esi2467862edo.371.2023.07.19.00.22.17; Wed, 19 Jul 2023 00:22:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=0Nvddeaq; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231269AbjGSG6D (ORCPT + 99 others); Wed, 19 Jul 2023 02:58:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231309AbjGSG6B (ORCPT ); Wed, 19 Jul 2023 02:58:01 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2046.outbound.protection.outlook.com [40.107.223.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBAC410A; Tue, 18 Jul 2023 23:57:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TixDvjc/li8L9p+h1L8MnqvFy1Dcsxtwy+9zH9OQN3MlZyFsVM4utyeQ3DysZ+3VV4oWiTVi+xcTxr71AXm7LcdA0/HKUYG9gob83stkffdWuVf59ZmeE6g1kTpXX12ye9n0Ejhk1R9tsmTttDvBosjSZRrzUgUHTV2e3OlTuNsXgdn5bG3VBxPuEvau3U5ScvkATPEKC4BSOMpp4u1dxfqba89qAIgF1pqaMt3L2uiQnGVfqI5XP9FVwOLKknsQ0PDRfZGgKUgjvtd5FtojFzlitWwhv45Y1jAyM/bKAtX+SCH8bti4UC5di/exfXH39VZ03dTN0EXXiJY+294spA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=weOXGP6LbgDsIogCjgxThSVU9bQcyzHQ0DMmYFblQO0=; b=jCSIhXzqEx8PE7RbqjPtK6g+FSlUVHyETNXbRq4SKlqSIUuauq3DXTM0dES9/hgxRPkhtMmZ3Bd79nFuOo0IOOzJLtaz49PbiZCeNoJf4hbCnS2u5dhL/Mq1GSUDkEbWaGxrPzYYK7n244bro2atUBmdXQzjjVMziZV5cuGONMkM0Qf0iAPr//Ywf3pvzK56+/CQGL57vrKHPzxDKcEVF9MMrtAK7i+RfQHk5frk1CR1qn9DBndrGEtRvaTDHSEahgtktq6AOe6WsSV6mo+n8ksvotvOh4d8KSkeMDGTzM9i398VbDIuziHsNe49wddUdSZ94ASZjw9Mc/+R/exEag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=weOXGP6LbgDsIogCjgxThSVU9bQcyzHQ0DMmYFblQO0=; b=0NvddeaqV/ikwRdRuFeIJSxiKHRUx0mrr9FLg8xvB+/ztkEX7YbDGnz45FROumd0ua9xF3xRM/UDYHdQsfGtajq2fb3M6A2ecN1LbeBZkL0OGA1KO1aCi4yguntVLixWF/SQ3iZUEkjeYDjm7722QH7dOcXbOnUEQp9Y+eU6/Is= Received: from BN9PR03CA0040.namprd03.prod.outlook.com (2603:10b6:408:fb::15) by PH0PR12MB5433.namprd12.prod.outlook.com (2603:10b6:510:e1::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.33; Wed, 19 Jul 2023 06:57:56 +0000 Received: from BN8NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:408:fb:cafe::62) by BN9PR03CA0040.outlook.office365.com (2603:10b6:408:fb::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.33 via Frontend Transport; Wed, 19 Jul 2023 06:57:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:57:55 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:57:34 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 4/6] perf/x86/amd/uncore: Add group exclusivity Date: Wed, 19 Jul 2023 12:25:39 +0530 Message-ID: <92465f174413553410aaa876223817b156808800.1689748843.git.sandipan.das@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|PH0PR12MB5433:EE_ X-MS-Office365-Filtering-Correlation-Id: 21d6f756-a901-416f-58e4-08db88257ae3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NDg8xIlRxe+wzbLHOvVSxiekiA3qN+JP9EAk0DKC9hL6JAQM74InQxspJh00UgfFmZkWONbupzDK5MGx4C7NlDZNiKXve28RJe+CUWNN6ceds0XtarE7peAW9vwjuLktiM5AOSMl5HxXmfd8m6s9hMNHMuZBB0wxI9hneVcxY1jIBm68yW17zFs/MCYpsXkNKq+WILma1bUSKMqnUmVtwQVY57dnz448oHLMvOLT0rLI7ZJ9Mj/s8HZgnJEl43IHB8hI5Xx08JxaEzDg6V0NMwdFNt109O4R3h6b2Il++pwgdO79q5GJ+I0nHh2yU1JZGUpj8pBm8WemrzrBth7NW/LEg7Nc46YMwCuUTgP7BUOVjaG0hHbkWHDHU2CH+bM7sFagAuMLhQrycVamMiT0gtDfJyhOu29UNZGxei9YKV/mrHgxZ0Ogx3IZ96Fe5dEQ8HUzS1XtVDipxZkW3IWfmA08dDMpQ7kv9CT7v8PpnUs8Yf+5iJhOoiRZThAwa0e5E8friXahvDVUH991uAuNvq543sEeciSOguOxH8rAuWrSSdi7V3ZLabOH0lkZ4LXYDK5udNOvxz5miK72635UxSpt36/LNyIn6AfHMqOFjnHG+9rjPJgc1RABkNkeZ9OOA8VktHGRe8sguS/r3pu3N9k2awwfwYgf4wOXIuE8ugNtIX4pBYmbn8XNQJAWgV2bJ1A9QlXCJRL7zp53LJemxBXymVEhSVDInZdangP9tJo6O9I49tB4hLZ7q3M3YOPzHpJdQE9W0jefWhxkKk6EDA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(376002)(136003)(396003)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(44832011)(478600001)(110136005)(54906003)(36860700001)(2616005)(83380400001)(426003)(47076005)(40460700003)(86362001)(36756003)(40480700001)(2906002)(70586007)(186003)(336012)(16526019)(26005)(356005)(82740400003)(81166007)(4326008)(70206006)(316002)(41300700001)(5660300002)(7416002)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:57:55.9475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21d6f756-a901-416f-58e4-08db88257ae3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5433 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771832723676820167 X-GMAIL-MSGID: 1771832723676820167 In some cases, it may be necessary to restrict opening PMU events to a subset of CPUs. Uncore PMUs which require this restriction can use the new group attribute in struct amd_uncore to set a valid uncore ID during initialization. In the starting phase of hotplug, the per-CPU context will be marked as unused if the ID in group does not match the uncore ID for the CPU that is being onlined. E.g. the Zen 4 memory controller (UMC) PMUs are specific to each active memory channel and the MSR address space for the PERF_CTL and PERF_CTR registers is reused on each socket. Thus, PMU events corresponding to a memory controller should only be opened on CPUs belonging to the socket associated with that memory controller. Signed-off-by: Sandipan Das --- arch/x86/events/amd/uncore.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index f17df6574ba5..6653e8e164bd 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -50,6 +50,7 @@ struct amd_uncore { int num_counters; int rdpmc_base; u32 msr_base; + int group; cpumask_t active_mask; struct pmu pmu; struct amd_uncore_ctx * __percpu *ctx; @@ -423,6 +424,17 @@ static int amd_uncore_cpu_starting(unsigned int cpu) uncore = &uncores[i]; ctx = *per_cpu_ptr(uncore->ctx, cpu); ctx->id = uncore->id(cpu); + + /* + * Reclaim the context if events can only be opened by CPUs + * within the same group + */ + if (uncore->group >= 0 && ctx->id != uncore->group) { + hlist_add_head(&ctx->node, &uncore_unused_list); + *per_cpu_ptr(uncore->ctx, cpu) = NULL; + continue; + } + ctx = amd_uncore_find_online_sibling(ctx, uncore); *per_cpu_ptr(uncore->ctx, cpu) = ctx; } @@ -453,7 +465,7 @@ static int amd_uncore_cpu_online(unsigned int cpu) for (i = 0; i < num_uncores; i++) { uncore = &uncores[i]; ctx = *per_cpu_ptr(uncore->ctx, cpu); - if (cpu == ctx->cpu) + if (ctx && cpu == ctx->cpu) cpumask_set_cpu(cpu, &uncore->active_mask); } @@ -469,12 +481,14 @@ static int amd_uncore_cpu_down_prepare(unsigned int cpu) for (i = 0; i < num_uncores; i++) { uncore = &uncores[i]; this = *per_cpu_ptr(uncore->ctx, cpu); + if (!this) + continue; /* this cpu is going down, migrate to a shared sibling if possible */ for_each_online_cpu(j) { that = *per_cpu_ptr(uncore->ctx, j); - if (cpu == j) + if (!that || cpu == j) continue; if (this == that) { @@ -499,6 +513,9 @@ static int amd_uncore_cpu_dead(unsigned int cpu) for (i = 0; i < num_uncores; i++) { uncore = &uncores[i]; ctx = *per_cpu_ptr(uncore->ctx, cpu); + if (!ctx) + continue; + if (cpu == ctx->cpu) cpumask_clear_cpu(cpu, &uncore->active_mask); @@ -584,6 +601,7 @@ static int amd_uncore_df_init(void) uncore->msr_base = MSR_F15H_NB_PERF_CTL; uncore->rdpmc_base = RDPMC_BASE_NB; uncore->id = amd_uncore_df_id; + uncore->group = -1; if (pmu_version >= 2) { *df_attr++ = &format_attr_event14v2.attr; @@ -693,6 +711,7 @@ static int amd_uncore_l3_init(void) uncore->msr_base = MSR_F16H_L2I_PERF_CTL; uncore->rdpmc_base = RDPMC_BASE_LLC; uncore->id = amd_uncore_l3_id; + uncore->group = -1; if (boot_cpu_data.x86 >= 0x17) { *l3_attr++ = &format_attr_event8.attr; From patchwork Wed Jul 19 06:55:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2251631vqt; Wed, 19 Jul 2023 00:08:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlHwA8A+vQ5n7iV5rduDlh/HsDeHXkaeEwPAOa3OkiQnRcEc3XMHLd3TC8HmkelQrgz8x3nS X-Received: by 2002:a05:6a00:cd4:b0:668:9bf9:fa70 with SMTP id b20-20020a056a000cd400b006689bf9fa70mr18938803pfv.34.1689750519606; Wed, 19 Jul 2023 00:08:39 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689750519; cv=pass; d=google.com; s=arc-20160816; b=WZpxYiGU7Y5lB2uTTZvZTkR6P9L9N6qy+NPtddh3Skdwrk4oJmMFnEZGfCi1xQ9CeE X5uipkem5WRKk6+9/Z0iEeQYJS0vtq1USsT7DWpiqY78g3gMOquKCS7n0LdK8na+/Ikw TYqgBKpq0shY80bvAcsPKzlYORZ+fBxx2Wa52WNkWTUt4HO3W2w6h5AvA8cjIBNhWdKp HFAzMoZ/dilVFGkpKwUAbMZPDCZ9ol/3cKBABa0hIPHbbHAaJ6ISACf4MpJRnuR43p3h 91Vk0YJRfTidJJvFd/+cpTp91+WpcZ+fUZAXQ0+GztwOqbdrWsBlXex85ik5qBW8GHs5 hlNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ucIt6usfVwa5iVw1cbvicaBXZykmgyDVLlRaZolSXns=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=vD8npYFwosiJVuOSmYPEKhQ0lUJYzIP/dCHifWZj3IjMmW7rtF0F0nd8Ucw23yUApu 3pgVO0hipj5W09CDbm6tOuZ1i22Jbb2QeQaqAUDannfTiztq6OeA3CX1o1w+efg4nlkK 14+Ui8/uUg6vReP8h7sPtFl+znuewYo8LIHCDMa1KZ6Res3VnV/7QAclsmgUFsRWq/Ic oIp66GAvgNNXqT15GHV2I1iex+RSuKPjxkR4LeCXT+EML+Axic3BkGaF2A+raeqKVDkN bdE0JRBPlkEZ6ZV0FU87zTXfvZpNm3c5Z/OZTFiIExHa5HhaTnk0uxfYXxVXyyzrVEY0 BM+A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="Q76T2t6/"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d7-20020a631d07000000b0054f93b261cfsi2748240pgd.88.2023.07.19.00.08.25; Wed, 19 Jul 2023 00:08:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="Q76T2t6/"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231301AbjGSG6d (ORCPT + 99 others); Wed, 19 Jul 2023 02:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbjGSG6b (ORCPT ); Wed, 19 Jul 2023 02:58:31 -0400 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2043.outbound.protection.outlook.com [40.107.101.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 986DE1FE8; Tue, 18 Jul 2023 23:58:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dfHKxgaygwFdJ4xk0wLUrj8CerTv3gNWtD6yidcxSWL9jn+ho2Gi1s3kWO8teb3hrAz2i9smJAq+Y1vMcOYHfatNkctWVwBH0tXX6cN8ijYeCbrR/y5stxqLxjaM79IsFpT/wtqdK48T/dAoIRN+H4JjPD2uD8G4NgWILJFn6hQbIYoi9bbSvHBxJIxnEK0C6lQDG6SFDklIGmfCXBjboO4UmwzUfSA6jNbMS1mRcxF8T2W13wr5QtN/M9dD00GyXzp0E2UMMnqGzg9GYXHdFhw3HPn6su1TZa+2jIY03t2emjV7ka42l7LRccRWWGM3aMD+NmVO9tKV7ZxLKOE4pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ucIt6usfVwa5iVw1cbvicaBXZykmgyDVLlRaZolSXns=; b=PaibzPJRNAS2fDyoJQerUPfVVOAeakKQXxLHvPIwvAkbd63dDS6sP7RoHznMAUSQi0nj9RD9ph8HIv8TpfBh6ohl5kpNPAcM2bFx9gZVfIPHXfbz5J+4+xhPfWQVLcw/8b1XLbRVIUJ5gbyPFl2r/G/WONNbKsUNykzmLlgdjfWZALutNXBv/35a5Ds3YaGr8v3/ISf2GUPomibOBRjFVJrn/SIdxVVfDoANiHdg9VTf8Z1x9x2q2EYpjGnmcHWPt1Yq3MquTYNEkeV/MPnCcWv43gCq1GxyIew2oX4S7mn4uqS+DYdTjmNdVACGzQ6YOdu0packFNO62KNROsv2DA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ucIt6usfVwa5iVw1cbvicaBXZykmgyDVLlRaZolSXns=; b=Q76T2t6/LBpR17f9740r0sZcCT6HhsXJXilX/R5cfgj7SkuDUngEMLz3HLTYnimGoHVOCRhyQXB9sKhJVFB5x6N7HwaXhkebM2pfS7V/AVEFBwY5uDGbt2PI6D6oodvqlso8TFQGPiR8Q3WMAj9iZArbO9DS0ReFxag1/6XR9L0= Received: from BN8PR16CA0001.namprd16.prod.outlook.com (2603:10b6:408:4c::14) by BL1PR12MB5377.namprd12.prod.outlook.com (2603:10b6:208:31f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.24; Wed, 19 Jul 2023 06:58:24 +0000 Received: from BN8NAM11FT005.eop-nam11.prod.protection.outlook.com (2603:10b6:408:4c:cafe::c5) by BN8PR16CA0001.outlook.office365.com (2603:10b6:408:4c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.23 via Frontend Transport; Wed, 19 Jul 2023 06:58:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT005.mail.protection.outlook.com (10.13.176.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:58:24 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:58:08 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 5/6] perf/x86/amd/uncore: Add memory controller support Date: Wed, 19 Jul 2023 12:25:40 +0530 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT005:EE_|BL1PR12MB5377:EE_ X-MS-Office365-Filtering-Correlation-Id: f0c60716-27f1-44c0-c0e9-08db88258bfb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EB53PlUB60UEEetLWRMUb0jH7xb0rXi+qo3xWu3FVbFRv89SIGNBGdErfT/tEw207Vg75km7A5fvCiaQPVylz3f2e6opPCElNu6Sld9EsO6y0cAcEOgsemrXnGNCC+o+7CcdiJUgmHkV38fLuNEZSSN3DZ1oQxiEHsgZfIO94dwnzOdBznL+R0MjQefaHJNuCZPDaDLdA7HFfhQYi2Rv71Deu+TjtOYqid4S5pXBcrRqrpvzOcEn/2Wi7ryxc2kMDl+WwBhYjL9LnOFupNvkapQffP4mp+lw0vu2ahckQsGsTYyBsTS92wWI30dmONlfxqa3OMBfIm/iY028AkQjfU333Vas09Hh1HjZ0P3xbrhjeV6fXmIGbIURhsy3CUUNdhhROpXrijzv3pwQ/NN1OUrNy/OeQ4ySOdGbw0xTQWyhiEfB1P8THo2wasSNVLxpTdhp469h/t5+p4gRRxPbO8WxEQnIdc9Buuf1YvTrbUkGWMMHJeFNcGn6hXb1gSKJXsRmO6Xg6CiRMFaLPtx6jd0Dro9j5skTak4o8tV8Hm7sV1aDJHOiwaLrRfxfWpywzJSea0boxg44MTPaiJhTCed0cOSlNqVSPkjkIJcPgWw9ncSO8Qd6T0Nk9LExhIyKJDJQlvRyn7HgzQNQ26YA9eaZNpS6So90s97fnL2mLF01uAjb336Da2BNt1eLM7m7zgX1k4fsuxT/s6sAUqSdBjATNKPVGxgKUR8kbwO5A3JMqPad9+fzIprbhvDvL42NuHDHXLPyhlsotBSNJmc4Kw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(376002)(39860400002)(136003)(82310400008)(451199021)(36840700001)(40470700004)(46966006)(6666004)(478600001)(54906003)(110136005)(336012)(186003)(16526019)(26005)(82740400003)(2906002)(30864003)(316002)(41300700001)(4326008)(70586007)(70206006)(5660300002)(7416002)(8936002)(8676002)(44832011)(81166007)(356005)(86362001)(40460700003)(36756003)(36860700001)(426003)(2616005)(83380400001)(47076005)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:58:24.6287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0c60716-27f1-44c0-c0e9-08db88258bfb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5377 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771831840831401080 X-GMAIL-MSGID: 1771831840831401080 Unified Memory Controller (UMC) events were introduced with Zen 4 as a part of the Performance Monitoring Version 2 (PerfMonV2) enhancements. An event is specified using the EventSelect bits and the RdWrMask bits can be used for additional filtering of reads and writes. As of now, a maximum of 12 channels of DDR5 are available on each socket and each channel controlled by a dedicated UMC. Each UMC has it own set of counters. Since the MSR address space for the UMC PERF_CTL and PERF_CTR registers are reused across sockets, uncore groups are created on the basis of socket IDs. Hence, group exclusivity is mandatory while opening events so that events for an UMC can only be opened on CPUs which are the same socket as the corresponding memory channel. For each socket, the total number of available UMC counters and active memory channels are determined from CPUID leaf 0x80000022 EBX and ECX respectively. Usually, on Zen 4, each UMC gets 4 counters. MSR assignments are determined on the basis of active UMCs. E.g. if UMCs 1, 4 and 9 are active for a given socket, then * UMC 1 gets MSRs 0xc0010800 to 0xc0010807 as PERF_CTLs and PERF_CTRs * UMC 4 gets MSRs 0xc0010808 to 0xc001080f as PERF_CTLs and PERF_CTRs * UMC 9 gets MSRs 0xc0010810 to 0xc0010817 as PERF_CTLs and PERF_CTRs Memory channels are generally labelled using alphabets and the mapping of UMCs to memory channels is dependent on the family and model. This information can be found in the "UMC and DDR Phy Logical Mapping" section of the AMD Processor Programming Reference (PPR). If there are sockets without any online CPUs when the amd_uncore driver is loaded, UMCs for such sockets will not be discoverable since the mechanism relies on executing the CPUID instruction on an online CPU from the socket. Signed-off-by: Sandipan Das --- arch/x86/events/amd/uncore.c | 171 +++++++++++++++++++++++++++++- arch/x86/include/asm/msr-index.h | 4 + arch/x86/include/asm/perf_event.h | 9 ++ 3 files changed, 182 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 6653e8e164bd..c3e1bddd4e1b 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -27,7 +27,12 @@ #define COUNTER_SHIFT 16 -#define NUM_UNCORES_MAX 2 /* DF (or NB) and L3 (or L2) */ +/* + * While DF (or NB) and L3 (or L2) PMUs have a single instance, there may be + * multiple UMC PMUs, each corresponding to active memory channels across all + * sockets. + */ +#define NUM_UNCORES_MAX 64 #define UNCORE_NAME_LEN 16 #undef pr_fmt @@ -264,7 +269,7 @@ static struct device_attribute format_attr_##_var = \ DEFINE_UNCORE_FORMAT_ATTR(event12, event, "config:0-7,32-35"); DEFINE_UNCORE_FORMAT_ATTR(event14, event, "config:0-7,32-35,59-60"); /* F17h+ DF */ DEFINE_UNCORE_FORMAT_ATTR(event14v2, event, "config:0-7,32-37"); /* PerfMonV2 DF */ -DEFINE_UNCORE_FORMAT_ATTR(event8, event, "config:0-7"); /* F17h+ L3 */ +DEFINE_UNCORE_FORMAT_ATTR(event8, event, "config:0-7"); /* F17h+ L3, PerfMonV2 UMC */ DEFINE_UNCORE_FORMAT_ATTR(umask8, umask, "config:8-15"); DEFINE_UNCORE_FORMAT_ATTR(umask12, umask, "config:8-15,24-27"); /* PerfMonV2 DF */ DEFINE_UNCORE_FORMAT_ATTR(coreid, coreid, "config:42-44"); /* F19h L3 */ @@ -274,6 +279,7 @@ DEFINE_UNCORE_FORMAT_ATTR(threadmask2, threadmask, "config:56-57"); /* F19h L DEFINE_UNCORE_FORMAT_ATTR(enallslices, enallslices, "config:46"); /* F19h L3 */ DEFINE_UNCORE_FORMAT_ATTR(enallcores, enallcores, "config:47"); /* F19h L3 */ DEFINE_UNCORE_FORMAT_ATTR(sliceid, sliceid, "config:48-50"); /* F19h L3 */ +DEFINE_UNCORE_FORMAT_ATTR(rdwrmask, rdwrmask, "config:8-9"); /* PerfMonV2 UMC */ /* Common DF and NB attributes */ static struct attribute *amd_uncore_df_format_attr[] = { @@ -305,6 +311,13 @@ static struct attribute *amd_f19h_uncore_l3_format_attr[] = { NULL, }; +/* Common UMC attributes */ +static struct attribute *amd_uncore_umc_format_attr[] = { + &format_attr_event8.attr, /* event */ + &format_attr_rdwrmask.attr, /* rdwrmask */ + NULL, +}; + static struct attribute_group amd_uncore_df_format_group = { .name = "format", .attrs = amd_uncore_df_format_attr, @@ -327,6 +340,11 @@ static struct attribute_group amd_f19h_uncore_l3_format_group = { .is_visible = amd_f19h_uncore_is_visible, }; +static struct attribute_group amd_uncore_umc_format_group = { + .name = "format", + .attrs = amd_uncore_umc_format_attr, +}; + static const struct attribute_group *amd_uncore_df_attr_groups[] = { &amd_uncore_attr_group, &amd_uncore_df_format_group, @@ -345,6 +363,12 @@ static const struct attribute_group *amd_uncore_l3_attr_update[] = { NULL, }; +static const struct attribute_group *amd_uncore_umc_attr_groups[] = { + &amd_uncore_attr_group, + &amd_uncore_umc_format_group, + NULL, +}; + static int amd_uncore_cpu_up_prepare(unsigned int cpu) { struct amd_uncore *uncore; @@ -757,6 +781,145 @@ static int amd_uncore_l3_init(void) return 0; } +static int amd_uncore_umc_id(unsigned int cpu) +{ + return topology_die_id(cpu); +} + +static int amd_uncore_umc_event_init(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + int ret = amd_uncore_event_init(event); + + if (ret) + return ret; + + hwc->config = event->attr.config & AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC; + + return 0; +} + +static void amd_uncore_umc_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + + if (flags & PERF_EF_RELOAD) + wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); + + hwc->state = 0; + wrmsrl(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); + perf_event_update_userpage(event); +} + +static int amd_uncore_umc_init(void) +{ + unsigned int cpu, eax, ecx, edx; + union cpuid_0x80000022_ebx ebx; + struct amd_uncore *uncore; + int umc_idx = 0, group_id, group_num_umc, group_umc_idx, ret, i; + DECLARE_BITMAP(group_mask, NUM_UNCORES_MAX) = { 0 }; + + if (pmu_version < 2) + return 0; + + /* + * Each group of memory controllers can have an unique configuration + * based on the DIMM population scheme. If all CPUs associated with a + * group of memory channels are offline, the corresponding UMC PMUs + * will not be initialized since they are only discoverable via CPUID. + */ + for_each_online_cpu(cpu) { + group_id = amd_uncore_umc_id(cpu); + + /* Check if this group has already been discovered */ + if (test_bit(group_id, group_mask)) + continue; + + __set_bit(group_id, group_mask); + ret = cpuid_on_cpu(cpu, EXT_PERFMON_DEBUG_FEATURES, &eax, + &ebx.full, &ecx, &edx); + if (ret) + goto fail; + + group_umc_idx = 0; + group_num_umc = hweight32(ecx); + + /* + * There are more PMUs than anticipated and the max array size + * needs to be increased to accommodate them + */ + if ((num_uncores + umc_idx + group_num_umc) > NUM_UNCORES_MAX) { + WARN(1, "some uncore PMUs cannot be initialized"); + break; + } + + /* Create PMUs for active UMCs in the current group */ + for (i = 0; i < 32; i++) { + if (!(ecx & BIT(i))) + continue; + + uncore = &uncores[num_uncores + umc_idx]; + snprintf(uncore->name, sizeof(uncore->name), "amd_umc_%d", umc_idx); + uncore->num_counters = ebx.split.num_umc_pmc / group_num_umc; + uncore->msr_base = MSR_F19H_UMC_PERF_CTL + group_umc_idx * uncore->num_counters * 2; + uncore->rdpmc_base = -1; + uncore->id = amd_uncore_umc_id; + uncore->group = group_id; + + uncore->ctx = alloc_percpu(struct amd_uncore_ctx *); + if (!uncore->ctx) { + ret = -ENOMEM; + goto fail; + } + + uncore->pmu = (struct pmu) { + .task_ctx_nr = perf_invalid_context, + .attr_groups = amd_uncore_umc_attr_groups, + .name = uncore->name, + .event_init = amd_uncore_umc_event_init, + .add = amd_uncore_add, + .del = amd_uncore_del, + .start = amd_uncore_umc_start, + .stop = amd_uncore_stop, + .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .module = THIS_MODULE, + }; + + ret = perf_pmu_register(&uncore->pmu, uncore->pmu.name, -1); + if (ret) { + free_percpu(uncore->ctx); + uncore->ctx = NULL; + goto fail; + } + + pr_info("%d %s %s counters detected\n", uncore->num_counters, + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ? "HYGON" : "", + uncore->pmu.name); + + umc_idx++; + group_umc_idx++; + } + } + + num_uncores += umc_idx; + + return 0; + +fail: + for (i = 0; i < umc_idx; i++) { + uncore = &uncores[num_uncores + i]; + if (!uncore->ctx) + continue; + + perf_pmu_unregister(&uncore->pmu); + free_percpu(uncore->ctx); + uncore->ctx = NULL; + } + + return ret; +} + static void uncore_free(void) { struct amd_uncore *uncore; @@ -797,6 +960,10 @@ static int __init amd_uncore_init(void) if (ret) goto fail; + ret = amd_uncore_umc_init(); + if (ret) + goto fail; + /* * Install callbacks. Core will call them for each online cpu. */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3aedae61af4f..bfcc72b20f54 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -624,6 +624,10 @@ /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e +/* Fam 19h MSRs */ +#define MSR_F19H_UMC_PERF_CTL 0xc0010800 +#define MSR_F19H_UMC_PERF_CTR 0xc0010801 + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 85a9fd5a3ec3..2618ec7c3d1d 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -112,6 +112,13 @@ (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \ AMD64_PERFMON_V2_EVENTSEL_UMASK_NB) +#define AMD64_PERFMON_V2_ENABLE_UMC BIT_ULL(31) +#define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0) +#define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC GENMASK_ULL(9, 8) +#define AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC \ + (AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC | \ + AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC) + #define AMD64_NUM_COUNTERS 4 #define AMD64_NUM_COUNTERS_CORE 6 #define AMD64_NUM_COUNTERS_NB 4 @@ -232,6 +239,8 @@ union cpuid_0x80000022_ebx { unsigned int lbr_v2_stack_sz:6; /* Number of Data Fabric Counters */ unsigned int num_df_pmc:6; + /* Number of Unified Memory Controller Counters */ + unsigned int num_umc_pmc:6; } split; unsigned int full; }; From patchwork Wed Jul 19 06:55:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Das X-Patchwork-Id: 122429 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp2258335vqt; Wed, 19 Jul 2023 00:23:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlEylXjzWDfKMB3F+wPZQmLkdJ5Yh3juRqvFmKWq5Fp6UYgvdZJ0fGu0iwV1vyhai2y5G9U/ X-Received: by 2002:a17:906:2101:b0:991:f7cb:cc3d with SMTP id 1-20020a170906210100b00991f7cbcc3dmr1557597ejt.65.1689751396409; Wed, 19 Jul 2023 00:23:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689751396; cv=pass; d=google.com; s=arc-20160816; b=L0UujD8hf6q0yXa4G4hus/ZZ/WRW4wT2sK4grLaI1pN8X61Z43byhp0rcIj2IFF/mI BqehtjBcNETYp2hSv5GF8G0lWBHborwXJQA8kFp9YQGY0ZKW6e7jzv9ePfE0VNu7/T9U A+a/9Xp0CVikchal4wxhvax4gIgrZmYkE2u3Q4YqTFSyX/myhBvVmqnZufIlmM4OsRBX E2mkW9xyS6HAJru1IxtOJdCoqhMfiqwNwINzgTkey8coF4XU4dmfTree2HDZ92/+dm00 cJIJ0/qlWbeuLeLFNdIL+IqPA+IZPyNA6Hd8Ag71d8GBuioLrVEdlEuODNIDypeZHhE8 jqlg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=shJYfo5HPR96g5uSryEucrv1t0iGShZOy9dV1NlVuB0=; fh=MKSgTbUakCCNPtZUo6Oc2ve/v653ST1LDQFwDKrjRaI=; b=Oyf+q/vVpI34EUJF1vJ7NxeXGbbT1uVFKfNirtUZOm/xpn16HlCkfFHQYjfF9ZJRv2 2OyoPknfNWfCTR+KhqnHHcAPYy/1U+31Xt1PNaJQR+k2tgJUxirC6y4m/H5WSxe1d40a kqUbUHsfUeig8nPyJ/RffKvOBLGnK0lAipzYwDiaYbqgsXQFiO2iM1QKByL8mSs3Tg6Y b2v96C2xgqLQpZ21lC23MJYEQpPOhr+xdBScNUk8BEdcJ7zeqnV9v6pDpccy++2sCR8a +M2LTu+LQ8TqfgXzF+oMw6jp3cllI5hK9Me3+H5nV288WMNlqDMwRyPK0kColqlCx46f vzBg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=IFGqHPRC; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k10-20020a1709065fca00b009932528281asi2452391ejv.579.2023.07.19.00.22.52; Wed, 19 Jul 2023 00:23:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=IFGqHPRC; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231289AbjGSG66 (ORCPT + 99 others); Wed, 19 Jul 2023 02:58:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231273AbjGSG6y (ORCPT ); Wed, 19 Jul 2023 02:58:54 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on20600.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5a::600]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFBDC1735; Tue, 18 Jul 2023 23:58:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kNd6udUw+vPC0cn36IleM8galdcx0NCQEReh1WK1WsYWGhjbu3FaqqHR83IlERKFnsGKC9ohu2lFEoHrJkgcxXrZvNiCP/P5Ht4tiPPEtBArZaLIsN974NBQFl1T8/SwzTMxGhujP5RmvrpMBauy48mQesoBgDkG5aoH1rVn417Qthi+W62r6L4VSMcLQeEhh8YFp+35I8taUF8dri8USOzf1NBaNbQLeyKmjnYUoI5a1uX5nXW4WmnYqkCQgaVDsD/KiR/4BQBOApDT+T2ifQt2B/QWbOpKx3rsJ3PvSkR/WpNSM1aPFkSROhOVKZLjZ73zXWxK0krGnpMISNys+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=shJYfo5HPR96g5uSryEucrv1t0iGShZOy9dV1NlVuB0=; b=l6o+HpFjmvtMlf6SUq0Tx30U6Qnhf2clQc4LBoZmFhru7gPnpA5ycB//b1mvXCkVZuuqbKBmyVQbuS8PIzICWTLcnzHhKFZNeC2YGR5HfMJ/pnMkG73fS8/LIY00+QdBMoZMET9/SKdlfbz+Cr5zqy46+Z7BcU/kBRwUbYXangxcIBCO7HfeKKFNrpWqqjVBOPJ0qEKftfLiXteWX4kKoJOPXnTmNFXyixFzG/uDSXo34OFvHwJDpJYUMyJcE4Sc9xP4FNDETKg+56cPJTy6L95sQ5NO7AES5zctCsJlaYG2ab/yawIscoWaho2jeJCjIWDFRcB+DLkYcBq8o/7iJA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=shJYfo5HPR96g5uSryEucrv1t0iGShZOy9dV1NlVuB0=; b=IFGqHPRCiDzzxmp7FTUaUQkQdS1Mlz/t3YwjbTcun9ap8ZJIX/n0WSRkg9NOUGuV4wVmWBojmieJATtg1MJFka/e3sw0s54Yd15Yvoblr7XU6tMcxtsnwx/In4JQR9HKxi4BckWIVyqo/f6Kk8Bm2VlrMFAI6FD0cAXmPzl9D1Q= Received: from BN9PR03CA0504.namprd03.prod.outlook.com (2603:10b6:408:130::29) by SN7PR12MB7324.namprd12.prod.outlook.com (2603:10b6:806:29b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.33; Wed, 19 Jul 2023 06:58:44 +0000 Received: from BN8NAM11FT089.eop-nam11.prod.protection.outlook.com (2603:10b6:408:130:cafe::8d) by BN9PR03CA0504.outlook.office365.com (2603:10b6:408:130::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.33 via Frontend Transport; Wed, 19 Jul 2023 06:58:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT089.mail.protection.outlook.com (10.13.176.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6588.34 via Frontend Transport; Wed, 19 Jul 2023 06:58:44 +0000 Received: from sindhu.amdval.net (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Jul 2023 01:58:37 -0500 From: Sandipan Das To: , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH 6/6] perf vendor events amd: Add Zen 4 memory controller events Date: Wed, 19 Jul 2023 12:25:41 +0530 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT089:EE_|SN7PR12MB7324:EE_ X-MS-Office365-Filtering-Correlation-Id: 708ed943-8416-43dd-6f15-08db882597d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nIZEJI+8RyWZD6B+6pSbESa/imx8zS74+qNlMT3XJTm2We5E2hx8u4hu/u+3fZ7P+LZ3rU3n2x0Y0ngRuBMGccBhF5DuNoE7/N8Y3rE6G8OzFM3+rwDTS99hHCvNmai3V0j+sJ5grTPBEutjUdJl5nL8zRgSJ3kBCtS6k3veK/93Sd7Ppkld9TjcDJXm44xFUUaaAQ1bKhQGUzAENyFdiaxVpFuD8zFPqrF5TwDPzQBUmyJmUnEOwUS/FeWQswD6tH4x2k/Xmcmnph/pERSE9evB5n36lhpLiHfCSstvQf6KFEmyeZYtLT2srHuDB/3K+MX+BAk3HWwBZGQ9bnPC/QwMrs85OV8S3i39OL+BMBNW0fva0ji7/ILaWL+fpEvpYf/7Fx5Mi1OS7UsVwci+MELuFgIpFpMJEo3xrZGCLlMPVgHQ+6DZy7GSzG9tk6kY+A5OlAcDTWwa/0oRr4VYr6RZrkOQ8GhebxPEtEvjsz4ICJKNH8AKEuO6+TCIO4IToldRi5Oqtm5QgSxaSPDbcpU3mYHvORsjitaYdjDOtexXHe6Hy171ggcdXFMQYlvFXdrPoA17IiUQnldwfoB+q0/PQFBj579sETQnsSln/orGaIWayfO+iGbvVNPhPXfMCxhNtL/8X27rGjEtYQcAV4XtKRMtENSpKNwWaUxFHezrogpou9TPw0DgJ+kdAmEFhKUeZk2+pzZ5sqXP1JPhtx4lX8c+tnHlez8BTnk03hzEY1uyjqpgwFHfDWH3gazPsmsMIYQgoW0rUPVTSDgEsg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(346002)(39860400002)(376002)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(54906003)(110136005)(40480700001)(86362001)(44832011)(7416002)(186003)(336012)(70586007)(70206006)(4326008)(478600001)(41300700001)(316002)(6666004)(8676002)(40460700003)(8936002)(5660300002)(26005)(2906002)(36860700001)(36756003)(426003)(82740400003)(16526019)(81166007)(356005)(83380400001)(2616005)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 06:58:44.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 708ed943-8416-43dd-6f15-08db882597d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7324 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771832760425436571 X-GMAIL-MSGID: 1771832760425436571 Make the jevents parser aware of the Unified Memory Controller (UMC) PMU and add events taken from Section 8.2.1 "UMC Performance Monitor Events" of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h processors. The events capture UMC command activity such as CAS, ACTIVATE, PRECHARGE etc. while the metrics derive data bus utilization and memory bandwidth out of these events. Signed-off-by: Sandipan Das Acked-by: Ian Rogers --- .../arch/x86/amdzen4/memory-controller.json | 101 ++++++++++++++++++ .../arch/x86/amdzen4/recommended.json | 84 +++++++++++++++ tools/perf/pmu-events/jevents.py | 2 + 3 files changed, 187 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json new file mode 100644 index 000000000000..55263e5e4f69 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json @@ -0,0 +1,101 @@ +[ + { + "EventName": "umc_mem_clk", + "PublicDescription": "Number of memory clock cycles.", + "EventCode": "0x00", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_act_cmd.all", + "PublicDescription": "Number of ACTIVATE commands sent.", + "EventCode": "0x05", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_act_cmd.rd", + "PublicDescription": "Number of ACTIVATE commands sent for reads.", + "EventCode": "0x05", + "RdWrMask": "0x1", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_act_cmd.wr", + "PublicDescription": "Number of ACTIVATE commands sent for writes.", + "EventCode": "0x05", + "RdWrMask": "0x2", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_pchg_cmd.all", + "PublicDescription": "Number of PRECHARGE commands sent.", + "EventCode": "0x06", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_pchg_cmd.rd", + "PublicDescription": "Number of PRECHARGE commands sent for reads.", + "EventCode": "0x06", + "RdWrMask": "0x1", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_pchg_cmd.wr", + "PublicDescription": "Number of PRECHARGE commands sent for writes.", + "EventCode": "0x06", + "RdWrMask": "0x2", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_cas_cmd.all", + "PublicDescription": "Number of CAS commands sent.", + "EventCode": "0x0a", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_cas_cmd.rd", + "PublicDescription": "Number of CAS commands sent for reads.", + "EventCode": "0x0a", + "RdWrMask": "0x1", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_cas_cmd.wr", + "PublicDescription": "Number of CAS commands sent for writes.", + "EventCode": "0x0a", + "RdWrMask": "0x2", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_data_slot_clks.all", + "PublicDescription": "Number of clocks used by the data bus.", + "EventCode": "0x14", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_data_slot_clks.rd", + "PublicDescription": "Number of clocks used by the data bus for reads.", + "EventCode": "0x14", + "RdWrMask": "0x1", + "PerPkg": "1", + "Unit": "UMCPMC" + }, + { + "EventName": "umc_data_slot_clks.wr", + "PublicDescription": "Number of clocks used by the data bus for writes.", + "EventCode": "0x14", + "RdWrMask": "0x2", + "PerPkg": "1", + "Unit": "UMCPMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json index 5e6a793acf7b..96e06401c6cb 100644 --- a/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json +++ b/tools/perf/pmu-events/arch/x86/amdzen4/recommended.json @@ -330,5 +330,89 @@ "MetricGroup": "data_fabric", "PerPkg": "1", "ScaleUnit": "6.103515625e-5MiB" + }, + { + "MetricName": "umc_data_bus_utilization", + "BriefDescription": "Memory controller data bus utilization.", + "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "100%" + }, + { + "MetricName": "umc_cas_cmd_rate", + "BriefDescription": "Memory controller CAS command rate.", + "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)", + "MetricGroup": "memory_controller", + "PerPkg": "1" + }, + { + "MetricName": "umc_cas_cmd_read_ratio", + "BriefDescription": "Ratio of memory controller CAS commands for reads.", + "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "100%" + }, + { + "MetricName": "umc_cas_cmd_write_ratio", + "BriefDescription": "Ratio of memory controller CAS commands for writes.", + "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "100%" + }, + { + "MetricName": "umc_mem_read_bandwidth", + "BriefDescription": "Estimated memory read bandwidth.", + "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "1MB/s" + }, + { + "MetricName": "umc_mem_write_bandwidth", + "BriefDescription": "Estimated memory write bandwidth.", + "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "1MB/s" + }, + { + "MetricName": "umc_mem_bandwidth", + "BriefDescription": "Estimated combined memory bandwidth.", + "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "1MB/s" + }, + { + "MetricName": "umc_cas_cmd_read_ratio", + "BriefDescription": "Ratio of memory controller CAS commands for reads.", + "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)", + "MetricGroup": "memory_controller", + "PerPkg": "1", + "ScaleUnit": "100%" + }, + { + "MetricName": "umc_cas_cmd_rate", + "BriefDescription": "Memory controller CAS command rate.", + "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)", + "MetricGroup": "memory_controller", + "PerPkg": "1" + }, + { + "MetricName": "umc_activate_cmd_rate", + "BriefDescription": "Memory controller ACTIVATE command rate.", + "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)", + "MetricGroup": "memory_controller", + "PerPkg": "1" + }, + { + "MetricName": "umc_precharge_cmd_rate", + "BriefDescription": "Memory controller PRECHARGE command rate.", + "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)", + "MetricGroup": "memory_controller", + "PerPkg": "1" } ] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 12e80bb7939b..c2a5728253db 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -272,6 +272,7 @@ class JsonEvent: 'imx8_ddr': 'imx8_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', + 'UMCPMC': 'amd_umc', 'cpu_core': 'cpu_core', 'cpu_atom': 'cpu_atom', } @@ -330,6 +331,7 @@ class JsonEvent: ('Invert', 'inv='), ('SampleAfterValue', 'period='), ('UMask', 'umask='), + ('RdWrMask', 'rdwrmask='), ] for key, value in event_fields: if key in jd and jd[key] != '0':