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Acked-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Change from v1 to v2 - move pci_epc_linkdown() after dev_dbg() drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index de4c1758a6c3..e0969ff2ddf7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -89,6 +89,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dev_dbg(pci->dev, "Link up\n"); } else if (val & PEX_PF0_PME_MES_DR_LDD) { dev_dbg(pci->dev, "Link down\n"); + pci_epc_linkdown(pci->ep.epc); } else if (val & PEX_PF0_PME_MES_DR_HRD) { dev_dbg(pci->dev, "Hot reset\n"); } From patchwork Tue Jul 18 18:21:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 122196 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1937826vqt; Tue, 18 Jul 2023 11:40:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlED1hoUvOlQ61XNXJ9d8geeg+8aCA0b0wgwmeUA0xHiaMqQGbPsYwUO70wW3WjDGWlHoPxE X-Received: by 2002:a05:6a20:3c9e:b0:12e:92c1:b1c8 with SMTP id b30-20020a056a203c9e00b0012e92c1b1c8mr17896688pzj.47.1689705603620; Tue, 18 Jul 2023 11:40:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1689705603; cv=pass; d=google.com; s=arc-20160816; b=mZBdfTg0S9vqkKZTlOZuu0GK7n813F0isEsL+oiunSzlHUavST/GMKT8bp70pkaCP5 uE+PRDnswxT6a6MjZJpqJDt6EBKBMgnXyooAYzHusBmZzfFFtj31qcBDtXrl1s6Xy7Ys xQn5rfVwLtL3cPoOrsraujaPZe1c/3YsRRGsBX698CV1OqTCriY0MC/gjJCPtaH95tdO /RAxuX/U+XQc21JSKNLCbLL37zr14bQ/odIFjVSTFxUXPWa+JKi9dk5HGhvYnHmLtSsg +whrAKIiJnyNryG1rO7P68FR+G20t9AXdAkwoCh9tpOj9ycgwJQ1xP0oheuc5ybM2gGh rVag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tOlUGhcVml+LzCFGMvAde1bKSkEEwT8EzhKyegX+UXk=; fh=yPrLISB45GnfagyCLYb0xWgOrKbf3LRnCoyeWAGjBkE=; b=vQ/1RV1I+t370vdqAkLO+Der3T/dqlTu92FW8NEHQ7tAMdBowel+z+FkS+cmZCexEv naBOZ8hsq/GPPuck9FGJfN/ZzoBDHk8LNBbTx5mNEip+NBBTQ8OBze65NpcUVg/qGCGC ShElcqkG827X/bVx1kunh8/JZBSEFuNq0ykdrqcPfXjQWGwaUK0lQGkX8R8AjbiT20/O 4vcn/RwQH048zKovZ04m7iNUPGk5dFYZx8jii281sqU1WUVuzLJ4J49a+oPFEZzyU30Q 3bNXz7fMaSne6L5+TLyFdFnnchLn6QphTezxxIDseiLY1DRmozNz7blY3MNziSJO3jhn aibg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=NM+TGiiW; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB9572.eurprd04.prod.outlook.com (2603:10a6:102:24f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.32; Tue, 18 Jul 2023 18:22:05 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::6cc2:14b2:ca51:6c0]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::6cc2:14b2:ca51:6c0%4]) with mapi id 15.20.6588.031; Tue, 18 Jul 2023 18:22:05 +0000 From: Frank Li To: mani@kernel.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Date: Tue, 18 Jul 2023 14:21:42 -0400 Message-Id: <20230718182142.1864070-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718182142.1864070-1-Frank.Li@nxp.com> References: <20230718182142.1864070-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0049.namprd13.prod.outlook.com (2603:10b6:a03:2c2::24) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB9572:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e881eaa-83b7-4738-1f6e-08db87bbe3cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Frank Li Acked-by: Manivannan Sadhasivam --- change from v1 to v2: - add comments at restore register - add fixes tag .../pci/controller/dwc/pci-layerscape-ep.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index e0969ff2ddf7..b1faf41a2fae 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,6 +45,7 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; + u32 lnkcap; bool big_endian; }; @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; + u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + /* + * The values of the Maximum Link Width and Supported Link + * Speed from the Link Capabilities Register will be lost + * during link down or hot reset. Restore initial value + * that configured by the Reset Configuration Word (RCW). + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret;