From patchwork Tue Jul 18 15:22:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 122114 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1864289vqt; Tue, 18 Jul 2023 09:27:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlGxOHjPsTautSOLl/eKGZ+GNj175kQw2ljl0Tg3TfBvjtP05xO3exxBBNJnOHNnfiP3dPxM X-Received: by 2002:aa7:cf0b:0:b0:51d:a6e3:81fb with SMTP id a11-20020aa7cf0b000000b0051da6e381fbmr415736edy.14.1689697622669; Tue, 18 Jul 2023 09:27:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689697622; cv=none; d=google.com; s=arc-20160816; b=ERKPOwjcLu9qFV/22BwX3xDALZFo/SX+5eKwEKN+wIWQSmPwtcz9XCAo3XEItomIkH LFbowKbfESCLL4K+yXyPJGZdRPuY5AhZkkozWq+HymejPA5sTzWAtT90ecHAPHIf0xpb p8VZJto7JDQVACvfMBA8Kw39RbhVw1W4mpOmj0oWhGJ+XEr4Wv+kGS4T0WYlQRrk7TjU zzQRunPHSnNIkDi/zCWA2b8tApLdao47EmTtLTF3po401tkGk1l3u4605Ai2PKtOjRIf 86fLEh1yuppTy7O82dtfe0+M+BVO6xUGoGEWJm4gancUymlUvnVxNP8+/xVnxF0EbEOm LQCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DWAultWzpQVsdeC6ocSMHVYcnjnZ/sb7WEhsp28Y+Go=; fh=4dEsi7QIwecjtTyQysIed7zhM6Kqdn9yv5jIBHUtcd8=; b=r9B4R8Cmvk0xrNxfAXzs5+OKu8ln7Y0VWkgWeOXcZqclqU+q0yUJOoxvS0g53xQAvD jsXiEOr5Yut5+cjbQ/QYrrw92qbkMMoWjbNwLG5XkI09k8TGxUZq4/9kRO0cjz9azCZQ S4te7gEi+phTJm9rAGqc22QJWtOTdBGaVSwrysWORvoXRSJOnRx2OCLMTbokaLx7B5l1 QgqSXqjrOmGv3l+0qs/xnvVJN5yqYacHdrUKq+a62vwo56aGqNQFfNWOn24iNFAhxgGZ Qjbn891vWo7xHZTYO0XlGahQjkBIKRPXmfPep7cPEDp6C/iUgcAcGVXCEEIiCp2rzasq vKrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IFQ8InmJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r21-20020a056402035500b0051dd2c07091si1514612edw.161.2023.07.18.09.26.38; Tue, 18 Jul 2023 09:27:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IFQ8InmJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231994AbjGRPe1 (ORCPT + 99 others); Tue, 18 Jul 2023 11:34:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231582AbjGRPeT (ORCPT ); Tue, 18 Jul 2023 11:34:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 375161B1 for ; Tue, 18 Jul 2023 08:33:58 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E75D76163F for ; Tue, 18 Jul 2023 15:33:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2F9CC433C7; Tue, 18 Jul 2023 15:33:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689694429; bh=dNhCnd7BRoxmEqrazlgCFOTdL35V2PIvQRzI8MBzvnc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IFQ8InmJBGLXenNwP9TnDxUAeYjLdfDQrr8/wvAJCYqc4mrpPIq0ZDaoObnj9De23 Qr6f29az56t/spK0A4QRGSAeLEwJMUgG48Ea3TRX4Mzt7N6F552Zxe6gSg6zzQ4Wu5 lc7cKIYgNIRocm20YW0mn47mMNx1yfPpDKXKU3jb2Kzyf9MYBc6RoEv1XSEsdxNufS BbzcZzQWpU0+m0GsJ/TUpMcScleur68RFM+hygwNFuVVfS1j1JfkENZpHBktkkGyn7 jK13Hr1rjvd19fBFltYyTB3eo5n3GCF69fWeyK85m+M9rYBo/Wc/QvN/fRAI/PClLG uf+7JdXQJgsFA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] riscv: allow kmalloc() caches aligned to the smallest value Date: Tue, 18 Jul 2023 23:22:13 +0800 Message-Id: <20230718152214.2907-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230718152214.2907-1-jszhang@kernel.org> References: <20230718152214.2907-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771776374625012187 X-GMAIL-MSGID: 1771776374625012187 Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus it brings some bad effects to coherent platforms: Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and kmalloc-8 slab caches don't exist any more, they are replaced with either kmalloc-128 or kmalloc-64. Secondly, larger than necessary kmalloc aligned allocations results in unnecessary cache/TLB pressure. This issue also exists on arm64 platforms. From last year, Catalin tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage in various drivers with ARCH_DMA_MINALIGN etc.[1] One fact we can make use of for riscv: if the CPU doesn't support ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on Catalin's work and above fact, we can easily solve the kmalloc align issue for riscv: we can override dma_get_cache_alignment(), then let it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know the underlying HW neither supports ZICBOM nor supports T-HEAD CMO. So what about if the CPU supports ZICBOM or T-HEAD CMO, but all the devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the kmalloc minimum alignment, nothing changed in this case. This case can be improved in the future. After this patch, a simple test of booting to a small buildroot rootfs on qemu shows: kmalloc-96 5041 5041 96 ... kmalloc-64 9606 9606 64 ... kmalloc-32 5128 5128 32 ... kmalloc-16 7682 7682 16 ... kmalloc-8 10246 10246 8 ... So we save about 1268KB memory. The saving will be much larger in normal OS env on real HW platforms. Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/ [1] Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cache.h | 14 ++++++++++++++ arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/kernel/setup.c | 1 + arch/riscv/mm/dma-noncoherent.c | 8 ++++++++ 4 files changed, 25 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index d3036df23ccb..2174fe7bac9a 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -13,6 +13,7 @@ #ifdef CONFIG_RISCV_DMA_NONCOHERENT #define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN (8) #endif /* @@ -23,4 +24,17 @@ #define ARCH_SLAB_MINALIGN 16 #endif +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +extern int dma_cache_alignment; +#define dma_get_cache_alignment dma_get_cache_alignment +static inline int dma_get_cache_alignment(void) +{ + return dma_cache_alignment; +} +#endif + +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_RISCV_CACHE_H */ diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..c640ab6f843b 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -55,8 +55,10 @@ void riscv_init_cbo_blocksizes(void); #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); +void __init riscv_set_dma_cache_alignment(void); #else static inline void riscv_noncoherent_supported(void) {} +static inline void riscv_set_dma_cache_alignment(void) {} #endif /* diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 971fe776e2f8..027879b1557a 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -311,6 +311,7 @@ void __init setup_arch(char **cmdline_p) if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) riscv_noncoherent_supported(); + riscv_set_dma_cache_alignment(); } static int __init topology_init(void) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d51a75864e53..811227e54bbd 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -11,6 +11,8 @@ #include static bool noncoherent_supported __ro_after_init; +int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN; +EXPORT_SYMBOL_GPL(dma_cache_alignment); void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) @@ -78,3 +80,9 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +void __init riscv_set_dma_cache_alignment(void) +{ + if (!noncoherent_supported) + dma_cache_alignment = 1; +} From patchwork Tue Jul 18 15:22:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 122109 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1855873vqt; Tue, 18 Jul 2023 09:12:50 -0700 (PDT) X-Google-Smtp-Source: APBJJlGMXQttCVtgYZ643UkFtybk6AYKSxpINn4+HUyIOALfp/0nyT5jn7klcgBdnVJ0FpdsTgYm X-Received: by 2002:a17:906:1990:b0:991:fef4:bb7 with SMTP id g16-20020a170906199000b00991fef40bb7mr107652ejd.73.1689696769555; Tue, 18 Jul 2023 09:12:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689696769; cv=none; d=google.com; s=arc-20160816; b=cHP75+myYFd0cX0XV0W5EAVzW8VFXzIn+FQqc0WsT4V7j6xuDYxG7oAP0HXohIacDD iT5oRuGHhHWBQSKdVYQhkw/ogK9IurJWZYgLgmCDCSoGgJYbO49N/4npLuqaAvaGHPXE ZygDZcBjdBWmVMQ3E0XS6FeyYkDxVTtKoSiBYnRM0Px0xnUqgG0lOYpTU2AjJzM2pVqn aut1+5hSafe9EvXjK/PQQ60qLJdaniVCsS0ZYrerxTYQvfR69MhMOmoklwKt29h0GTcP 7V77oMqsuVhTI9zZTPa+3NZmzkcDJB9YOdJXcLyqX7KhFyA8w7IjKbghL5vepEuqW2Ub 9DqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zV5zqI83iPv7AITQY55QeT+k9nsbrdlD6lFEUZyFCiE=; fh=1UfjdVY4gj8HcsYK7tCqVu7nJXHajZ1RjmcSSd+4W94=; b=YH/XS2daJodhnJpCEtdyCI96XE223fn/4BztcdMcPxNxH5B7zJaT2EuC3TByMOEMYN cNrRzqo6zcQFX+HNWF4Qr0382/3uUbyi1eI4eSPNU9ZsbSd2HrkC1GfRLX6iXH8B6dqZ GbSiMKVw21d/o4PAjAnrc2pT8zCEPRXNwHK8/IIvJytfy0U1rqjrCaoIGaJgGFkw14zI JClShX6jfMdPj/NGWWHTzLNSMj+Ex9iV3SQCgcs2cF/MAbzHAdB0y+nFFLLeF8aVQoEw I3awSU69WOhG5nhVdZDS8oPeYdjIFO6r7nOlp8AQqnZluZg7Eqr8ll7Bskk4avtiQpHD DWtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ZauC2YoS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g13-20020a170906198d00b00992c3b85acbsi1329868ejd.128.2023.07.18.09.12.25; Tue, 18 Jul 2023 09:12:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ZauC2YoS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233696AbjGRPec (ORCPT + 99 others); Tue, 18 Jul 2023 11:34:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232294AbjGRPeV (ORCPT ); Tue, 18 Jul 2023 11:34:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69B0E172D for ; Tue, 18 Jul 2023 08:34:00 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 78AB56164C for ; Tue, 18 Jul 2023 15:33:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC4A2C433C8; Tue, 18 Jul 2023 15:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689694430; bh=mqwYcIZH+M6h8d7AW+YLg7/JE8kUv6dByMB/fsXMe5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZauC2YoS57Y7Z75WX93K8wwq6vCm7vKYIrjQ7e1PVKNVB9oFy4zuFqlAHt/o9u8ig +jHL7t3YG0DIEB6aHqFTmfny58qvFcbf5CIXyGWvdZTy1e53lTQ536dn67rE17C/nX tNSMeABCJ0uBzJAhNRUYMbCjBerE73usUmO+jRF0pZkGkqrR+kns0jDAsySb5rrjm0 vJ0c0tNKTFlWD33YC5Vz/yDQMvPds538rFQgalIrZPB3wuBc466LP3kRSqQwFP4Ch0 oEvk6Z0ioJ5Hc+hwquvbxlp6Z83T51FMAMWjgZo4xqIpfbbJNOElQr6m7JucSJtx3Y kYKEx/dV4ZjKQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v3 2/2] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Date: Tue, 18 Jul 2023 23:22:14 +0800 Message-Id: <20230718152214.2907-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230718152214.2907-1-jszhang@kernel.org> References: <20230718152214.2907-1-jszhang@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771775480303690351 X-GMAIL-MSGID: 1771775480303690351 With the DMA bouncing of unaligned kmalloc() buffers now in place, enable it for riscv when RISCV_DMA_NONCOHERENT=y to allow the kmalloc-{8,16,32,96} caches. Since RV32 doesn't enable SWIOTLB yet, and I didn't see any dma noncoherent RV32 platforms in the mainline, so skip RV32 now by only enabling DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB is available. Once we see such requirement on RV32, we can enable it then. NOTE: we didn't force to create the swiotlb buffer even when the end of RAM is within the 32-bit physical address range. That's to say: For RV64 with > 4GB memory, the feature is enabled. For RV64 with <= 4GB memory, the feature isn't enabled by default. We rely on users to pass "swiotlb=mmnn,force" where mmnn is the Number of I/O TLB slabs, see kernel-parameters.txt for details. Tested on Sipeed Lichee Pi 4A with 8GB DDR and Sipeed M1S BL808 Dock board. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4c07b9189c86..6681bd6ed2d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -267,6 +267,7 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB select DMA_DIRECT_REMAP config AS_HAS_INSN