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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id w5-20020ac25d45000000b004fbc95a4db3sm418257lfd.28.2023.07.18.05.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 05:19:14 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Jul 2023 14:19:10 +0200 Subject: [PATCH v4 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v4-1-bae382dc0f92@linaro.org> References: <20230328-topic-msgram_mpm-v4-0-bae382dc0f92@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v4-0-bae382dc0f92@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689682752; l=3218; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=u7PKeGTsnebqt/okOLLY3lwduIHrT4WR6NdeB30CILY=; b=D/5g2C3sqCGpybb/GodJlreV5rDzRD9x/w6Al8mFWyfRb19zFCPxVj5YC+m4wBj6PH/LQR7Tg 9ay+dDf8/eQAnOE/EG5tuOTQMKMIAsQTR1BgkUyS5s00i2lcdudg3RA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771761851603194561 X-GMAIL-MSGID: 1771761851603194561 Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible = "qcom,mpm"; - interrupts = ; - reg = <0x45f01b8 0x1000>; - mboxes = <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - qcom,mpm-pin-count = <96>; - qcom,mpm-pin-map = <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; From patchwork Tue Jul 18 12:19:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 121984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1709273vqt; Tue, 18 Jul 2023 05:34:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlED2Gh+9GNZBMoZFptx8/R7IskuR4v9gk/9hm+dEXoPQ13Ey+L476WyJcFNIhhtQLycy0T9 X-Received: by 2002:a05:6a00:21d0:b0:671:6fbf:f901 with SMTP id t16-20020a056a0021d000b006716fbff901mr17682711pfj.10.1689683695592; Tue, 18 Jul 2023 05:34:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689683695; cv=none; d=google.com; s=arc-20160816; b=vtRcFvWcqdOiRIUiRy9T+FFr7nipXORsOIklLZonCqrGTuDljjz6vtT0PWoenKFf04 SDVzsnKjZ5ebAH4Y2GrRORZVrX5ZAA4SHXAnHbNQTO8U6Fc3mnrxINHDHC0cj3HrcZRe G7q83dqWExy+/BIAiVbaDKm6BoyoKHgeAUz6G1pYQpmjyqHfdvLxfXgEzfC1b2rjrxFt YnSzgiSe+/nK5767sqf1ImJXj4DukYRB6/yXiYD7PcVvG/FuAQNGrz1j6+w7E/KZy2kK aBiQl/TScrnO0sjFkWeaMHnOXLQrKj+OeZW4ble8ZbUwg1GLZcvOY+pkdXmZ+PJXVc9t 4J2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=UZHiNhlcnBcV/12CBhpoH4NhL4fdNzTRpHhX759efoE=; fh=FCGQIQhIoBeQIuAmosFmbTCLUM3rKAqeZFV8ZSIlHeM=; b=ZdqBuUdJfVHlhGJGy76Lt/7sXmH0JSA1PwqNNlxB7wd8XjlFQc+n2D7BnN9iMAzPs4 fwE3J+hlUNxmHYPZ7BZfPSxqVTMaURDw6Dnf/MPpDJYy6zHtnCLlnR+QA3iCARua2aXz m3kWIo5KCr3Gs5QGZoZMAfm14Tdl2KfDzLXJVyXlEvpnBmWkG0RwFJcje7rJGavUeh2o VZBfJ6eSi5zgMZnL85pkisZUPMOUx8pzJfGY5dqNPR1dmKiD4+v9FOjVXPl9eQr4MCKC ae7a3CdxEp+gvMotCNVy9vSWSsgZcw5mx6chOUGqzkvYrk7AVO1YRG3EAEH+vf2s7AMm Rqxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BkiQdJeW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id w5-20020ac25d45000000b004fbc95a4db3sm418257lfd.28.2023.07.18.05.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 05:19:16 -0700 (PDT) From: Konrad Dybcio Date: Tue, 18 Jul 2023 14:19:11 +0200 Subject: [PATCH v4 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v4-2-bae382dc0f92@linaro.org> References: <20230328-topic-msgram_mpm-v4-0-bae382dc0f92@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v4-0-bae382dc0f92@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689682752; l=2751; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yQx/+qerpXC0l+cy+Ejk8gpdBKyKLvnTn9FYud1Txtk=; b=5CXvh5t6cxxmX683kjykjDScpVxz5kvmakrM1qH3EXTb53Kw1A5IqAAzygFxf1rNF0/r/LGhJ v7Ay7ThPnocDBXcvdEegD7ivKBpaQ+GfHIY9l7jTm+5hNWk0ePtVgbK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771761770446685378 X-GMAIL-MSGID: 1771761770446685378 The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Signed-off-by: Konrad Dybcio --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index d30614661eea..ee5f39a4a42a 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);