From patchwork Tue Jul 18 07:21:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U3RhbmxleSBDaGFuZ1vmmIzogrLlvrdd?= X-Patchwork-Id: 121818 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1569319vqt; Tue, 18 Jul 2023 00:40:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlErvAYkU4wxJ2RBSsfPeikJ/oyq4LMP8+5rBKv75E9PwkamejSWqRgb8CUKEGU/MhZfo4w5 X-Received: by 2002:a17:902:f68c:b0:1b8:c8bc:c81b with SMTP id l12-20020a170902f68c00b001b8c8bcc81bmr15550133plg.21.1689666003972; Tue, 18 Jul 2023 00:40:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689666003; cv=none; d=google.com; s=arc-20160816; b=vp9127TR3xAS8lfAuwHema1zSdXxP5lmiK84PcII8sHblATwFXLnaIVQMehkLZ54Fg eXFH0vtPznxfkopBSgUiT9bvEabFiBkmHzxd1NEt8Rg7QcbM22ntvl0y/+IcZ9o3zQD0 MArayxIAfWc7HNBbPwAP77GfkT6VaX/wgAkQHmDpjimSA2V4G5+1GK6ERZ0B1myS5zf0 WyzDze2TXl+frzKfonfbelopdAvg4lOAyC0MLRxkvRnh2V7cjqd0ZeSMTI9RL2JSiGwS 6CD1gNqo2cXC8crvk02IMKeuMFYXRxPPVhMBEYsMz7t8KtjAZEn6vCUo+GBjslx52Ed4 Y6ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:authenticated-by; bh=LfwKYvvFXNxhc6a2MqtJmdfF+is8V/7h4nvzzHNpHxI=; fh=KcreGm5jGgmIE1NaGHUu4gJN0T5ux2Fo5ikyfC+bcrY=; b=qtjJzaFSrTPltX8aSj2vG+3rw3KqpgQHks7abnVQtUXpeG0qeuSlScS62xicMt5hZ5 zH5M/IWdyMYgmOn2OQlDXT3WdF7XMjVz1Bwnb1YIvzZ2sGHhQSzijnv24OYxcn/xPaJ8 U+njJ42fwV98xdQaPKI+moX/9Zn3Ar3LALAjwfaRrPtSZ5EarJdZqf2HV+kEYpMs0wv4 Kds/hn/wdlZ5/WrNSvbNWo7IDG0Cfam9Iw0COv12TnoRYhFE9jDLcQ19l+pqIWBGyr8m OH+zFHQORHH1p983BGmZJC2+W1T9CNTKkAXIqpYxX1VriowkBf6m8wZNdGzs5FqyBaG2 nadA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u10-20020a17090341ca00b001b87b17cfb4si1265485ple.392.2023.07.18.00.39.51; Tue, 18 Jul 2023 00:40:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231592AbjGRHVi (ORCPT + 99 others); Tue, 18 Jul 2023 03:21:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229920AbjGRHVg (ORCPT ); Tue, 18 Jul 2023 03:21:36 -0400 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9BB4610C; Tue, 18 Jul 2023 00:21:32 -0700 (PDT) Authenticated-By: X-SpamFilter-By: ArmorX SpamTrap 5.77 with qID 36I7L8h44009295, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.81/5.90) with ESMTPS id 36I7L8h44009295 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 18 Jul 2023 15:21:08 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Tue, 18 Jul 2023 15:21:17 +0800 Received: from RTEXH36505.realtek.com.tw (172.21.6.25) by RTEXMBS04.realtek.com.tw (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Tue, 18 Jul 2023 15:21:15 +0800 Received: from localhost.localdomain (172.21.252.101) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server id 15.1.2375.32 via Frontend Transport; Tue, 18 Jul 2023 15:21:15 +0800 From: Stanley Chang To: Thinh Nguyen CC: Stanley Chang , Greg Kroah-Hartman , , Subject: [PATCH v1] usb: dwc3: core: configure TX/RX threshold for DWC3_IP Date: Tue, 18 Jul 2023 15:21:08 +0800 Message-ID: <20230718072115.19685-1-stanley_chang@realtek.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-KSE-ServerInfo: RTEXMBS04.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771743219422518736 X-GMAIL-MSGID: 1771743219422518736 In Synopsys's dwc3 data book: To avoid underrun and overrun during the burst, in a high-latency bus system (like USB), threshold and burst size control is provided through GTXTHRCFG and GRXTHRCFG registers. In Realtek DHC SoC, DWC3 USB 3.0 uses AHB system bus. When dwc3 is connected with USB 2.5G Ethernet, there will be overrun problem. Therefore, setting TX/RX thresholds can avoid this issue. Signed-off-by: Stanley Chang --- drivers/usb/dwc3/core.c | 33 +++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 5 +++++ 2 files changed, 38 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f6689b731718..a0a54e5c4ad9 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1262,6 +1262,39 @@ static int dwc3_core_init(struct dwc3 *dwc) } } + if (DWC3_IP_IS(DWC3)) { + u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; + u8 rx_maxburst = dwc->rx_max_burst_prd; + u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; + u8 tx_maxburst = dwc->tx_max_burst_prd; + + if (rx_thr_num && rx_maxburst) { + reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); + reg |= DWC3_GRXTHRCFG_PKTCNTSEL; + + reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); + reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); + + reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); + reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); + + dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); + } + + if (tx_thr_num && tx_maxburst) { + reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); + reg |= DWC3_GTXTHRCFG_PKTCNTSEL; + + reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); + reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); + + reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); + reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); + + dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); + } + } + return 0; err_power_off_phy: diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 8b1295e4dcdd..5480fcb59bcb 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -211,6 +211,11 @@ #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) +/* Global TX Threshold Configuration Register */ +#define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16) +#define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24) +#define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29) + /* Global RX Threshold Configuration Register for DWC_usb31 only */ #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)