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Signed-off-by: Bhupesh Sharma Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 5ad9d5deaaf8a..b580398041d87 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm845-tcsr - qcom,sdx55-tcsr - qcom,sdx65-tcsr + - qcom,sm6115-tcsr - qcom,sm8150-tcsr - qcom,sm8450-tcsr - qcom,tcsr-apq8064 From patchwork Tue Jul 18 06:10:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121781 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1537009vqt; Mon, 17 Jul 2023 23:17:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlFrHhCDrlN+CIjF9vdMBwsOLF6OOy8EmFdGYPBJm2EGVCY6gYvggFXfnS1O+6FM0qYBR1gd X-Received: by 2002:a05:6a21:9993:b0:133:b3db:c78b with SMTP id ve19-20020a056a21999300b00133b3dbc78bmr11265431pzb.36.1689661025064; Mon, 17 Jul 2023 23:17:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689661025; cv=none; d=google.com; s=arc-20160816; b=f8JWCFhCivEUZR1oLzEMbYk+ylQj2CnAwSXAbtoXF5Dd9R7eSUG1m7C+lYTjI3yiCS nBUtMyJOlWQIkwfYP0k2vZqR+gccmTgRG2JQQw2cbu2oVOXFwOnep5IHyFyhb2bThb8L Y0KNGKVv4PA713K4yEk5G3A8p1Is8uRYruiZCGOwCQKJGnmfz+5kT93MbU5eYSupNkID ND5YqBEW5QvBZ+rv6A7F20S8cqO7Dv2pHxe0/MBuoXTrFBrCKkRExaxczN1J08aDdhRb oajc5fDr5KCqJAJoepY03CKMO/xcqbITNv9L4fmqFiySxI+qf8yvP/a+jZlR2+7Wyocq dd+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R3U8YGGir0L/mdYZ0L+59VSzteiUJkc0KitjLit6CXs=; fh=m/g2beIBC/gUlgiFZ33vN+mjSQx49mQUAjZ4Ony+ssI=; b=UTZBiHZUfK+mibqs0dJf+FfEqcLhx4vGSQU9PmFDwmCttH6H0upKT+PjekwGWD7BHo WhMMwabZpeVFvKPfg55SmtdxpfCO+FmdsoTYij8N3t/Ou0tzXeqm3H0D168ij/bgVRCy diXZ4H0jjClO1D6c68qOyOfLNjtDckCM0mRBqr6jJ4LnKp28JfEIMvrvKiQaz1BlNpi7 un5bR3ZgVhvWwBz2e+lXF02IMmMchdurwwKsHUIO0hl5M6zu4lZvZQK5n6FXZM65dt71 k9/AaM0S8F0Xw6/DElWNBma2wS7juJhfmuCj3FSiA6QCY8rQkMoiRjp5ZgLEzZb17QDi N77g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=asFylN+n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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So introduce a vendor-specific dt-property 'qcom,secure-eud-reg' which specifies the base address of the TCSR reg space and the offset of the 'tcsr_check_reg'. Signed-off-by: Bhupesh Sharma Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437b..ca38d219e57d5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -45,6 +45,14 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: This port is to be attached to the type C connector. + qcom,secure-eud-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the secure mode manager register + description: TCSR hardware block + required: - compatible - reg From patchwork Tue Jul 18 06:10:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121789 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1540945vqt; Mon, 17 Jul 2023 23:28:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlFUjYwsfViGaTMsoXkDZnG07BrFsIpJ53uJxxLwcZc8fs7juD9IFC1f7n28BlH1veIKJl9z X-Received: by 2002:a17:902:82c2:b0:1b8:76d1:f1e8 with SMTP id u2-20020a17090282c200b001b876d1f1e8mr12038701plz.28.1689661683462; Mon, 17 Jul 2023 23:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689661683; cv=none; d=google.com; s=arc-20160816; b=BopICmdbSH4n2Vombry51NAHd7gQN/LkdC2GcLdJ5FvjqMHHXewIDE0qtitCxNYMz7 Ua1FXclPYClaT0Ya8RuFCWf24dGmtB7co6a/k/EjZnHTM9sgxssc4VJS/B/idVEkcviD vlrutoiWLxZB0DDYiUfOFH8WiPbcez+J/UI6t3zyzscBHh/YiodgXqnsxdNn/JFgi3Ys GTtImEG6KUjl8Ic1XuhmLmloPtPjxRhDqLEXu8uM9UpZZB9o6ggd0C2t72MWTOVdjn1W 2oEAQsa4UqDAlLe/bMyD0odSLG5RVS4R6/+1nKtYFYPiJkd0OmFvfhcmmgthFMat46j4 fzeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cj0Kr21fyKMkxAxxSOMwsypaT2zCqEO5kfSgBNpmV4w=; fh=m/g2beIBC/gUlgiFZ33vN+mjSQx49mQUAjZ4Ony+ssI=; b=BLBenvyL4Enc3o5kkKQ7oAVOju8Aj/Icsi8cZ0kaCAZMEcoLsAtcwP+S+J2TJ3qqrS yBtAHek3rvHQO3yiNOF2enTdKsxfnh1w78vAzSP0NnhwLwlUs3dumladNg0ij2QvaHYY 3he4LdouKfSFFUP2LJba9XA0tCfhKnx3XDI6vM1seCj5cGZXSsPcw6Hs0QO0Aw/CBUN2 haw7Qb40/myN5Gegz5L30K3JYDFWFrN9qQpnEKbHk5yrXVtdNiZukRAbi434Lf5nZoMg O+4k2Rujtbb+9urJSkrF42FlAjavovkt3H7UyqtiAmlWMSM/gm2OSFVWSW4fUdmUxuTE uYQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E4VIlEjB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index ca38d219e57d5..bb9b97f03585f 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: From patchwork Tue Jul 18 06:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1537161vqt; Mon, 17 Jul 2023 23:17:30 -0700 (PDT) X-Google-Smtp-Source: APBJJlEPWeYmOS5G23fOja877bDWExI8iiOpzHSEs2tzO4GgNaDz91pPCnZtPmH/Px8oBA6OeLMt X-Received: by 2002:a9d:73c4:0:b0:6b9:48fb:1b5a with SMTP id m4-20020a9d73c4000000b006b948fb1b5amr12904781otk.8.1689661049818; Mon, 17 Jul 2023 23:17:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689661049; cv=none; d=google.com; s=arc-20160816; b=nLBG2zuH+LLghFxK3p1vXuVtlyymwEKKiZNnvjhmdo8UPLQrdFfCp5eulqwg96k/c+ i9mpccO1KZiObgQY9EP7wIX1J5XPFAi2SDqWuVzUSwASEmRIzR76ldyWpTWTIAWfpywT jYb2M2wXcPqfhEQyo1v0Iqa0gv9sjYsZ1FufbtHUk9tx7vZkxoYuiy70hsuwHOFTrGs7 OzjbOoi6rhhcowuNMNJw96yWOJm+5S/0hW8gNDCUlTrsmRyFd9p8bbBSBK6ouw2/TfbB FEge4zVi6fiwNVKq3bz+4/Od1MCRQivtqr6rdSiqqMRWoU5WIXb2laqCm5jmijdlX0ZE vLfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BYiFLzJcgS5ZH0B0OriyMRTUX2STtvU6MnH5HLZczGY=; fh=m/g2beIBC/gUlgiFZ33vN+mjSQx49mQUAjZ4Ony+ssI=; b=x53xxRQGNNi6j3An4BPKE0DY+cleM1myH+PNOU3cSm62lCOxICUXvphCiO1azGr2OL z/rf03OV7RPn5H5LZfjHsnHsTPcu/PPe3ficRsuUY14eYSEUKzu+3lm4NlS1ZxCpnvt+ Jtygt00dGww8GbXBKGmOYiqyq9W2SjuC2CFYekm9saSvcoV53zh5sQxOYSaZMRJ2+lV9 eSGUzKvshDKjY3es9xaYw8xYYyGmMTxKpmwhjnMAO5JN86GspgfEwH13LqgGIMfPgPhO oh95X+xq/KqOv+LdApV4xufHVJuR/7pTQuVaVmrk+KZazeGDzZNojRrv4mm7Kgc4+puT FNZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CW+vd5hw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 2 +- drivers/usb/misc/qcom_eud.c | 76 ++++++++++++++++++++++++++++++++++--- 2 files changed, 72 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd57..51eb5140caa14 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -146,7 +146,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on (ARCH_QCOM && QCOM_SCM) || COMPILE_TEST select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 7f371ea1248c3..a5b28fc24116a 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,9 +11,12 @@ #include #include #include +#include +#include #include #include #include +#include #include #define EUD_REG_INT1_EN_MASK 0x0024 @@ -30,6 +33,10 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +#define EUD_EN2_EN BIT(0) +#define EUD_EN2_DISABLE (0) +#define TCSR_CHECK_EN BIT(0) + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; @@ -39,6 +46,7 @@ struct eud_chip { int irq; bool enabled; bool usb_attached; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +54,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_EN); + else + writel(EUD_EN2_EN, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +66,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_DISABLE); + else + writel(EUD_EN2_DISABLE, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -175,9 +191,37 @@ static void eud_role_switch_release(void *data) usb_role_switch_put(chip->role_sw); } +static int eud_find_secure_reg_addr(struct device *dev, u64 *addr) +{ + struct device_node *tcsr; + struct device_node *np = dev->of_node; + struct resource res; + u32 offset; + int ret; + + tcsr = of_parse_phandle(np, "qcom,secure-eud-reg", 0); + if (!tcsr) + return 0; + + ret = of_address_to_resource(tcsr, 0, &res); + of_node_put(tcsr); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "qcom,secure-eud-reg", 1, &offset); + if (ret < 0) + return ret; + + *addr = res.start + offset; + + return 0; +} + static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_check = 0; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +244,30 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + /* + * EUD block on a few Qualcomm SoCs needs secure register access. + * Check for the same via vendor-specific dt property. + */ + ret = eud_find_secure_reg_addr(&pdev->dev, &tcsr_check); + if (ret < 0) + return ret; + + if (tcsr_check) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + + ret = qcom_scm_io_writel(tcsr_check, TCSR_CHECK_EN); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -230,6 +295,7 @@ static void eud_remove(struct platform_device *pdev) static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud" }, { } }; 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Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 839c603512403..3be0b54fc3628 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -591,6 +591,11 @@ tcsr_mutex: hwlock@340000 { #hwlock-cells = <1>; }; + tcsr_regs: syscon@3c0000 { + compatible = "qcom,sm6115-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; reg = <0x0 0x00500000 0x0 0x400000>, From patchwork Tue Jul 18 06:10:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121788 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1540104vqt; Mon, 17 Jul 2023 23:25:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlHIb4HOs0C+VvnlD2f9jBbF+SU+ljMy+hZKWJ1yIXrMdkwONcZDvWG87awi15rkJtc8vD56 X-Received: by 2002:a05:6808:1294:b0:3a3:fde5:dd20 with SMTP id a20-20020a056808129400b003a3fde5dd20mr2348115oiw.30.1689661552543; Mon, 17 Jul 2023 23:25:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689661552; cv=none; d=google.com; s=arc-20160816; b=mrRTA0prDDFA9LUxAHiWAecQsJ6gIOWqkIVqU5mpsWOjitH4J9T9I3lGJxsgeEYx3F LYGJMXdN+cGn0pcnKIOs9QqWae4rWe3EbT4R6StAVPKyp/iZvAQ50d+WSe2F38OmRXqg dO6pKkDWf8WlbWqv3gCqZTs66IHNPJIViWQCkDsDgJu8pSCQl9xn9s9NC3ELrHFtguBP v85ReErNKaPG55FVrMxRYgQHJpEQvCkC3vyKMyI9Ah1pHTf4w2dmOgxHt1xfPEPyJxx8 5lGbhodNwUUDuYUnoJXgfjdAzKbhG98qrkxpVh3/aaMLnRKnjPtGDhRFF2kB4OOtJKAP UHTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KBuW+Z6XAY92SVZQectHpFEOvJKx1OjjfxzUkTjvZPo=; fh=m/g2beIBC/gUlgiFZ33vN+mjSQx49mQUAjZ4Ony+ssI=; b=ACLOjcFv5NaH0s/cQuQUtt5wF5Bk0FTL5tMR3LvkGp5qGHVXfCQsNjXEMyFZ2Q7uHo 31/34HyhL/rrLrhuS+JwUVLu678HBqYf1Dq0gz+XBzc4LezInuqcsnZC/A3Bii4aga3a O56X42jUZgY3DBsVNlMhRX8l+fZhhTvAbhTKm3pSipaGK+6f0Dofe/XpEW2gZjaqhMoL powdlj8uaWaEKKNU113n9dx3I37CDL4k0L4MTkgeOxaKiLrTETUAuaPylW5HliGSFrva /0zEEkQMkzMVSqhdidgyUj3lEqVN3AKltEV52ObRZrJAoDUjAvcMJJhe4d+7IBjzyPEZ tpyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HpItcyu7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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The node contains EUD base register region, EUD mode manager register region. The TCSR Base register region is defined via a vendor specific dt-property. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 3be0b54fc3628..cd5b85b63a9ec 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -260,6 +260,18 @@ CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -794,6 +806,38 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>; + reg-names = "eud-base", "eud-mode-mgr"; + interrupts = ; + + qcom,secure-eud-reg = <&tcsr_regs 0x25018>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; @@ -1327,6 +1371,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; From patchwork Tue Jul 18 06:10:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121782 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1537070vqt; Mon, 17 Jul 2023 23:17:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlEY+JvHtabP1ca4BV85RHsZHTkyx6FqU2Rp031SWat/rOcg2YWB/NK09Ubfu8NetT/JBTcY X-Received: by 2002:a05:6512:158d:b0:4f8:596a:4bb7 with SMTP id bp13-20020a056512158d00b004f8596a4bb7mr9467767lfb.57.1689661036687; Mon, 17 Jul 2023 23:17:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689661036; cv=none; d=google.com; s=arc-20160816; b=z1yenqrriZY44SFyM+6SINHjfH+sPnXHSO2W8KlVzazdTk4VRnUKulj/R8WGMEIDgP nYolr8ypo5wGoUyhcOWsLa601gg9mS7uZuZBnIcqRKxZW6PebwZ1JaltMssl2pynY117 RCdxPohuWU8dIsfArTvKsnBNS6lIa9Kxgqi+8txv6bSsRWe3j6EaOB0nBXruielBOviH 2Nx9yRxbQTE9FR+EAg7smMyEpzuwUZkwCGyxwLFwP8w1T7WQrP7umOtzo7ACQDq0sSe6 8jGg7/BPSVuQwKNIaapWxITP2GB0tZKLXw1FOdpd04RtuGdbIJPQVQ9mhj8II8BQvxjs a6pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aoaxiWdRTQIjlpKBPFLmbhlJ2o+zAdh4av4kyochmEo=; fh=m/g2beIBC/gUlgiFZ33vN+mjSQx49mQUAjZ4Ony+ssI=; b=0z0Hg93nK4yyiKU5uxb910ngLNjOfBNHS4D4+TTbebgZ+1VVILfuQl/zhBs7BBz0Zl hjhxXE11mkDT/RqmFmL2rbFVW4ltnade8fdeT7fPBJKPKpOGzxyOCK8NWCtu6qoKagct y5vjgxP/9ByS4MkSVtC+TqhqTwrDGAsIhWGBhoAfdgTIdqHpQjSWlancaYxfMVglzPE9 VwKwgV9rwG+99Y4JR6/uXpxhXM82pXL6XcIRnO/lz7a/i6LLkLZNAZZAKJNPEzDgkywP xBlGSkjuqx2Zn7IsW9vzPXk9gMZ8NeYbinbZaOZcCoWj/qIhA9rHhvBA6c6LE/bqFahb H/nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sn5U4MWG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a7278a9472ed9..640668960deb0 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -264,6 +264,10 @@ &pon_resin { status = "okay"; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -518,7 +522,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {