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[8.43.85.97]) by mx.google.com with ESMTPS id p16-20020a1709060e9000b0096fe1a56de3si709968ejf.1048.2023.07.17.23.03.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 23:03:33 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@embecosm.com header.s=google header.b=EXEQnJt0; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D856F385700B for ; Tue, 18 Jul 2023 06:03:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 8FA0E3858D20 for ; Tue, 18 Jul 2023 06:02:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8FA0E3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-il1-x12d.google.com with SMTP id e9e14a558f8ab-345d6dc271dso28348855ab.0 for ; Mon, 17 Jul 2023 23:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1689660178; x=1692252178; h=to:subject:message-id:date:from:mime-version:from:to:cc:subject :date:message-id:reply-to; bh=bFUXbKAmQ+S2L1gVA9U/bFT9DB/smhgz7pMyU4V5J/g=; b=EXEQnJt0ZePargxfugkpk/wQQt0mwJIyI9kgVgIoRgVM99z3Ppave4LNOIwQQZus5n hXQAIU2BtmEltNqZ6nqWycOtfkGspQTh2a2vxPdS6EMu/wija7jODjs93091AzCWmCno T0zD/b3xmvo1BdQYBPsbt0qIkEGaE0XH0xR15btr/5OKUoi2zfjQJH4To7PniV4g1bRf 3XXm41bSsJWWhLbdJ1Y9LV/xnQqNXzodoe1PMk6I9pGSuAsoZZBA8IpPoQts0+7ZPAp7 SMkEj2lqQ1VxaouTas5klDrCnwe6T5I4WXDXh+hbvW9vTv9mVTa3FOhafHmsId4rUDsw d8Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689660178; x=1692252178; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=bFUXbKAmQ+S2L1gVA9U/bFT9DB/smhgz7pMyU4V5J/g=; b=KoBqWBFDCHfNpdf378xQtY9ixPHQOFEyWuRqJFPgJxrFY0qYyvRzkLodcKTDmgweGx MfkVauI+RfS5prxRJMtWFVfUn6HP/GyUlOyuPoAMfvzv6ohW9K88Z7u/EWJVtRMIjJBU XVxrn4Avf8bICeqr27LAIM8L+LO7/GKmSeQf0Jn1g52LyRz/ugS+9h98U0CQ2lY7rQZ8 d90EewnSMkm6UzFecEiLJrWOtSFfqRxGhft2Ug2fgD+wARkBsKCTUiratAf9Iv4ZE7YP oRHIaCAEyWrHYEnBKitoUeXDgUJuCJpkvhtFVd2EujmJCAxMX4r1qEYgySJzEPOtovlm FQ+g== X-Gm-Message-State: ABy/qLYU1/jDabE81YKBU4LffR5G4+ypZux71BMlwKNJJjU0zEEJy6uf FMXf0scDT8tyt1JKjHHNcUeC816B9uVsxPRPCvFX9UVOa015IwavqtI= X-Received: by 2002:a05:6e02:1aa1:b0:347:733c:a55a with SMTP id l1-20020a056e021aa100b00347733ca55amr1788411ilv.18.1689660177717; Mon, 17 Jul 2023 23:02:57 -0700 (PDT) MIME-Version: 1.0 From: Joern Rennecke Date: Tue, 18 Jul 2023 07:02:46 +0100 Message-ID: Subject: RISCV test infrastructure for d / v / zfh extensions To: GCC Patches X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771737147978484419 X-GMAIL-MSGID: 1771737147978484419 This makes it easier to write tests that safely test features needing d, v and/or zfh extensions. check_effective_target_riscv_v checks if the current target allows to use vector instructions. add_options_for_riscv_v ask to add an -arch option to change the target to one like the current one, but with the 'v' extension enabled, if it is not already is. That is generally safe for compile-only tests, e.g. using scan-assembler* stanzas. If you have an execution test that you want to force usin the extension if the actual execution target supports that, you can use check_effective_target_riscv_v_ok to check if that's ok, and then add_options_for_riscv_v to add the appropriate -march option. Examples how this can be used can be found athttps://github.com/embecosm/rvv-gcc/tree/rvv-12/gcc/testsuite 2023-04-17 Joern Rennecke gcc/testsuite/ * lib/target-supports.exp (check_effective_target_rv_float_abi_soft): New proc. (check_effective_target_riscv_d): Likewise. (check_effective_target_riscv_v): Likewise. (check_effective_target_riscv_zfh): Likewise. (check_effective_target_riscv_v_ok): likewise. (check_effective_target_riscv_zfh_ok): Likewise. (riscv_get_arch, add_options_for_riscv_v): Likewise. (add_options_for_riscv_zfh): Likewise. (add_options_for_riscv_d): Likewise. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 8ea0d9feb1c..deeb0ef8865 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1884,6 +1884,173 @@ proc check_effective_target_rv64 { } { }] } +# Return 1 if the target abi is __riscv_float_abi_soft, 0 otherwise. +# Cache the result. + +proc check_effective_target_rv_float_abi_soft { } { + # Check that we are compiling for RV64 by checking the xlen size. + return [check_no_compiler_messages riscv_riscv_float_abi_soft assembly { + #ifndef __riscv_float_abi_soft + #error "Not __riscv_float_abi_soft" + #endif + }] +} + +# Return 1 if the target arch supports the double precision floating point +# extension, 0 otherwise. Cache the result. + +proc check_effective_target_riscv_d { } { + return [check_no_compiler_messages riscv_ext_d assembly { + #ifndef __riscv_d + #error "Not __riscv_d" + #endif + }] +} + +# Return 1 if the target arch supports the vector extension, 0 otherwise. +# Cache the result. + +proc check_effective_target_riscv_v { } { + return [check_no_compiler_messages riscv_ext_v assembly { + #ifndef __riscv_v + #error "Not __riscv_v" + #endif + }] +} + +# Return 1 if the target arch supports half float, 0 otherwise. +# Note, this differs from the test performed by +# /* dg-skip-if "" { *-*-* } { "*" } { "-march=rv*zfh*" } */ +# in that it takes default behaviour into account. +# Cache the result. + +proc check_effective_target_riscv_zfh { } { + return [check_no_compiler_messages riscv_ext_zfh assembly { + #ifndef __riscv_zfh + #error "Not __riscv_zfh" + #endif + }] +} + +# Return 1 if we can execute code when using dg-add-options riscv_v + +proc check_effective_target_riscv_v_ok { } { + # If the target already supports v without any added options, + # we may assume we can execute just fine. + if { [check_effective_target_riscv_v] } { + return 1 + } + + # check if we can execute vector insns with the given hardware or + # simulator + set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v] + if { [check_runtime ${gcc_march}_exec { + int main() { asm("vsetivli t0, 9, e8, m1, tu, ma"); return 0; } } "-march=${gcc_march}"] } { + return 1 + } + + # Possible future extensions: If the target is a simulator, dg-add-options + # might change its config to make it allow vector insns, or we might use + # options to set special elf flags / sections to effect that. + + return 0 +} + +# Return 1 if we can execute code when using dg-add-options riscv_zfh + +proc check_effective_target_riscv_zfh_ok { } { + # If the target already supports zfh without any added options, + # we may assume we can execute just fine. + # ??? Other cases we should consider: + # - target / simulator already supports zfh extension - test for that. + # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator + if { [check_effective_target_riscv_zfh] } { + return 1 + } + + # check if we can execute vector insns with the given hardware or + # simulator + set gcc_march [riscv_get_arch] + if { [check_runtime ${gcc_march}_zfh_exec { + int main() { asm("feq.h a3,fa5,fa4"); return 0; } } "-march=${gcc_march}_zfh"] } { + return 1 + } + + # Possible future extensions: If the target is a simulator, dg-add-options + # might change its config to make it allow half float insns, or we might + # use options to set special elf flags / sections to effect that. + + return 0 +} + +proc riscv_get_arch { } { + set gcc_march "" + # ??? do we neeed to add more extensions to the list below? + foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs } { + if { [check_no_compiler_messages riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] { + #ifndef DEF + #error "Not DEF" + #endif + }]] } { + if { [string length $ext] > 1 } { + set ext _${ext} + } + set gcc_march $gcc_march$ext + } + if { [string equal $gcc_march "imafd"] } { + set gcc_march "g" + } + } + if { [check_effective_target_rv32] } { + set gcc_march rv32$gcc_march + } elseif { [check_effective_target_rv64] } { + set gcc_march rv64$gcc_march + } else { + set gcc_march "" + } + return "$gcc_march" +} + +proc add_options_for_riscv_d { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + # ??? Is there a way to make the match specific to a full list element? + # as it is, we might match something inside a string. + return [regsub -all -- {(-march=rv[[:digit:]]*[a-ce-rt-wy]*)d*} $flags \\1d ] + } + if { [check_effective_target_riscv_d] } { + return "$flags" + } + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &d]" +} + +proc add_options_for_riscv_v { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + # ??? Is there a way to make the match specific to a full list element? + # as it is, we might match something inside a string. + return [regsub -all -- {(-march=rv[[:digit:]]*[a-rt-uwy]*)v*} $flags \\1v ] + } + if { [check_effective_target_riscv_v] } { + return "$flags" + } + return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]" +} + +proc add_options_for_riscv_zfh { flags } { + if { [lsearch $flags -march=*] >= 0 } { + # If there are multiple -march flags, we have to adjust all of them. + # ??? Is there a way to make the match specific to a full list element? + # as it is, we might match something inside a string. + set flags [regsub -all -- {-march=[[:alnum:]_.]*} $flags &_zfh ] + return [regsub -all -- {(-march=[[:alnum:]_.]*_zfh[[:alnum:]_.]*)_zfh} $flags \\1 ] + } + if { [check_effective_target_riscv_zfh] } { + return "$flags" + } + return "$flags -march=[riscv_get_arch]_zfh" +} + # Return 1 if the target OS supports running SSE executables, 0 # otherwise. Cache the result.