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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ay1-20020a056402202100b0051e0c612208si13262082edb.546.2023.07.17.05.40.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 05:40:26 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 88D323857731 for ; Mon, 17 Jul 2023 12:40:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 6A2243858430 for ; Mon, 17 Jul 2023 12:39:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6A2243858430 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1689597572t1mdci6m Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Jul 2023 20:39:31 +0800 (CST) X-QQ-SSF: 01400000000000G0T000000A0000000 X-QQ-FEAT: PS/N6jJLnDbnd4TJ4qzn9toUhgl5rHpNlAjyx/vXBU0NOFn+ne5CZmT4u58+n yrx52mZz+2WLhir9al0WUisfvw6MIjzI+ksfTwdUNZ/tAE4whOeWtbeq5lYwAotuHuCzQ2q G1l+BcRM+pOA2fD12dGQzBvXTsbt614lQ/8pQ/gvlfgsZ7QQJfGwoXhAUrpUuWvQSzYgs4/ fKeKK7yDjp7CS8Ldy53Wh/U84egp6kOwRb/kG9NKNSHkdHpB+vVjYfaSoUodjVea2pXtPDI UjpmCg4p+WsV4q6+8U2Iy6Ny3eHkBqsBsQDAP3FLb8RJ6Vz9UQFBsE1I9ov8Uz00VMmegzp YWJSt9x8prP86Cm7s8QSwhhY3ajrZtgdoBjGrPAcKkpxecy0HU3ZPASRsC2E9/VhAJvAzAI X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10485823464768693672 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Juzhe-Zhong Subject: [PATCH] RTL_SSA: Relax PHI_MODE in phi_setup Date: Mon, 17 Jul 2023 20:39:29 +0800 Message-Id: <20230717123929.260814-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771671520862607164 X-GMAIL-MSGID: 1771671520862607164 Hi, Richard. RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc) There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc) When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE: rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186 13 | } | ^ 0xf7a5b1 partial_subreg_p(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl.h:3186 0x1407616 wider_subreg_mode(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl.h:3252 0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677 0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*) ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146 0x2a2c142 rtl_ssa::function_info::simplify_phis() ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258 0x2a2b3f0 rtl_ssa::function_info::function_info(function*) ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51 0x1cebab9 pass_vsetvl::init() ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578 0x1cec150 pass_vsetvl::execute(function*) ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716 The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97] When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () = V32QImode. But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes). Then combine_modes report ICE. In this situation, I relax it and let it use phi_mode directly. Is it correct ? Thanks. gcc/ChangeLog: * rtl-ssa/functions.cc (function_info::simplify_phi_setup): Relax combine in PHI setup. --- gcc/rtl-ssa/functions.cc | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/gcc/rtl-ssa/functions.cc b/gcc/rtl-ssa/functions.cc index c35d25dbf8f..0793598ab1d 100644 --- a/gcc/rtl-ssa/functions.cc +++ b/gcc/rtl-ssa/functions.cc @@ -143,7 +143,19 @@ function_info::simplify_phi_setup (phi_info *phi, set_info **assumed_values, // If the input has a known mode (i.e. not BLKmode), make sure // that the phi's mode is at least as large. if (def) - phi_mode = combine_modes (phi_mode, def->mode ()); + { + /* For target like RISC-V, it applies both variable-length + and fixed-length to the same REG_CLASS. + + It will cause ICE for these 2 following cases: + 1. phi_mode: variable-length. + def->mode (): fixed-length. + 2. phi_mode: fixed-length. + def->mode (): variable-length. */ + if (!(GET_MODE_SIZE (phi_mode).is_constant () + ^ GET_MODE_SIZE (def->mode ()).is_constant ())) + phi_mode = combine_modes (phi_mode, def->mode ()); + } } if (phi->mode () != phi_mode) phi->set_mode (phi_mode);