From patchwork Mon Jul 17 10:32:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121194 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1025842vqt; Mon, 17 Jul 2023 03:38:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlHsixx0iKjfdQ/N7zSE27hxUjhXA9bRUXXmZaAIGElKDJ84u86GHb7B05Cm+CMmF2y8cvJJ X-Received: by 2002:a2e:3001:0:b0:2b6:ee6d:b647 with SMTP id w1-20020a2e3001000000b002b6ee6db647mr7697127ljw.28.1689590316446; Mon, 17 Jul 2023 03:38:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689590316; cv=none; d=google.com; s=arc-20160816; b=pNbFo1ynje2txOmzGMr2Np8Bsh+ufPF8WDXPBUE2vBZFWTXk07k4ArYnu+HMHfVql0 +tznAjXSFxTSpjtJjwyuk98MSKNWyuhmqemovzJoap8yyStQ+uAvThdRd5ZDF3HJXgg1 wLXI2sVEmDsRManaAjEkIlVfODTC59OLyO0YchTkRHi4HxjywTk7cRLsTMH6tDz3Lky7 kImQxvw9eb02M7/7E32j64biWTtHrhrPTVcmR81LPDFriVOC4qBcUtN1XoGLRzPfrzm6 AOrkHQ7uR5BnPYunIPcl0HLjB/CjgZtiNEW3edyuZxiumdwKHUofgBmc+VTv9VglFP+O nRQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f6nS90cTjCSY7Tyo8KTgzDnh4BrkTy5UxyLb8PDeWUE=; fh=EpmhsCJ53Xk7LwEhS9AhHTV+oP3v1t43CrLSIzR2Qco=; b=0IIvjMdUX95V/Lk+d8ltzfjJ0c0LoOIlUZbibpPkEuT+rxwKeSb91oqoIH9ja5i9wL xiGEVSBnrWk4c2pBq6hyfjMvNiqyNSA8jIYrAT+n4hRCPnXNiXRvBY3MJIFZ0nBPglIQ psPSpmYLUxO4Ga2jHSaf6CHQE75PWjQ0ZbEIccg+l88tgtOsJO+zVPfVFWt7N5JDUDqb SnCOJ6ukLxyK2iqxaj1Yjx/S0p1vyTE746D06bEd7tcx5KCnsrBj278bReXL2E45eBiw y2Uf2W9+7NEYKxA3LsRlIp0I7l4D/I3wA3iu57noDIMdmDYjjENes/m6kIgEHrbI2Z8j eZLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c+09fdJb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kg17-20020a17090776f100b0098874379199si13157696ejc.163.2023.07.17.03.38.12; Mon, 17 Jul 2023 03:38:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c+09fdJb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231182AbjGQKdj (ORCPT + 99 others); Mon, 17 Jul 2023 06:33:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229772AbjGQKd3 (ORCPT ); Mon, 17 Jul 2023 06:33:29 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC69B19A9 for ; Mon, 17 Jul 2023 03:33:07 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1b852785a65so26392165ad.0 for ; Mon, 17 Jul 2023 03:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689589978; x=1692181978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f6nS90cTjCSY7Tyo8KTgzDnh4BrkTy5UxyLb8PDeWUE=; b=c+09fdJb79CO8X/gmJ74r6rTnBbn0Pe5L63/elKMcPDbT0DESKOvmxcIxAPsxoBw0J A46rI4QatHrxVoCEz/OJCQUX8b3B54nHbRBYEF/xNUx3EWhZmoDSkkOmRAGE7Jcg39lv Q+AVd6RfWm9ahCcWtAVEqQSogWV+HKcoBnviU8b+4yGDVcXK7/XySHfHTYU7rtuN6Y4G Kx2LHT0begdXwscKvyf3ZDhWTe/mpX7RL51MWN/XAi6rZ2ZhyG0zRzORjerTPzVi1w8f 4XpwZAldTnrds8BvA1jf+TqoJ88O7+8Pl+bkkQkW4Atii46aC/u0KQp9yxXA6pCUXYDh NYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689589978; x=1692181978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6nS90cTjCSY7Tyo8KTgzDnh4BrkTy5UxyLb8PDeWUE=; b=fcOHXhm6G+o2ElNZ3dyhfxDU8EhHhOy6pMomQN68F/sTm0K4CpaGQoOgC+sdGJMOTk FwGukwhm0M+bUk4aLs9z8tMKXE5AlKETgpETysiVzAPLe9HANHkhTFWLDHR4xf7uamWj dWeaWkYdWi/V/zfk0CSZYU13miVgr+vUKejcvmzx4cS2QnSukE2e5CpJITz83AWAQh+M e6xWIiMGa2i1eXrny6Xhcq0JO1uTyIFIbxpLvKgjWFy/EICZTweNDzOSvUBUXUUJWNZq vErcJ4Sfxc2BrZtdkDi795cEVzfUQ6PFkxXfs+uPE+FM2NKwWctguuZcz4LsrLf9PfbX cKHg== X-Gm-Message-State: ABy/qLZs2HUfzyxCfIsSUltTtyAoyOJiP1kssfquB1REIUpawAXDqRgc SfnKot38UVRLo84chLFiVyxOow== X-Received: by 2002:a17:903:32c9:b0:1b5:5162:53bd with SMTP id i9-20020a17090332c900b001b5516253bdmr13332000plr.33.1689589977999; Mon, 17 Jul 2023 03:32:57 -0700 (PDT) Received: from localhost.localdomain ([223.233.68.54]) by smtp.gmail.com with ESMTPSA id ij9-20020a170902ab4900b001b9de67285dsm12633616plb.156.2023.07.17.03.32.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 03:32:57 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, quic_schowdhu@quicinc.com, gregkh@linuxfoundation.org Subject: [PATCH v8 1/4] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 support Date: Mon, 17 Jul 2023 16:02:33 +0530 Message-Id: <20230717103236.1246771-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230717103236.1246771-1-bhupesh.sharma@linaro.org> References: <20230717103236.1246771-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771663855695174652 X-GMAIL-MSGID: 1771663855695174652 Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma --- .../bindings/soc/qcom/qcom,eud.yaml | 42 +++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437b..71274bc978584 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,12 +18,16 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud reg: - items: - - description: EUD Base Register Region - - description: EUD Mode Manager Register + minItems: 2 + maxItems: 3 + + reg-names: + minItems: 2 + maxItems: 3 interrupts: description: EUD interrupt @@ -50,6 +54,38 @@ required: - reg - ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-eud + then: + properties: + reg: + maxItems: 2 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-eud + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base + additionalProperties: false examples: From patchwork Mon Jul 17 10:32:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121201 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1030373vqt; Mon, 17 Jul 2023 03:51:13 -0700 (PDT) X-Google-Smtp-Source: APBJJlEuZm+nH9uuEwAp5XNZ0F8Y0g8gh+52Ztv6h+wfO2Zr4kQ+4KSL9+wJx3nJ7C8FeOVuLBGZ X-Received: by 2002:a05:6a20:8f28:b0:10f:be0:4dce with SMTP id b40-20020a056a208f2800b0010f0be04dcemr15233609pzk.8.1689591072896; Mon, 17 Jul 2023 03:51:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689591072; cv=none; d=google.com; s=arc-20160816; b=ixH+/Y28YsyVqNtRFd67RaAtAuKiZ2z3//xXbTSt5nyfSMYbwmaYvHgCHnBi0cJDED PUh3shvM4i2z+aQ2x1TI2BCkebqgA1vvrKe+OWHOlUxjoqAakQBEUbANb2shy3fl7H4p FMy9BRNDB3M39K0laheMPpz/E40igIkKP02hF+6kgI9CmOFSaFQis1rvcV/+KFOD5XUv 6BiUcYZuvF9JlIejZZuBjufE5g7M9fBjPRo9ZCjNO2xigNtFI/HJMEm9rh32rr3XS6Ne oEadNbtw8ZD87s//fHgZOjlE0IdMqjYl3jCtoHKfTv22Y7XN0FuCkUzEkoZPD3G4nkkP nwKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ATTO38/iOwVxNwj2oDkWC8K05sDZoQ4wq1YyEPI7+d8=; fh=EpmhsCJ53Xk7LwEhS9AhHTV+oP3v1t43CrLSIzR2Qco=; b=zY1TXtxRTP7nEBkYRnNA/sNIyPqwKY2fXmx7nlfWGZFEoTOqfIj21K8sXv/jzbl3Yt dkuH5PkkPZ5t+B+BAB/5EBG2enUHQO1xBSETFfP6RdtOz1ekd/gTVZokhVFUSwlF8QOV Df90wk5YaA8zFw3Wg7HLW/iHg/mZ6JbhQ39HlSOnfv4o6IkRcXOPKZnzVc9PbFZlntE6 zxRAP76nre51D9g84gh0GxRJeIRU0b28jxGg4YSmjdcfVZ6ptIbnpmvvXTZfgZV0ajT4 o7qU8n81oBykb/SmwJZ/0TFKVIt62QpP/DS/IJpmKD6fw27Gu2Dcnw0S6Q0NPFHM4g4Z lvfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MyOhzNAQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 2 +- drivers/usb/misc/qcom_eud.c | 62 ++++++++++++++++++++++++++++++++++--- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd57..51eb5140caa14 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -146,7 +146,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" - depends on ARCH_QCOM || COMPILE_TEST + depends on (ARCH_QCOM && QCOM_SCM) || COMPILE_TEST select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 7f371ea1248c3..136cac90228a0 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,9 +11,11 @@ #include #include #include +#include #include #include #include +#include #include #define EUD_REG_INT1_EN_MASK 0x0024 @@ -30,15 +32,25 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) +#define EUD_EN2_EN BIT(0) +#define EUD_EN2_DISABLE (0) +#define TCSR_CHECK_EN BIT(0) + +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + phys_addr_t secure_mode_mgr; }; static int enable_eud(struct eud_chip *priv) @@ -46,7 +58,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_EN); + else + writel(EUD_EN2_EN, priv->mode_mgr + EUD_REG_EUD_EN2); return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +70,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, EUD_EN2_DISABLE); + else + writel(EUD_EN2_DISABLE, priv->mode_mgr + EUD_REG_EUD_EN2); } static ssize_t enable_show(struct device *dev, @@ -178,6 +198,8 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_check; int ret; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); @@ -200,9 +222,34 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + /* + * EUD block on a few Qualcomm SoCs needs secure register access. + * Check for the same via SoC specific config data. + */ + chip->eud_cfg = of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr = res->start; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr-base"); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_check = res->start + chip->eud_cfg->tcsr_check_offset; + + ret = qcom_scm_io_writel(tcsr_check, TCSR_CHECK_EN); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"); + } else { + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } chip->irq = platform_get_irq(pdev, 0); ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -228,8 +275,13 @@ static void eud_remove(struct platform_device *pdev) disable_irq_wake(chip->irq); } +static const struct eud_soc_cfg sm6115_eud_cfg = { + .tcsr_check_offset = 0x25018, +}; + static const struct of_device_id eud_dt_match[] = { { .compatible = "qcom,sc7280-eud" }, + { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match); 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The node contains EUD base register region, EUD mode manager register region and TCSR Base register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 839c603512403..db45337c1082c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -260,6 +260,18 @@ CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -789,6 +801,37 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>, + <0x0 0x003c0000 0x0 0x40000>; + reg-names = "eud-base", "eud-mode-mgr", "tcsr-base"; + interrupts = ; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; @@ -1322,6 +1365,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; From patchwork Mon Jul 17 10:32:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 121195 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1025868vqt; Mon, 17 Jul 2023 03:38:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlHrygpE5pq5AXPAu684BBxfzm5bQs/zuV5YSNdbNHx2yH8vA8XdHPnE6f2ciHOqY8E6kpou X-Received: by 2002:a17:907:3f10:b0:994:55ce:1630 with SMTP id hq16-20020a1709073f1000b0099455ce1630mr10143570ejc.42.1689590319684; Mon, 17 Jul 2023 03:38:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689590319; cv=none; d=google.com; s=arc-20160816; b=wQDo1LvWZce+1K5aHqRoyiFIBYyTGpartIPdVfj1KlEVaDNUUURdRVw2cwBXxreX/j CTAF1PhWXzsgmQSX5QMuDZ5egDhIzmdywvCw4tMB5AENB0tuiuT32vkvllylpj29ZU9A 57dKt6b9BbkoX9tGZx38aKuhrmZj3tI7KYZEorzEugFal7KQIyxYs4q2X1LLabsaBHYT FZsNfp6DPWNP4683nWOZ41JVJQlZFKvVophK4v3axrkUtOYAMmWngOpiB873o4MyRiCT Tefzk45XvtA/OIOSR9FOQIKUZA3hFqUaL1IodG/gKHWaL3y/eRAJwd4I08FZ7iftecME glAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aoaxiWdRTQIjlpKBPFLmbhlJ2o+zAdh4av4kyochmEo=; fh=EpmhsCJ53Xk7LwEhS9AhHTV+oP3v1t43CrLSIzR2Qco=; b=T6MLLKYRxBC3Viw9yl3jWuz6uBaMfk19bsPdjhYnf2bO5F9EP7Ph2Yet+O55F0SwJb xTurRPzwkCQ/iNZw87MMZoX8fiqXHZ2rNyGq2zQ6uYegfwi16SW3Y0sTSFrOLCbucpCX MHwcUJ8/1RSrRbtINEm5rotu9PUX1q1pfZpTBTBjbUbE/P4+Dq/mvLK/MR3WPO/97nHB 04Bd6VAS0RPVzauZDlXF7FizYFVLBbFqok0ha/KM6eo42JYF4hAAYnYH/FGdytLUvgHp WhPusrjeloYwwos9wu+WGNboHwN+wj7bj+5S5PWZDBGLJDh9hxYGGkgVqFQhxsH5F2tw W5qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g519a+G7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a7278a9472ed9..640668960deb0 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -264,6 +264,10 @@ &pon_resin { status = "okay"; }; +&eud { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -518,7 +522,28 @@ &usb { &usb_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is connected + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connector + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (for e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethernet + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode = "otg"; }; &usb_hsphy {