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[83.9.2.167]) by smtp.gmail.com with ESMTPSA id 27-20020ac2483b000000b004f858249932sm1927732lft.90.2023.07.15.07.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jul 2023 07:37:21 -0700 (PDT) From: Konrad Dybcio Date: Sat, 15 Jul 2023 16:37:11 +0200 Subject: [PATCH v3 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v3-1-2c72f27b4706@linaro.org> References: <20230328-topic-msgram_mpm-v3-0-2c72f27b4706@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v3-0-2c72f27b4706@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689431838; l=2979; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hEZfhI1EGIlmfejCXVFxQDw5yfJpSTVeevTgH6zVb+o=; b=smtqGVT2hbELn8tjrn1hDztpZdaIz3pc7WiPLxXkZgqgZ5E9//CxZiIvoOAt5Ik9sz7PUku8w Gb2YXdtkfkgDzht6OAufS03cz0dcX1HdSTjdrqCnoGUfV2iu4l3+y5b X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771498687913892400 X-GMAIL-MSGID: 1771498687913892400 Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 44 +++++++++++++--------- 1 file changed, 27 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..b8bd408748e4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,33 +70,37 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible = "qcom,mpm"; - interrupts = ; - reg = <0x45f01b8 0x1000>; - mboxes = <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - qcom,mpm-pin-count = <96>; - qcom,mpm-pin-map = <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; From patchwork Sat Jul 15 14:37:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 120801 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp204874vqt; Sat, 15 Jul 2023 07:46:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlGpmb2yjsq7/KNIlYEue8AFKjsCFAzwIseNu0NHcNO80FbV6b36CRARc1H9f0XdIZc/Cvar X-Received: by 2002:aa7:d8c7:0:b0:51e:5686:d0f8 with SMTP id k7-20020aa7d8c7000000b0051e5686d0f8mr6916878eds.10.1689432418659; Sat, 15 Jul 2023 07:46:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689432418; cv=none; d=google.com; s=arc-20160816; b=s2ziOeCpGVtvfOovAIiGZeDGhtCGxEph8vlNgcIqjB3NLTKj87q3Q4IIRcvK4CCBI2 thgq9fXz87RTXhDwnwJeeNaQIfpa/oy9T/ZAe/XLrMnD2zkJae4bJASZYvrdmOfOzdWy lGNBoy3jLRTuTIsZ0nnNEDEaRGnzHJUdVl2oBHT1awZVTr4aKGcyumXN5BYYeLFqA2bx lPbsHVJGSpdxRNZeaMMK719bZxe4PTSzSNM4fK94WBKt2XqiQqhv6z3sHArM/CLgvYH4 XBatFPp5kgZFNVxiz9FQs+4djZXBS40Ytvtnxd9RUBYwiePJ21njGw7gSy9rHuMmrK2b FVMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=UZHiNhlcnBcV/12CBhpoH4NhL4fdNzTRpHhX759efoE=; fh=FCGQIQhIoBeQIuAmosFmbTCLUM3rKAqeZFV8ZSIlHeM=; b=b4NIMiD81+pGiWnDuTrS77oGL5g7gGv9ffN/gHjJN4bn1Kx5IFUCZMIzmWDHVRbKM1 IS3cb2QlM55PL9KunxY0oIYQ6JwDao8cuiz5X0LuOatmYvR1UfX/qLq/Z5fb6S5i5qQ3 suK9H8mLt4T63nICsWiy04zqw8GtpmqxgAwoSbxUfiw5ze2l1LnmEoVUaONrJRa+JezP fskaZRsEHXACq2DbP3oiKM7yiHM77SOYT7tyKJ1QODpn4VlSyNVVzBNFUxIdYMaxyvyn f02kO+ozi0ZgNOnCDsCWD7ORK9JBkZftFwV+3kL/ouL652w26bjkvVe7qNhw3GlxTlyQ QOpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BsY8MQ0x; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.2.167]) by smtp.gmail.com with ESMTPSA id 27-20020ac2483b000000b004f858249932sm1927732lft.90.2023.07.15.07.37.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jul 2023 07:37:22 -0700 (PDT) From: Konrad Dybcio Date: Sat, 15 Jul 2023 16:37:12 +0200 Subject: [PATCH v3 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v3-2-2c72f27b4706@linaro.org> References: <20230328-topic-msgram_mpm-v3-0-2c72f27b4706@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v3-0-2c72f27b4706@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689431838; l=2751; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yQx/+qerpXC0l+cy+Ejk8gpdBKyKLvnTn9FYud1Txtk=; b=szGuRyKgIllLGEGjGUWBYEelsIFHCREhm0PjQzBAVd4lOmpKRU1A29kDL5kw7XOvz7H87kCpy ZfQpQPJiHweDDXeQ1mH32MHmq7iNL/jUgQelWRHvrMIhOv8xPEJZKxD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771498287939847708 X-GMAIL-MSGID: 1771498287939847708 The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Signed-off-by: Konrad Dybcio --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index d30614661eea..ee5f39a4a42a 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);