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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e5-20020a50a685000000b0045d189ac60esi7128418edc.401.2022.10.31.02.20.23; Mon, 31 Oct 2022 02:20:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbiJaJTX (ORCPT + 99 others); Mon, 31 Oct 2022 05:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230144AbiJaJTQ (ORCPT ); Mon, 31 Oct 2022 05:19:16 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7DDDBD2F6; Mon, 31 Oct 2022 02:19:14 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 921DA1FB; Mon, 31 Oct 2022 02:19:20 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 160823F703; Mon, 31 Oct 2022 02:19:11 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Brijesh Singh , Suravee Suthikulpanit , Tom Lendacky , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH 01/20] arm64: dts: Update cache properties for amd Date: Mon, 31 Oct 2022 10:19:03 +0100 Message-Id: <20221031091903.531009-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194345957840162?= X-GMAIL-MSGID: =?utf-8?q?1748194345957840162?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi index 93688a0b6820..9f2d983e082d 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi @@ -163,38 +163,47 @@ CPU7: cpu@301 { }; L2_0: l2-cache0 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_1: l2-cache1 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_2: l2-cache2 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L2_3: l2-cache3 { + compatible = "cache"; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; cache-unified; + cache-level = <2>; next-level-cache = <&L3>; }; L3: l3-cache { + compatible = "cache"; cache-level = <3>; cache-size = <0x800000>; cache-line-size = <64>; From patchwork Mon Oct 31 09:19:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13162 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203401wru; Mon, 31 Oct 2022 02:22:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6t3TFROdHEVlxP2FQhPw2iKyQXFWqt0Wv0YoAraidSjHxUbjP+SaaVH6INPbAV+o8Ii1Xj X-Received: by 2002:a17:907:e8f:b0:7ad:923a:5a2c with SMTP id ho15-20020a1709070e8f00b007ad923a5a2cmr11678221ejc.736.1667208153666; Mon, 31 Oct 2022 02:22:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208153; cv=none; d=google.com; s=arc-20160816; b=aXbClQfrWq2CXUch4Z5riUDl0WrCYqbS5aF7040JIRFgb9W/MJzPyZjfkISQMQHCsp aFlCSltvAzDyCjPTvtU8e4hOKuQRbgP23WbveyCmq0ME2mX+vt18UAbmTYR01ulTwpiq OMhJ2T8A2ExzFr0Cih/TLpbH1Jxzpa8Ov4jeQ0HAj5v4rq3LQBWhXekuzn8FZYXQELEV AuWL+GBEgb6ehgLfkX/0ues7F8S9+jnUSYOMaXI3Fn+49vfkcumyt0Xij5v3MhvdhaUm p/ZDJjbFHsACFF570MsUaZQXW07LGMUec3+PrkvA/9+AmDxyL751DrbE+2/Bympp057V /dRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=TPuTBa6RefuFIXiIrZ8rhd2wM2v3yLNz8gBguxmEjDg=; b=cht3bv4mp01gH9SQ4dgsQCOv0nK4sqyy6S/p+bQGcruROtXBBZHnnM4DGLEONevhPd Ykugz1JhE7jKYHjQdY409QgHgxovGubtgY+GdNGm9qzEjMxKdz90lYXglHPB7IWApi/u j2T8w9O/jsBNAOWa6sqfSH0JDUOkavev1/pxJ6GwVviAwVBweQBNo154j/AIWY22NObK eR5J2wuTA0oTs5lIxBXsg55qu3iDVeBH8q14wJw3qpiFwsz0XEqq6vJYfz6eUJD6hM9n t2DIlQmtGAdtMDW28d/KWCb2lxjmBCsQHsmr1Uhq5SuK9wjleROMLxRdgEPwndLiempq R9sg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hq9-20020a1709073f0900b00782b261ea21si7539175ejc.729.2022.10.31.02.22.08; Mon, 31 Oct 2022 02:22:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbiJaJTi (ORCPT + 99 others); Mon, 31 Oct 2022 05:19:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230202AbiJaJTZ (ORCPT ); Mon, 31 Oct 2022 05:19:25 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E92F6DF04; Mon, 31 Oct 2022 02:19:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C477B1FB; Mon, 31 Oct 2022 02:19:29 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9D6633F703; Mon, 31 Oct 2022 02:19:20 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Subject: [PATCH 02/20] arm64: dts: Update cache properties for amlogic Date: Mon, 31 Oct 2022 10:19:18 +0100 Message-Id: <20221031091918.531607-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194457120310684?= X-GMAIL-MSGID: =?utf-8?q?1748194457120310684?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 1 + 6 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index b4000cf65a9a..d2f7cb4e5375 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -36,6 +36,7 @@ cpu1: cpu@1 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 04f797b5a012..1648e67afbb6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -105,6 +105,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index fb0ab27d1f64..af23d7968181 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -50,6 +50,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index ee8fcae9f9f0..9978e619accc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -105,6 +105,7 @@ cpu103: cpu@103 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 023a52005494..e3c12e0be99d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -132,6 +132,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 80737731af3f..d845eb19d93d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -88,6 +88,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:19:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13153 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2202935wru; Mon, 31 Oct 2022 02:21:09 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5E4Sz03/dxy1kMCdiUnMrCVS3vQggHSImDTpRyEfsywBntk8fijqyaZgac13WUhnogCSQh X-Received: by 2002:aa7:d650:0:b0:462:d945:3801 with SMTP id v16-20020aa7d650000000b00462d9453801mr12636245edr.117.1667208068887; Mon, 31 Oct 2022 02:21:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208068; cv=none; d=google.com; s=arc-20160816; b=k9DaQDUwT5xgEhAeFhZvj9n74tcx9UGDLyOoMVd03h37jRqGrmmK0G0ngL+D3MNTIw St0nIu6gCcLPIM1gxHtYxwqX8R7Z2/FWyzmJta3wNUN9wTJtlnRFCamjS1PODDOHVVZG D3GEtcMYLAZzGJJrtEHEUYTPUN7X2lp9xSHsIVNFRlMvZcK4HWuGsQq8mGpAUMTIZfKA AQtbhm4t0UBEdUaTLf7gAA7oz6kDR7MBxafYwFr/N0YboG0s9aeOpN+oTSH/tCIj93fo 8oxy/z4JBLPBC2qYqKsb5QsAzZ1EjhzbGjy0KNGoY7qYPs4+kzAcm6ukWKv5WlO62ksf xHqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=G+BOgD6M/Mzc16wrykdvF6oW8q/qQ4nUbmwI9r6Vy1Y=; b=1LNzFK208QhIfAbX2BtsHP7vYEOusFaLBKtH9Ion/2OaO0WyptButirjiqQ4mDcxCB IBgg3Jn2u7jkOiPah1Gn5SBfxPUY5ee88tUsiz6JdckHhGgpJ1rHtQ+51NihXVW2ix3j GN7GC6drEcGhoBEfA6DQJWfZp7kYRImspLVawmNb+mWXIcg+eRap4CE+k+D01X6YBleC v6NePUUBUOoWUdDBSvTJorfnfUQEmduZyN/F2O1wUsTB34IE7DGXfc3pwtarazmj8S7+ XCaKGEJYC4Xd+yOBvEfzOKwWExxl9WE9XNyVzZ63priJvgy1WjZOx1iEefktjZvZAbXk LaoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g12-20020a056402090c00b00453a0393deasi8763165edz.368.2022.10.31.02.20.45; Mon, 31 Oct 2022 02:21:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230297AbiJaJTo (ORCPT + 99 others); Mon, 31 Oct 2022 05:19:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbiJaJTd (ORCPT ); Mon, 31 Oct 2022 05:19:33 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0DCABDEE8; Mon, 31 Oct 2022 02:19:29 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 207FC1FB; Mon, 31 Oct 2022 02:19:35 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D9B113F703; Mon, 31 Oct 2022 02:19:26 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Khuong Dinh , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH 03/20] arm64: dts: Update cache properties for apm Date: Mon, 31 Oct 2022 10:19:27 +0100 Message-Id: <20221031091927.531688-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194368089934554?= X-GMAIL-MSGID: =?utf-8?q?1748194368089934554?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index a8526f8157ec..68ba865fcd58 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -97,15 +97,19 @@ cpu@301 { }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index f56d687f772d..9ac7417f65eb 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,15 +81,19 @@ cpu@301 { }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:19:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13154 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2202986wru; Mon, 31 Oct 2022 02:21:16 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5VOp04oQy+RcwQTEwhstZJwRjP8M9wwo1PrGRz2Mo8ZdQDu46J/VByW9aUCixbXYqZ+Tx1 X-Received: by 2002:a17:907:9493:b0:796:1166:70c4 with SMTP id dm19-20020a170907949300b00796116670c4mr11565339ejc.59.1667208076261; Mon, 31 Oct 2022 02:21:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208076; cv=none; d=google.com; s=arc-20160816; b=oLTlzI1NmrYkwBG51WiQXTTlZUFhXC/0WPlRqP6IukZgDH7fdbrj0gHcFBEoHedLD4 8QbxuCKx2KiO+plhQzOwoDv7ZJw7dXIz52tYVsIAJ0YwVjlQA2xR+feu7wVyKxmdXX0T TWdnU3P0rwmUx+v0OINh6J9W45cFpDtxmIz0WvrzaF+0vEgbIQieohWImw3UGgDODAP4 r8QQLv3ymkRgExT8SJOxzpoOVycGBCGC2OP3ZDKE623oUoGso60oM77UmVLc1f/2aWGN joLri/ew1lbpERilVwt7AmcioAI+PfaT2Q+gZmrQkZnnpqoAWqUfCIrX9qnkDMDuNJ0b N+Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=+v2WJleVDHcacgNS+/RnDCbnc8YrFuSLcihJ3EsLHVY=; b=UIsaV5NjSk2Ghkz+5P00aAW7NJdHcuYS/FxTVyx8l+lO2T5RSbFhwlXAge+QU3sPxM hEa6GFR23iZSdbHLgLDGugofmj5FdDjT1nQCkNW8aG+FOiaYQC4sYwT9punn/oAhLfqO qLA7SZWcikzzAkKmQqP7VkXeYp6i5XD7i66tg5vox3/zLkWUsWeDRhG9Ez7D+Aqzod9a 8SjETj6zCh1m0iaG8TO072AePZMFaKwoW0dM2zYLu+zdXIG49ARupx3oM2mMabZwDWcN IUY1YFH1wo+4lwBx9wkgEvnUJL3vSEXeqvCKEI9hjEr6CsLGDLRgRJp7DaBnmNP74lP+ UvrQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sd26-20020a1709076e1a00b0078db6f56d51si6751991ejc.808.2022.10.31.02.20.52; Mon, 31 Oct 2022 02:21:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbiJaJTz (ORCPT + 99 others); Mon, 31 Oct 2022 05:19:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbiJaJTi (ORCPT ); Mon, 31 Oct 2022 05:19:38 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 112C8DE85; Mon, 31 Oct 2022 02:19:34 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 255521FB; Mon, 31 Oct 2022 02:19:40 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 84EBE3F703; Mon, 31 Oct 2022 02:19:31 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 04/20] arm64: dts: Update cache properties for arm Date: Mon, 31 Oct 2022 10:19:32 +0100 Message-Id: <20221031091932.531749-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194375761328781?= X-GMAIL-MSGID: =?utf-8?q?1748194375761328781?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 + arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 + arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 83e3e7e3984f..c8bd23b1a7ba 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -58,6 +58,7 @@ cpu3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index 258991ad7cc0..ef68f5aae7dd 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -71,6 +71,7 @@ cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 5b6d9d8e934d..796cd7d02eb5 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -57,6 +57,7 @@ cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:19:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13155 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2202999wru; Mon, 31 Oct 2022 02:21:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5aVBW3V0axoPhYWmuVzUDW3Asajxw4g7Wkrh9D5Bd6gYPQC0f/fqwZ4zBrk0NhEkrAZowf X-Received: by 2002:a05:6402:194d:b0:461:8982:52b8 with SMTP id f13-20020a056402194d00b00461898252b8mr12517121edz.49.1667208078097; Mon, 31 Oct 2022 02:21:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208078; cv=none; d=google.com; s=arc-20160816; b=jhpwO9jksLadHUoy7DnAAT6/e5zsf146E6AsgyQzLyzBzrGQNsC8BwxX4YV1WPu5th LOVsmjPEyecJfzQptTsCeY71PDbUx1D5NgnrxAw0uIKqcSeFEe5DEzOpaezudpouqQdZ I2a8BbVAm00DUt4aMnvdDfjR2oJmiDW29Uax0TUL7mW1DyIAJvecG0ATDsZZOZ6b1cPw TLmsLQeklVB3gkDRc3jd5m2f5a6K+vAXzsIqF0yMHQR1Rx1rOrdiJtK7kNCLUtzDQ58n Ib3n1q/1MkAXS6JB+ylureayvecziVkFt1SNmSjDUmJLBPPvFH4G0auoACtJXSIxcka1 Peww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=n+S596bL4LZF61CcFkT53aasv6/DvepURk0/QgXxn+8=; b=g39ZfimeErMRXtq2xju76YQ4F1lI7u+7v/FqVJy0c1dxqWovTwuvVpnLtZSa7QbuVq qY6iW9wBAraF9MetVws31WluxVFkv9f85VqwmIw0dE+LyK4vgSXYtHmdiIMXR+pEMNjz IKIwYR/c6bSEPCmApRWY32r9zHXG9Qu4MF2rMBduVGl73CYE3rl/z0t58T2YpChhljTB G2B9CDnOpCB9LziujU22hdxm+DibXdTRJ1fKglKiV9eVfWmkFZm+H3a/dvL7L+clgypH hVykO3j8GBxoKAhXXcd/uQj+OnGjt1d8W+uXWj7uZGbAXNsZnE6JvbUwm4kF5qD78CG2 Lm8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a26-20020a1709065f9a00b0078dd7383ed8si5840451eju.414.2022.10.31.02.20.54; Mon, 31 Oct 2022 02:21:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230300AbiJaJUD (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbiJaJTo (ORCPT ); Mon, 31 Oct 2022 05:19:44 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 00075DF33; Mon, 31 Oct 2022 02:19:41 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09DB81FB; Mon, 31 Oct 2022 02:19:48 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2635B3F703; Mon, 31 Oct 2022 02:19:37 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/20] arm64: dts: Update cache properties for broadcom Date: Mon, 31 Oct 2022 10:19:37 +0100 Message-Id: <20221031091938.531810-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194377601433384?= X-GMAIL-MSGID: =?utf-8?q?1748194377601433384?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Acked-by: William Zhang --- arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 + arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 + arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++ 9 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 967d2cd3c3ce..5035a3cc90e0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -63,6 +63,7 @@ cpu3: cpu@3 { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index 3d016c2ce675..d5bc31980f03 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -51,6 +51,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 04de96bd0a03..6f805266d3c9 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -35,6 +35,7 @@ B53_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index 13629702f70b..b982249b80a2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -51,6 +51,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index c3e6197be808..a996d436e977 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -51,6 +51,7 @@ B53_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index 0bce6497219f..62c530d4b103 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -35,6 +35,7 @@ B53_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index 29a880c6c858..ba3d5a98ccbc 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -50,6 +50,7 @@ B53_3: cpu@3 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index fda97c47f4e9..18cdbc20f03f 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -79,6 +79,7 @@ A57_3: cpu@3 { CLUSTER0_L2: l2-cache@0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 8f8c25e51194..e05901abe957 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -108,18 +108,22 @@ cpu@301 { CLUSTER0_L2: l2-cache@0 { compatible = "cache"; + cache-level = <2>; }; CLUSTER1_L2: l2-cache@100 { compatible = "cache"; + cache-level = <2>; }; CLUSTER2_L2: l2-cache@200 { compatible = "cache"; + cache-level = <2>; }; CLUSTER3_L2: l2-cache@300 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:19:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13156 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203082wru; Mon, 31 Oct 2022 02:21:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5tmkjV8cnK0gD7+UwTUyHaKr8DYk1lJqKH5Tzm4NVqmnyTUBrbdNbSLf9dKCHm9QyInJGY X-Received: by 2002:a17:907:3da2:b0:78d:45df:b4f with SMTP id he34-20020a1709073da200b0078d45df0b4fmr11514842ejc.651.1667208092237; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id dn19-20020a17090794d300b007824786a7easi7868196ejc.724.2022.10.31.02.21.06; Mon, 31 Oct 2022 02:21:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbiJaJUN (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbiJaJTv (ORCPT ); Mon, 31 Oct 2022 05:19:51 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4A8C3DF35; Mon, 31 Oct 2022 02:19:47 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5754823A; Mon, 31 Oct 2022 02:19:53 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AD2403F703; Mon, 31 Oct 2022 02:19:44 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 06/20] arm64: dts: Update cache properties for exynos Date: Mon, 31 Oct 2022 10:19:45 +0100 Message-Id: <20221031091945.531874-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194392463299707?= X-GMAIL-MSGID: =?utf-8?q?1748194392463299707?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bd6a354b9cb5..e9eda46801f8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -229,6 +229,7 @@ cluster_a57_l2: l2-cache0 { cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; cluster_a53_l2: l2-cache1 { @@ -236,6 +237,7 @@ cluster_a53_l2: l2-cache1 { cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 1cd771c90b47..aca1c32a6411 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -110,6 +110,7 @@ atlas_l2: l2-cache0 { cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:19:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13168 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203794wru; Mon, 31 Oct 2022 02:23:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5CCIZ2ps+6qCWT97+pVI6nITSigmrwGztE1LOLzGLKwSFblDTmfjqbA0OIbXYTS6F7pNp3 X-Received: by 2002:aa7:cb59:0:b0:461:7378:7be0 with SMTP id w25-20020aa7cb59000000b0046173787be0mr12725955edt.60.1667208218528; Mon, 31 Oct 2022 02:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208218; cv=none; d=google.com; s=arc-20160816; b=wBm2Ap8tq0Kf2x1NVaJUVzdx3XBDkUfAASgzZMAsbI3dOaWWXBmz3+XpawYhKXInRn BY9686Klk6YtIm3qprzRonMrl7wywHJyWP1rU02AHcHWaJIs9hUe0K/YwZo+oNma+WzS tCeNEqao2kmuQyOd8boUZmHYvw7TehYGkU3uQwdUGfBpVV/DTkgS89byz7Kjy4nHjeYY 4q9nHow9jrqb/8chvMUcZ0FHIrQ0P1Jjod/YWz5sgMrO9lCv31uv6MJfsXqDWgp+KInC 8KIjIugNV4qjm5xixKAVnNOjby1buFPDh9setcgpnNighCaa/5UbyStE/Lbkb7LimWbA YKJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=J5Gh/+TJbWcfiHg6s6TXC5P+U55OtwGVHvUGb54vcIw=; b=QSqUiAe6CPaJqRmO3uHevqYz0DketWm3ofNut7IQd0m/40wzxtnkXOe++iigYF9/kO Jl2WoG9LWrZJDX3q03vM0Vlb2feT3/8u3d29yyON+X3rsnTqKxMHY770IsgOM0vL+8e4 DqolcYDTNFDuOg2PFY7rKayxw0fEjpZ0CD+UN5F67c7dNvGguCWUTTpB2tQ/Yz8heEKQ Cj6qj6y+7ZbA+TFkSMwhap7isAyjuS6isoGOqH/8oWCPBq7k6tuPqkRhho5IpIkogpZu l4LDuKemRUCVY1FS1OvCKVCt0xvBaOjEXSViBUtvsVIymOn3U/hszQ3+VEBbCf03abTu vY7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ce12-20020a170906b24c00b007ab34c9d9d3si5842258ejb.733.2022.10.31.02.23.15; Mon, 31 Oct 2022 02:23:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbiJaJU2 (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230150AbiJaJUL (ORCPT ); Mon, 31 Oct 2022 05:20:11 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 88315DF31; Mon, 31 Oct 2022 02:20:00 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DD451FB; Mon, 31 Oct 2022 02:20:06 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 44AFA3F703; Mon, 31 Oct 2022 02:19:56 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Shawn Guo , Li Yang , Rob Herring , Krzysztof Kozlowski , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Chester Lin , =?utf-8?q?Andreas_F=C3=A4rber?= , Matthias Brugger , NXP S32 Linux Team , Peng Fan , Jacky Bai , Sudeep Holla , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 07/20] arm64: dts: Update cache properties for freescale Date: Mon, 31 Oct 2022 10:19:51 +0100 Message-Id: <20221031091956.531935-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194524557769136?= X-GMAIL-MSGID: =?utf-8?q?1748194524557769136?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Chester Lin Acked-by: Li Yang --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 1 + arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 ++ arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 ++ 8 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5627dd7734f3..ed0cc1a5d17e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -46,6 +46,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index ca3d5a90d6d4..c8b1202d2584 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -83,6 +83,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index feab604322cf..4590bdc076b7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -78,6 +78,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 6f6667b70028..2a7e13b6ef8a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index c3dc38188c17..c12c86915ec8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -95,18 +95,22 @@ cpu7: cpu@301 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 60c1b018bf03..187353458673 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -50,6 +50,7 @@ A35_1: cpu@1 { A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 824d401e7a2c..d8c82da88ca0 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -52,10 +52,12 @@ cpu3: cpu@101 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index ba0b5305d481..3e306218d533 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -61,10 +61,12 @@ cpu3: cpu@101 { cluster0_l2_cache: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:20:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13159 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203232wru; Mon, 31 Oct 2022 02:22:07 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5whFaTV9zcXoJN+m0Ff2qQCUGCaQ5lOEY04l7zWX7Y2b9SZGEPuql1SxPDPitfHgLq9XA8 X-Received: by 2002:a05:6402:1e88:b0:461:a513:f543 with SMTP id f8-20020a0564021e8800b00461a513f543mr12842626edf.183.1667208127343; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id cz11-20020a0564021cab00b0045c9dbe290csi6051040edb.406.2022.10.31.02.21.43; Mon, 31 Oct 2022 02:22:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230193AbiJaJUl (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230280AbiJaJUW (ORCPT ); Mon, 31 Oct 2022 05:20:22 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 32702DF62; Mon, 31 Oct 2022 02:20:07 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69A9D1FB; Mon, 31 Oct 2022 02:20:13 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2E6043F703; Mon, 31 Oct 2022 02:20:04 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Wei Xu , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 08/20] arm64: dts: Update cache properties for hisilicon Date: Mon, 31 Oct 2022 10:20:04 +0100 Message-Id: <20221031092004.532113-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194428971334082?= X-GMAIL-MSGID: =?utf-8?q?1748194428971334082?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++ 5 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8343d0cedde3..a57f35eb5ef6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; A73_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index ae0a7cfeeb47..f6d3202b0d1a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -186,10 +186,12 @@ cpu7: cpu@103 { CLUSTER0_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 7b2abd10d3d6..5b2b1bfd0d2a 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -211,18 +211,22 @@ cpu15: cpu@20303 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2f8b03b0d365..291c2ee38288 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -211,18 +211,22 @@ cpu15: cpu@10303 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 1a16662f8867..b8746fb959b5 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -842,66 +842,82 @@ cpu63: cpu@70303 { cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; cluster4_l2: l2-cache4 { compatible = "cache"; + cache-level = <2>; }; cluster5_l2: l2-cache5 { compatible = "cache"; + cache-level = <2>; }; cluster6_l2: l2-cache6 { compatible = "cache"; + cache-level = <2>; }; cluster7_l2: l2-cache7 { compatible = "cache"; + cache-level = <2>; }; cluster8_l2: l2-cache8 { compatible = "cache"; + cache-level = <2>; }; cluster9_l2: l2-cache9 { compatible = "cache"; + cache-level = <2>; }; cluster10_l2: l2-cache10 { compatible = "cache"; + cache-level = <2>; }; cluster11_l2: l2-cache11 { compatible = "cache"; + cache-level = <2>; }; cluster12_l2: l2-cache12 { compatible = "cache"; + cache-level = <2>; }; cluster13_l2: l2-cache13 { compatible = "cache"; + cache-level = <2>; }; cluster14_l2: l2-cache14 { compatible = "cache"; + cache-level = <2>; }; cluster15_l2: l2-cache15 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:20:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13157 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203143wru; Mon, 31 Oct 2022 02:21:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5PvZQg73rx5QNlyT61C3LzJ9lTDr0WfEw73ZGiNnpx2jcrK3TtbpPd7ke7/9m8tf+7mgjx X-Received: by 2002:a17:907:2705:b0:7ad:855d:1050 with SMTP id w5-20020a170907270500b007ad855d1050mr12071860ejk.443.1667208107720; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m17-20020a056402511100b00461f2b974d2si7654426edd.339.2022.10.31.02.21.24; Mon, 31 Oct 2022 02:21:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbiJaJUp (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbiJaJUY (ORCPT ); Mon, 31 Oct 2022 05:20:24 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 71918DF07; Mon, 31 Oct 2022 02:20:12 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 863CA23A; Mon, 31 Oct 2022 02:20:18 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 19A883F703; Mon, 31 Oct 2022 02:20:09 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Chanho Min , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 09/20] arm64: dts: Update cache properties for lg Date: Mon, 31 Oct 2022 10:20:11 +0100 Message-Id: <20221031092011.532395-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194408813379792?= X-GMAIL-MSGID: =?utf-8?q?1748194408813379792?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/lg/lg1312.dtsi | 1 + arch/arm64/boot/dts/lg/lg1313.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 78ae73d0cf36..25ed9aeee2dc 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -48,6 +48,7 @@ cpu3: cpu@3 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 2173316573be..db82fd4cc759 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -48,6 +48,7 @@ cpu3: cpu@3 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:20:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13165 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203452wru; Mon, 31 Oct 2022 02:22:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM58Gm4v+x/HKoFfoAW3herMxjhJEtWNW4mjHP1yIxWiJcXqcpm/mU/5REbfLQuiUutTl82C X-Received: by 2002:a17:906:5ac2:b0:78d:3358:7694 with SMTP id x2-20020a1709065ac200b0078d33587694mr12133905ejs.276.1667208164531; Mon, 31 Oct 2022 02:22:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208164; cv=none; d=google.com; s=arc-20160816; b=H8OV9ROjq2RAQ81CIPqdqDYuHab93nAxD5TKe029/G0fPYr4lVnz+/KnIjAnsaWh1l nmbMxYlKmW17emDFO4CXH/q572QQn+Mh99lO/eecYLVMucjzg1pc0IJNQ2JKYH1+TJtk tfT8XGupvqWgGIu74eUEUU+spKqWcs82xZc0mAp+QgPJhqwKJe8vsWVZLSdJyr34Ae17 UC0OTsqFgMWgBb8lRCAxgGVOR2UdAtyOxZCbxpazLeQu3DDXwQF5bSKReZDl0gOgJ6XE B/XUNl9srN72vcOL0Pz8wnZBjxowPPK/sKkVTsYQ9oDNPGpBtq6DVA/VggzkbNeVxuHF 3LJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=ZWQ2JjsS4ZRyVj5gF9LEiyR9aih+rB9csFLlZu4KWrI=; b=jWp49+7wxYha4i0lxnTF3gv91XgrTq0HSBaKKDFUmwTx2Wqj7JnDYmQnCAJXptzFsQ r68LjUjkn8cVudWxkYkGO9Z2s7krWW0Tm4VJlXJ1rEE2Yh9gJW8NCttD12G4HJHxn+9K u6PIwvC1ZQVdQpuwkZ1sQJZN45L5wFLlbltaJTrtR+7rv6dVcZiTCejTi3P3RZgFkkfc jyEO7lzwFNpx9whwq8hEbFkpDYZCOmdqlGhbi1JSheOyAOS7Ig6Dw363ZrrGEuFLdgpK UXjfRPZ15MTLpgBjddOc2vKr5hfg4+i6cyZeB/kDkD0XYx/cg85rbdOHO83EDn0yVjxv 8ABw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dm19-20020a170907949300b007919f213511si6760827ejc.951.2022.10.31.02.22.21; Mon, 31 Oct 2022 02:22:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbiJaJUv (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230165AbiJaJUa (ORCPT ); Mon, 31 Oct 2022 05:20:30 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DC095DEE1; Mon, 31 Oct 2022 02:20:21 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF5E723A; Mon, 31 Oct 2022 02:20:27 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DF00E3F703; Mon, 31 Oct 2022 02:20:18 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Vadym Kochan , Chris Packham , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/20] arm64: dts: Update cache properties for marvell Date: Mon, 31 Oct 2022 10:20:16 +0100 Message-Id: <20221031092020.532456-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194468585678226?= X-GMAIL-MSGID: =?utf-8?q?1748194468585678226?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Chris Packham --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ 4 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 80b44c7df56a..d4770acec6ac 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -49,6 +49,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index fcab5173fe67..990f70303fe6 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -51,6 +51,7 @@ l2: l2-cache { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 3db427122f9e..a7b8e001cc9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -81,6 +81,7 @@ l2_0: l2-cache0 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ l2_1: l2-cache1 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 68782f161f12..7740098fd108 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -81,6 +81,7 @@ l2_0: l2-cache0 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ l2_1: l2-cache1 { cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; From patchwork Mon Oct 31 09:20:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13158 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203220wru; Mon, 31 Oct 2022 02:22:03 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4iqJ8rs5YMXpBPQmONEOw802jEp7QOLETa/HVv7exG8I1teXanBRFvUOWoz3gQm8rI57dB X-Received: by 2002:a17:907:3d89:b0:7ad:b97e:2949 with SMTP id he9-20020a1709073d8900b007adb97e2949mr8672541ejc.686.1667208123543; Mon, 31 Oct 2022 02:22:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208123; cv=none; d=google.com; s=arc-20160816; b=QY5HUoxr8IFDLdj+vb+fu9hF3t+wBOv11Sc9Pnh9IXdQtNnEYvSf17ahAV7yHvRsWC iKX/1B4rGLa+fC0V1puKzgn5gbAEUCuMUMiuit94PGh1PkPApsu5Wf7vOH3Z/yTM7w/s YXA0ggE5iy6JEt4MyHlcIzF68Hi862bKwIljKs1rdl64qYuwqijgSp5WYZkAW0q7N4yf MGvQw20kd7gw5iiKFuTG7nsNdrW4x8irQZzNwF+AgiVf1mQi+57TC5NLTdinoaTf1Hg5 A1osNkkbj5B+5d2WOJWLrsUR8KVx0IzoLETru0EM+m5rvUisQlZX3gMFdvcl8KCw1YKz Zf6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=xqodkPfeVGhOUk8WuAgsO02qopi2iCHVpqEEckFqj4g=; b=BbbYFppqVeGD1NIm30QQuOOaAF7gbVWOVvWTSKoE43B1uvwJ3kOER5DpTMOiiQVWEP t31AXajJjhGVK+bWpsz9j9UEXn8f5OxtR6SAtV6KHQgfPCmj3U4OpOZ/caloHd7DEwL8 bALtUSLLsVzgkwjXEE6+4UHuDuu3ykeGgnTz4XtEYzfk32bZ4Naby5MWIyhc9JSdM2Q1 Kmp3fuVj1v8Eju8Pgp2AvslF2xTqaeRc6JKy/Mr7wDX5C6/OU/LNzDFlL2O0rk5z9GPy RMx5OHAIhRny8zoXM0m8P+hC/IlvmqmKgUKeMzcFLEcrxkPpD2p8vE/105zEobXvKMUI KKYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qk18-20020a1709077f9200b0078d3b4510b5si7933574ejc.854.2022.10.31.02.21.38; Mon, 31 Oct 2022 02:22:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230185AbiJaJUy (ORCPT + 99 others); Mon, 31 Oct 2022 05:20:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbiJaJUf (ORCPT ); Mon, 31 Oct 2022 05:20:35 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 01D4BDEE7; Mon, 31 Oct 2022 02:20:27 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16EA11FB; Mon, 31 Oct 2022 02:20:33 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8A0E13F703; Mon, 31 Oct 2022 02:20:24 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Matthias Brugger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 11/20] arm64: dts: Update cache properties for mediatek Date: Mon, 31 Oct 2022 10:20:25 +0100 Message-Id: <20221031092025.533051-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194425587031449?= X-GMAIL-MSGID: =?utf-8?q?1748194425587031449?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cbae5a5ee4a0..9a20055ec1fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -159,16 +159,19 @@ core3 { l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; idle-states { diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 066c14989708..2e73db4229d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -197,16 +197,19 @@ cluster_off_b: cluster-off-b { l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; From patchwork Mon Oct 31 09:20:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13160 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203241wru; Mon, 31 Oct 2022 02:22:09 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5WRUvXKyRaHCNH0/JBqWOoflgjYBwsVUWAzjZLXls6vS/ERTdzRKjFk4L0gePGofxXCLz4 X-Received: by 2002:a05:6402:410:b0:451:ea13:4ed7 with SMTP id q16-20020a056402041000b00451ea134ed7mr13176372edv.262.1667208129402; Mon, 31 Oct 2022 02:22:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208129; cv=none; d=google.com; s=arc-20160816; b=D0hQiPLg/Xq3+tWVpUPUC8IOtOCTQHcLOQg34tIHQuWXN8Z6IOHeCD6rkTbXmjBwkI KQBD5VCRgfOdsM09sRGhn5QAYdN7Ya6dpXkynSBWnztThNN7zhYpr6+RF4tXheS9P+ls 6AnODMNos8Tvw3mtAxiBVG1D1D1IBR8XT9jQrqzKqB6dyrDBS7lDQddYIn+Ajfp51Ocx kvQff+iX/5gTZM+LjGEu5smVRKEpqcRzIT+TpydCUxPqFW94DV4jXwK/aG5WgmIdnhgq 9nHvqlESTvUDOmMqoZCdmYeO/0dQtSS7rNdDJXT8U8a3Afgi35zGLiIXvlRYbhlzKSQ+ ytaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=nsbx1M2kMMHFTsnHMAKGlrb+0inPndEAVqlzTNwK8s4=; b=iuDM/B8A6EOyPG/A29NiRIQeojADlhN+7AjbfdFo6ATv3eb1pzRFPU7qNaJlXYx2Qe NcoH+qU9+y3X26q/Tmsb+xvikekHwchPnTEaKbTqrvS1Qs5cAyiFIBDY0+oxLNcn74KO 3DDikNBlFjqF9EkdDCgtnVimpv0XHs2SUimsPRr7SdhCGRmUyFjqPt0iIopXZ4GOopKd 8bHsFLZG9GAlqM5La1pCbvlXBXcmCuM+XzYar+jOhJD4OvBSKLlMdDkyV6iXpJWgVdrY N+08iVoQUW/pU66W5MeIZpI4GTb7sjbCGU3nNEJ+W3SUHm+rD/FgOIU2ohgQfjRa+Ykj IXIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id fj4-20020a1709069c8400b0078adad5930esi8069587ejc.255.2022.10.31.02.21.45; Mon, 31 Oct 2022 02:22:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230370AbiJaJVE (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230329AbiJaJUi (ORCPT ); Mon, 31 Oct 2022 05:20:38 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9DB6BAE58; Mon, 31 Oct 2022 02:20:32 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B2A831FB; Mon, 31 Oct 2022 02:20:38 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BB0AA3F703; Mon, 31 Oct 2022 02:20:29 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , UNGLinuxDriver@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/20] arm64: dts: Update cache properties for microchip Date: Mon, 31 Oct 2022 10:20:30 +0100 Message-Id: <20221031092030.533116-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194431499278761?= X-GMAIL-MSGID: =?utf-8?q?1748194431499278761?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 2dd5e38820b1..c4bca23b96b9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,7 @@ cpu1: cpu@1 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:20:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13161 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203329wru; Mon, 31 Oct 2022 02:22:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6cpm+C+5UiW0+XqRvTnVk7nWtvlvyDdSoA5IbLkOu81lhp7QceVLGSYr32D7tcu0QlUBk5 X-Received: by 2002:a17:906:9745:b0:78d:480f:cee7 with SMTP id o5-20020a170906974500b0078d480fcee7mr11803160ejy.192.1667208144520; Mon, 31 Oct 2022 02:22:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208144; cv=none; d=google.com; s=arc-20160816; b=hhoXbFOsgDe3yfyNXDQv+peicv+9M9EodP5sFMTh6jkA4tMtB/OqjZj4xf4WfNXvIm VEG+bAcBncvMg5QsJhaa2w1cQW3EKQY1RYWivenUqwjZIxSLjBKka8IjiOpQSma83xaR EnEiImGqOn/m/KPTNXh9bTFMrAr7LkSZtkwzJySrmjw/McmkVt+z3KWdOAgfOE+Eh8U2 6LMkHXKNiw5aKeidh75PmwDBCPPx5VOVkWHsvQL1PLuV5m/bQnE2EYH7YsOa5jKolIhc HUSDzvZI3r993Mq4WsJIgv4CyN8A2F0RV/xEt9OE+znFioROWdCWnux29SGXuNOhB9YW Wyig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=2dZQdjXZDnr0kPrONuWwIerLpgEZXiSZbUpOREt60i8=; b=D0UnSP0jppbsX74XSvUg1r6c/Wklg9P/Z76SRkiyCYiu8W/OWAHJXSgiUh+0Ytlv2p 1n4TKi0XtLqpBOZknHj8oqdil322cwtDaQNC+h+XdNS9bLwLABfp6bgMk77PXXfWjy7f BzcaX4qnbWMOavTzvFymfWXZgeKTKk5hspe38hUDQxY1nhG9YwGmmBi6W7okBVplKBY9 sIHUQEb3hbaIVsZ+XZHxaRnztAxC4VaHnwS9We2Uh/Y9KFF/Maud67ioMk3Uw45ozLkl J7rVIcjaZbU8Otu7RRv0v+Mi+9Uz2HuaKe9HxDECRD81TCVSNftlKPsrYs/WFBStd9mq Z6yA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i20-20020a1709064fd400b007a5cdd9550esi8504644ejw.201.2022.10.31.02.22.00; Mon, 31 Oct 2022 02:22:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbiJaJVO (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230200AbiJaJUo (ORCPT ); Mon, 31 Oct 2022 05:20:44 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2B940DFAE; Mon, 31 Oct 2022 02:20:38 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3F85A23A; Mon, 31 Oct 2022 02:20:44 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D86B83F703; Mon, 31 Oct 2022 02:20:34 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Rob Herring , Krzysztof Kozlowski , openbmc@lists.ozlabs.org, devicetree@vger.kernel.org Subject: [PATCH 13/20] arm64: dts: Update cache properties for nuvoton Date: Mon, 31 Oct 2022 10:20:36 +0100 Message-Id: <20221031092036.533177-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194447568377436?= X-GMAIL-MSGID: =?utf-8?q?1748194447568377436?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi index 12118b75c0e6..4c196140634b 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -49,6 +49,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:20:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13163 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203408wru; Mon, 31 Oct 2022 02:22:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5hUJXTrF7rO8s3amPqP2k3QsFnBvAwDjr6tjDOHhhcZt+qamEx3wkZyyq3Z7eZhcJzaXzj X-Received: by 2002:aa7:c956:0:b0:43b:206d:c283 with SMTP id h22-20020aa7c956000000b0043b206dc283mr12549520edt.381.1667208154541; Mon, 31 Oct 2022 02:22:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208154; cv=none; d=google.com; s=arc-20160816; b=K7QaQnFptX3E3stVCFB+nF38EF+f0PJWjOJkjASLN6h3mu5yWLigWMctJgaxdKIfnF XT2apbydlH/1EPPVuq6FE8ely9CbZMVxGeNGPxBwhy3O41O8mZ4/5IV0XHff3Zh2Opsu u9Vv6QYvVTwjKoptebSEhabgDbdYWvI7paTGdTvfYtpedlVSUI3LYzuiRvsYmXdy65id jV5rRfpQjFyOFgg04sBLPok9ixwymPK2tNUKLBXjMsfW2Oz07XLZC0KLb31PYu7Bk9YG M5zl8ICBRwcMefaPZnYk5c+aNmaodQjAHOcos3dU0pTiYiSAR7H/JLXF22iSCVQyiQFu JDdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=eTd+hcqXvK/nxx5Htq/o8F6s2QQ+eMFbB2M8Y2PxEog=; b=X/ntPSb5L99Qgm3ks9Q3N4yg5u4Ncj3T3xAMnCYf3rSB1up3ghydpdCAgU4Ep5Si2T V9nsfp0gi+ZNwPpKp53wg4saN1crWsV3qxYK5hBfRNGzWll0+Vb7Jp7UL6I3jN46GzUA iGLuFtM73CmNJChYUHuS1api6n/BhXU4vyNrzS+G17jXICX13wn2xxw6tDDR3bYMDBNx LN6aaSEr2nOBO3Rxg1iH+qIrpwXbzLgu3K4/njTFhy43Gvvn6QVXHgYe4HERdd5wKJhv Ch/OENdv3VCf/Vv/4Ay818HDxD9Bbi9xrkQ/9EXYkygCmAgT38QeqTAvnKGi8IOgvVtq U8LA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gt41-20020a1709072da900b0078d2a84f2f8si8805344ejc.645.2022.10.31.02.22.09; Mon, 31 Oct 2022 02:22:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbiJaJVY (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230317AbiJaJUv (ORCPT ); Mon, 31 Oct 2022 05:20:51 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D7A1CDF36; Mon, 31 Oct 2022 02:20:46 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA9511FB; Mon, 31 Oct 2022 02:20:52 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EEABE3F703; Mon, 31 Oct 2022 02:20:42 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter , Sameer Pujar , Mikko Perttunen , Prathamesh Shete , Sumit Gupta , Akhil R , Ashish Mhetre , Diogo Ivo , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 14/20] arm64: dts: Update cache properties for nvidia Date: Mon, 31 Oct 2022 10:20:41 +0100 Message-Id: <20221031092043.533238-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194457469529719?= X-GMAIL-MSGID: =?utf-8?q?1748194457469529719?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra234.dtsi | 30 ++++++++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d0ed55e5c860..7508047e283b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2998,36 +2998,46 @@ core1 { }; l2c_0: l2-cache0 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_1: l2-cache1 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_2: l2-cache2 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_3: l2-cache3 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l3c: l3-cache { + compatible = "cache"; cache-size = <4194304>; cache-line-size = <64>; + cache-level = <3>; cache-sets = <4096>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 724e87450605..9474b0da0a3e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2005,6 +2005,7 @@ CPU_SLEEP: cpu-sleep { L2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 81a0f599685f..ca7a570c758b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1792,117 +1792,147 @@ core3 { }; l2c0_0: l2-cache00 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_1: l2-cache01 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_2: l2-cache02 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_3: l2-cache03 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c1_0: l2-cache10 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_1: l2-cache11 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_2: l2-cache12 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_3: l2-cache13 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c2_0: l2-cache20 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_1: l2-cache21 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_2: l2-cache22 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_3: l2-cache23 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l3c0: l3-cache0 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c1: l3-cache1 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c2: l3-cache2 { + compatible = "cache"; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; }; From patchwork Mon Oct 31 09:20:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13164 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203447wru; Mon, 31 Oct 2022 02:22:42 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5222fkFyHxfNsuTons9oWGB2Uw8OKV/QVo1DQZN4/dZCO5tRoBnCB6bhyR6YiSJNpLDhtl X-Received: by 2002:a05:6402:5409:b0:44f:1e05:1e8 with SMTP id ev9-20020a056402540900b0044f1e0501e8mr12697857edb.373.1667208162555; Mon, 31 Oct 2022 02:22:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f14-20020a0564021e8e00b00458985e9d19si8427556edf.632.2022.10.31.02.22.18; Mon, 31 Oct 2022 02:22:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiJaJVh (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbiJaJVM (ORCPT ); Mon, 31 Oct 2022 05:21:12 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6B35ADEFD; Mon, 31 Oct 2022 02:20:53 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E88F113E; Mon, 31 Oct 2022 02:20:59 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 874773F703; Mon, 31 Oct 2022 02:20:50 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 15/20] arm64: dts: Update cache properties for qcom Date: Mon, 31 Oct 2022 10:20:50 +0100 Message-Id: <20221031092051.533305-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194466154685783?= X-GMAIL-MSGID: =?utf-8?q?1748194466154685783?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. About msm8953.dtsi: According to the Devicetree Specification v0.3, s3.7.3 'Internal (L1) Cache Properties', cache-unified: If present, specifies the cache has a unified or- ganization. If not present, specifies that the cache has a Harvard architecture with separate caches for instructions and data. Plus, the 'cache-level' property seems to be reserved to higher cache levels (cf s3.8). To describe a l1 data/instruction cache couple, no cache information should be described. Remove the l1 cache nodes. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 56 -------------------------- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++ 11 files changed, 83 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 8416a45ca4fd..3a01ddba7ee5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -42,13 +42,6 @@ CPU0: cpu@0 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU1: cpu@1 { @@ -59,13 +52,6 @@ CPU1: cpu@1 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU2: cpu@2 { @@ -76,13 +62,6 @@ CPU2: cpu@2 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU3: cpu@3 { @@ -93,13 +72,6 @@ CPU3: cpu@3 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU4: cpu@100 { @@ -110,13 +82,6 @@ CPU4: cpu@100 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU5: cpu@101 { @@ -127,13 +92,6 @@ CPU5: cpu@101 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU6: cpu@102 { @@ -144,13 +102,6 @@ CPU6: cpu@102 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU7: cpu@103 { @@ -161,13 +112,6 @@ CPU7: cpu@103 { capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; cpu-map { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index b82c335c25af..4d66d9148dcd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -146,9 +146,11 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -171,6 +173,7 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -193,6 +196,7 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -215,6 +219,7 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -237,6 +242,7 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -259,6 +265,7 @@ &LITTLE_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -281,6 +288,7 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -303,6 +311,7 @@ &BIG_CPU_SLEEP_1 qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 13d7f267b289..bf2cd427de98 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -179,9 +179,11 @@ &LITTLE_CPU_SLEEP_1 #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -202,6 +204,7 @@ &LITTLE_CPU_SLEEP_1 #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -222,6 +225,7 @@ &LITTLE_CPU_SLEEP_1 #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -242,6 +246,7 @@ &LITTLE_CPU_SLEEP_1 #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -262,6 +267,7 @@ &BIG_CPU_SLEEP_1 #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -282,6 +288,7 @@ &BIG_CPU_SLEEP_1 #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -302,6 +309,7 @@ &BIG_CPU_SLEEP_1 #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -322,6 +330,7 @@ &BIG_CPU_SLEEP_1 #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 49ea8b5612fc..45ef0d419ef1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -188,9 +188,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -209,6 +211,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -227,6 +230,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -245,6 +249,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -263,6 +268,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -281,6 +287,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -299,6 +306,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -317,6 +325,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8ec144919ef1..2aa2a4c80f8a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -209,9 +209,11 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -233,6 +235,7 @@ CPU1: cpu@100 { next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -254,6 +257,7 @@ CPU2: cpu@200 { next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -275,6 +279,7 @@ CPU3: cpu@300 { next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -296,6 +301,7 @@ CPU4: cpu@400 { next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -317,6 +323,7 @@ CPU5: cpu@500 { next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -338,6 +345,7 @@ CPU6: cpu@600 { next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -359,6 +367,7 @@ CPU7: cpu@700 { next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 8c582a9e4ada..1e68475a4757 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -45,6 +45,7 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; @@ -84,6 +85,7 @@ CPU4: cpu@100 { next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d06aefdf3d9e..3305c00a0a77 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -47,9 +47,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -66,6 +68,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -82,6 +85,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -98,6 +102,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -114,6 +119,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -130,6 +136,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -147,6 +154,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -163,6 +171,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 7d509ecd44da..0fc083505776 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -60,9 +60,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -84,6 +86,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -106,6 +109,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -127,6 +131,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -148,6 +153,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -169,6 +175,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -190,6 +197,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -211,6 +219,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index bc773e210023..65dd382a3c40 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -110,9 +110,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -134,6 +136,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -155,6 +158,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -176,6 +180,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -197,6 +202,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -218,6 +224,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -240,6 +247,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -261,6 +269,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e72a04411888..ec5bdd25a580 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -73,9 +73,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -92,6 +94,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -108,6 +111,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -124,6 +128,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -140,6 +145,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -156,6 +162,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -173,6 +180,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -189,6 +197,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4978c5ba5dd0..038e1a53f209 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -53,9 +53,11 @@ CPU0: cpu@0 { #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -72,6 +74,7 @@ CPU1: cpu@100 { #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -88,6 +91,7 @@ CPU2: cpu@200 { #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -104,6 +108,7 @@ CPU3: cpu@300 { #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -120,6 +125,7 @@ CPU4: cpu@400 { #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -136,6 +142,7 @@ CPU5: cpu@500 { #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -153,6 +160,7 @@ CPU6: cpu@600 { #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -169,6 +177,7 @@ CPU7: cpu@700 { #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; From patchwork Mon Oct 31 09:20:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13166 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203536wru; Mon, 31 Oct 2022 02:22:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7SY64RmtvJ7PY/hhQR8tRUaQTLNkPsACqz1C4rpNaoRkseV4Sz7PG5G45HT63Ze0kTYVeJ X-Received: by 2002:a17:907:3181:b0:787:d81c:a6ad with SMTP id xe1-20020a170907318100b00787d81ca6admr11563630ejb.769.1667208178385; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hs25-20020a1709073e9900b007ada3808562si9213474ejc.737.2022.10.31.02.22.34; Mon, 31 Oct 2022 02:22:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230398AbiJaJVj (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbiJaJVP (ORCPT ); Mon, 31 Oct 2022 05:21:15 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0FB33DEF1; Mon, 31 Oct 2022 02:20:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24869113E; Mon, 31 Oct 2022 02:21:05 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 915B03F703; Mon, 31 Oct 2022 02:20:56 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, =?utf-8?q?Andreas_F=C3=A4rb?= =?utf-8?q?er?= , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 16/20] arm64: dts: Update cache properties for realtek Date: Mon, 31 Oct 2022 10:20:57 +0100 Message-Id: <20221031092057.533368-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194482747461636?= X-GMAIL-MSGID: =?utf-8?q?1748194482747461636?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/realtek/rtd1293.dtsi | 1 + arch/arm64/boot/dts/realtek/rtd1295.dtsi | 1 + arch/arm64/boot/dts/realtek/rtd1296.dtsi | 1 + arch/arm64/boot/dts/realtek/rtd1395.dtsi | 1 + arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 ++ 5 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi index 2d92b56ac94d..0696b99fc40d 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -30,6 +30,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 1402abe80ea1..4ca322e420e6 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -44,6 +44,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi index fb864a139c97..03fccd48f0c0 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -44,6 +44,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi index 05c9216a87ee..94c0a8cf4953 100644 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -44,6 +44,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index afba5f04c8ec..2ee9ba1ecdc1 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -87,12 +87,14 @@ cpu5: cpu@500 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3>; }; l3: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; From patchwork Mon Oct 31 09:21:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13167 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2203563wru; Mon, 31 Oct 2022 02:23:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5McKzcM2i9b912sQy/2gKtABIn1lS1pGwUcpI7+LhIHj3+CjbEXGz3qA6SPiY2GitD/Gib X-Received: by 2002:a05:6402:1f06:b0:457:149d:beaa with SMTP id b6-20020a0564021f0600b00457149dbeaamr12467507edb.238.1667208182349; Mon, 31 Oct 2022 02:23:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208182; cv=none; d=google.com; s=arc-20160816; b=WQwV4j9MLHjRKZgjeC3hQAf+uL/T8jx8DvOkVv3dBNGWtrFFiEJH+ozSaAaQBSMm1J km5Tpo26H83OtRkgJajW72WxBstXJUt9tMKDXEHIN+n/E5q8jD2sasAo988HVrdhoSjL Ol7O+2ApEoByy1RxHYN8M1ada6BVzVtHEC7BXOlhF56VBmcRSVsI2WSBJYmyeyNaYo0/ JvUAFml2JquLhHR9OsvNlpHMrVf4Mf2RmDEoNCBQtaWgPvNdgO9sGzxGoXD/EpdndUL9 XdyW726jCvpqPVQG27+lD9+H/WXiTX8m7P+2yPnF3roVVRsL0Pe5UzcAFUtffEktS066 u+gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=APnQROVmMg7nUvegNjNzVXK0rFFlBLN1oJTtHtRo6uE=; b=hli+/k2ojxAso3jSbyxJj1iZ8V5l0R9PRAnFRBbPmW24OoitCZG53dwQ10M6OyXMGi AA2fjoDUQI0gzr+wyExOOmO76+COCJ978jOSIsaPszBpnL1kr6zZefKhA9zHtIGsAhBT ACnIIFndNDLUSIn+iBmuycEDJzH0GljDyp4SaTsPqf7i+XlU4qghUJv/ZSHZWXtQhKwU s2uVLMtmV5rG3s5+MDWozl6HtoeRuJ+SXrI54xZ7/g3JhKR9O0btN4guq157eqDFkdme AuRian1+Vt7KaYBXYkmhxMQbgiEQOmAizpAe0Z+rkGnlXBYc5ui1h49mIjMuaqn+BG8B 8KLQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q18-20020a056402033200b00461cb980126si6209945edw.309.2022.10.31.02.22.38; Mon, 31 Oct 2022 02:23:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230364AbiJaJVo (ORCPT + 99 others); Mon, 31 Oct 2022 05:21:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230363AbiJaJV0 (ORCPT ); Mon, 31 Oct 2022 05:21:26 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C4A07DF9A; Mon, 31 Oct 2022 02:21:04 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDD1D113E; Mon, 31 Oct 2022 02:21:10 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 698A23F703; Mon, 31 Oct 2022 02:21:02 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 17/20] arm64: dts: Update cache properties for renesas Date: Mon, 31 Oct 2022 10:21:02 +0100 Message-Id: <20221031092102.533429-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194487272780514?= X-GMAIL-MSGID: =?utf-8?q?1748194487272780514?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 40201a16d653..748cf9dbca24 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -88,6 +88,7 @@ L3_CA55: cache-controller-0 { compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 3652e511160f..adcd62d33b3e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 { compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4d6b9d7684c9..7287d0590fad 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -109,6 +109,7 @@ L3_CA55: cache-controller-0 { compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; From patchwork Mon Oct 31 09:21:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13169 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2204047wru; Mon, 31 Oct 2022 02:24:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7CVU5eGWITgHn9Vv5XnSW8klfO6+hAHGiZjjItr8kcYyVOEdXg8uAFPBCsaAXdPqtRm1s8 X-Received: by 2002:a17:907:984:b0:77f:4d95:9e2f with SMTP id bf4-20020a170907098400b0077f4d959e2fmr12014225ejc.176.1667208254289; Mon, 31 Oct 2022 02:24:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208254; cv=none; d=google.com; s=arc-20160816; b=waSriqsHvlemMZBkIo8II3az42Rl8V4NvF+xPvJzW5vVjZlBs+f7yupCAI5q7BpMp8 LjY/OgQzrwYo1e4B4kLtd+Z+MfsrW55Grlzl/Yx4Rl0E5xo80N+9gyhFKS4Z1/L9FyzK 3tdXJtBXUYw5no4+Vg/RNN3D5/wmpnjCiA/4wfdqU8LF0EuM56ILXRkIsc0k5yoPleGA Miz27QnAceN4rb3xduUOMDdRrKJqTVucn9RyiyAOsTZc8oGpd1eHlyjtggD379+ao58B AKR0CFV1Ab0ZEZKe0EvpEg0eWpd7pCQH/ygqm9BKqf/Bpfafw5hGj+gDng4GDHZSZ4NB jowQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=k9j48o9DqM4MI8zQWyUyqnRG3krJXF7xnDT9n2Ha+Sc=; b=mskeMgBY/5ELBy+mNpQy7IdRMcifap+nzluyTXYC1z6wCw/tiC7/SzQscRrnuLqsFq GSKyTzm9L3h01nhySbBYvUmPbDxWrXNCvSHQLkAGoYhT5AoMVwCLHydodGOukY5M+Ol1 xndGlNmtJGvo/zXCcrB4YfShHyTPeF+x9xfIbds9Fln1/MyjCHoJgweoiBve220qZL79 1envQufkWZfbq0PrOONLF3ku3AweeGW23KUGUgWbOdUxtE3b5FHi/052lp4b1egXpE7U pytlP+422Btpg1THpoexORK1ByXnsk/Hq1Qa5WLDEZ+D/USQX72uksKw8O9ld/oUeiWh 1Glg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d7-20020a50ea87000000b0045cd7614e59si6892905edo.451.2022.10.31.02.23.50; Mon, 31 Oct 2022 02:24:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbiJaJWE (ORCPT + 99 others); Mon, 31 Oct 2022 05:22:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230382AbiJaJVj (ORCPT ); Mon, 31 Oct 2022 05:21:39 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5D5DEDFB4; Mon, 31 Oct 2022 02:21:11 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68FBE113E; Mon, 31 Oct 2022 02:21:17 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 28D193F703; Mon, 31 Oct 2022 02:21:07 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Johan Jonker , Christopher Obbard , Ezequiel Garcia , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 18/20] arm64: dts: Update cache properties for rockchip Date: Mon, 31 Oct 2022 10:21:08 +0100 Message-Id: <20221031092109.533495-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194562298687447?= X-GMAIL-MSGID: =?utf-8?q?1748194562298687447?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 2dfa67f1cd67..dd228a256a32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -96,6 +96,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 49ae15708a0b..8741914cea44 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -102,6 +102,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; From patchwork Mon Oct 31 09:21:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13170 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2204169wru; Mon, 31 Oct 2022 02:24:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6s/HeJa792c92yC+FkBhjl0CdCIzNDRv3XULVLbjTy12OQQf+2ZBS2Xs+vmCr1a7I2rAGs X-Received: by 2002:aa7:dc06:0:b0:461:b683:5fba with SMTP id b6-20020aa7dc06000000b00461b6835fbamr12545903edu.72.1667208270334; Mon, 31 Oct 2022 02:24:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208270; cv=none; d=google.com; s=arc-20160816; b=CqMjhQ/oDO65x8fWdjJJMsJypBXRNScir5NTpReJ1YSFjQas2itFzejD3U2klpoE5L S7LlHzZXSj9OexrgII/X8/sB8985alSLYfzFC0P4DahMpL1CFXzF9OHAzaQ8uMNzo47j b0mK+a5l2rEgkqzlUCIbQNWdaTz69d5/Gd9XpK1wCsV2Cb0z61QgnQdUB9EfR0g9OCE4 2jP/ddG+NDYpgar06mza4lYnDYNCzya5VvRkhIr746Qam8wXJnWZdTBkVE77j0SzV2ko 90RVWJ1sRKZGVg1kbA6/8vug4nz9S0/Kn86tJxZSFWEX1WBIHSTDQZjDELe7MLE9FBId 5BCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=uxkIqszN4Pq2mdLdWEcVynLflVricnVPAB8ReDVzPY0=; b=RWm/Vh+bpHJs89lU7Y6kw181kEnRFgzSaChpUVPnpNezJk8VCcu9JH4tB65EQQowyU L4gkF9MnkuA9XAuD9H4Ri9eXtnwe5iE+kczAcqI/N+MiSVV2A0FURZ61aBl0VApzFskt tyBFFvdldbISZuy7t99GvUySvXN6IuPdIsCw4ZHi15w73TsKl9ou7422kJiJa2pN6NL/ gjc4F7Nn4lL9PkVV/jEH5eOhEOLdRWYy054ST6PezD5FqfIlj+NluKMjJGT3SJvngEvX wY6WaZh7DY7XClM/EbWLJIPLdDVxblzXM9AHOM6tVaRz9srtei4itf6NOcBPSG+9QwRR ZzKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sg41-20020a170907a42900b0077f4fcfe49csi8156214ejc.905.2022.10.31.02.24.07; Mon, 31 Oct 2022 02:24:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbiJaJWS (ORCPT + 99 others); Mon, 31 Oct 2022 05:22:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230391AbiJaJV6 (ORCPT ); Mon, 31 Oct 2022 05:21:58 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1D22BE032; Mon, 31 Oct 2022 02:21:15 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09CE311FB; Mon, 31 Oct 2022 02:21:22 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9112E3F703; Mon, 31 Oct 2022 02:21:13 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Jisheng Zhang , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 19/20] arm64: dts: Update cache properties for synaptics Date: Mon, 31 Oct 2022 10:21:14 +0100 Message-Id: <20221031092115.533560-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194578990057292?= X-GMAIL-MSGID: =?utf-8?q?1748194578990057292?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Jisheng Zhang --- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 0949acee4728..926da7e1a6ba 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,7 @@ cpu3: cpu@3 { l2: cache { compatible = "cache"; + cache-level = <2>; }; idle-states { From patchwork Mon Oct 31 09:21:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 13171 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2204385wru; Mon, 31 Oct 2022 02:24:53 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5pKEReFxd28kWh8S2juIy41pX/Eo8Xl1i8jrjBEBhUWD1zyJHk80qqOlaHXD9n0573lEl4 X-Received: by 2002:a17:906:9414:b0:7ad:bde1:3ccf with SMTP id q20-20020a170906941400b007adbde13ccfmr8009424ejx.543.1667208293784; Mon, 31 Oct 2022 02:24:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667208293; cv=none; d=google.com; s=arc-20160816; b=djjgWJgectojV+kOTJJV34waclNP0Lbk4yIAwQ0h2LAmZqrfKwDNwivVxY+ttkdT31 MxVzGOM67pGXB9tIf206ns9nrTe24TEcz3Q+aygm0hOFHvjSY21HOetBHprKtDmTs7oa eZDzidHgj2naQG2j5ivqx2L9IFfaJaovleuFebXZnAzYwK3L4IuSEpfXzPTTpK4TkhEE rfFKD3YfnblFxAGhwGN1KyVQeBWP3PuMfKHzQF/5XihjgTyY4uWKVryT2HNPGTgkaoeP mL1LVa/o3GUWIvzwSBeNMCTlJkxaUg+8y6O5cDygswR/zNrhsiLMNf/JWS+LqWZoCRtv Nbow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=0+KnmDTlF/3uFj1G+1xTXCP3B9LQglgNo3gvnh6QWMI=; b=hPdExjIkoBvWA3gss3qvg6L52tJbd2Wq/e16TdgQU4RWMd4Gv2NvRItdNP3P5v0shR kxa/2iWCcd4UwhQOu/MWrOfFhbdBvKbOYKb5Wzm6L2AKOYfJUx58mOvz6XTKWNTAyAqR KMxYUX3XAfhut3WCxKy+oVh36gAui4BpTJR71K1sxsfLfeIaX3EMgKxMC+63ePvKlhmX WHKIdM6Eg+X+CDByoIFP0QrRR3gKJ3rVuOofBFo76kX7TEHcvLwURORpGGH1mOVX4wI7 Ng0jdwTrF7DbqZcs14J9sEkvLv9leNS+44YtBKMmnkTt65cagsHwKGPfWtUoz8RTZ7zP Ry9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sc21-20020a1709078a1500b00770880dff50si8093485ejc.586.2022.10.31.02.24.30; Mon, 31 Oct 2022 02:24:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230388AbiJaJWe (ORCPT + 99 others); Mon, 31 Oct 2022 05:22:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbiJaJWO (ORCPT ); Mon, 31 Oct 2022 05:22:14 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 24926DF4E; Mon, 31 Oct 2022 02:21:27 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 30B51113E; Mon, 31 Oct 2022 02:21:33 -0700 (PDT) Received: from pierre123.arm.com (unknown [10.57.7.107]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9F9333F703; Mon, 31 Oct 2022 02:21:24 -0700 (PDT) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: pierre.gondois@arm.com, Rob.Herring@arm.com, Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Aswani Reddy , Shashank Prashar , Sriranjani P , devicetree@vger.kernel.org Subject: [PATCH 20/20] arm64: dts: Update cache properties for tesla Date: Mon, 31 Oct 2022 10:21:19 +0100 Message-Id: <20221031092125.533621-1-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748194603585814746?= X-GMAIL-MSGID: =?utf-8?q?1748194603585814746?= The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..bfab040fc1e4 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -284,6 +284,7 @@ cpucl_l2: l2-cache0 { cache-size = <0x400000>; cache-line-size = <64>; cache-sets = <4096>; + cache-level = <2>; }; idle-states {