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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u195-20020a6379cc000000b00557888b4eb9si4989200pgc.622.2023.07.13.05.17.17; Thu, 13 Jul 2023 05:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=s6EZEkJ7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234120AbjGMMMh (ORCPT + 99 others); Thu, 13 Jul 2023 08:12:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230027AbjGMMMf (ORCPT ); Thu, 13 Jul 2023 08:12:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A87E1FEA; Thu, 13 Jul 2023 05:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250354; x=1720786354; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9j52FthJZNa9Xc0YEIj+5Oie+v4CQc4EqZA27meU8go=; b=s6EZEkJ7Jmyh+stjmzUm/Kk2gKHpCKz23rtEh6QEe4OLcF/b5xLAUjNH 5J7ObTBstkD2c/n7qLI7KLZtHXH4v2kmNtk5E+u4tiJJ9JywyDXZ98KZr iwRLP1j13AgthxNm9uDElZeCPIBIBRWl/5PmRgRoTbQ+i6f2OBtEqhlXH AXQIOMWNiXZo4nDvBs7kL+55gXRJih7E8l7konqjuVqaohOPgX9Je5CCO 2AYUK4/X80Z13Ye59rTyu1JnAQqDMoxyv69KANf6lphueNqS7ch9zz3wA eZtwNubkpnYef5iu+y3i4zI9KWbZNH0GvNTCsmHGiWFn5izYGyp7llyAv Q==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="222827123" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:33 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:32 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:30 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , , Palmer Dabbelt Subject: [PATCH v5 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Date: Thu, 13 Jul 2023 13:10:59 +0100 Message-ID: <20230713-endless-spearhead-62a5a4b149bd@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2940; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=9vL9UTnWKFum0JN16SUa6SYVYB7LNXsYDcHCgjUs78g=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX15Z31TaJ2s3lzevTmmnneHM8n8OFz29fLJ2NilFflF6 0dTfUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIk0JjMyTJq7/uiLtIVfulw33u7gdz Y+9vaU1blLHYKHuE7xSXvnTmb4X/TmkU8MT8yU/W7nJs9b/fe2mNCBZYz5vOtP82QxR3kJsAIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771307689953931754 X-GMAIL-MSGID: 1771307689953931754 From: Palmer Dabbelt Right now we provide a somewhat unhelpful error message on systems with invalid error messages, something along the lines of CPU with hartid=0 is not available ------------[ cut here ]------------ kernel BUG at arch/riscv/kernel/smpboot.c:174! Kernel BUG [#1] Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 6.4.0-rc1-00096-ge0097d2c62d5-dirty #1 Hardware name: Microchip PolarFire-SoC Icicle Kit (DT) epc : of_parse_and_init_cpus+0x16c/0x16e ra : of_parse_and_init_cpus+0x9a/0x16e epc : ffffffff80c04e0a ra : ffffffff80c04d38 sp : ffffffff81603e20 gp : ffffffff8182d658 tp : ffffffff81613f80 t0 : 000000000000006e t1 : 0000000000000064 t2 : 0000000000000000 s0 : ffffffff81603e80 s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000 a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 a5 : 0000000000001fff a6 : 0000000000001fff a7 : ffffffff816148b0 s2 : 0000000000000001 s3 : ffffffff81492a4c s4 : ffffffff81a4b090 s5 : ffffffff81506030 s6 : 0000000000000040 s7 : 0000000000000000 s8 : 00000000bfb6f046 s9 : 0000000000000001 s10: 0000000000000000 s11: 00000000bf389700 t3 : 0000000000000000 t4 : 0000000000000000 t5 : ffffffff824dd188 t6 : ffffffff824dd187 status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 [] of_parse_and_init_cpus+0x16c/0x16e [] setup_smp+0x1e/0x26 [] setup_arch+0x6e/0xb2 [] start_kernel+0x72/0x400 Code: 80e7 4a00 a603 0009 b795 1097 ffe5 80e7 92c0 9002 (9002) 715d ---[ end trace 0000000000000000 ]--- Kernel panic - not syncing: Fatal exception in interrupt Add a warning for the cases where the ISA string isn't valid. It's still above the BUG_ON cut, but hopefully it's at least a bit easier for users. Signed-off-by: Palmer Dabbelt Reviewed-by: Evan Green Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..3af2d214ce21 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -66,11 +66,15 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) { + pr_warn("CPU with hartid=%lu does not support rv32ima", *hart); return -ENODEV; + } - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) { + pr_warn("CPU with hartid=%lu does not support rv64ima", *hart); return -ENODEV; + } return 0; } From patchwork Thu Jul 13 12:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119825 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1780472vqm; Thu, 13 Jul 2023 05:16:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlHIhLybHE/SgpUnhBzzD6nRfzvK2reG1208Wj+b7CsQmrTndzeniIcKMBEPoTgsRMzzNhWM X-Received: by 2002:a05:6a20:3d8b:b0:133:6fe0:6525 with SMTP id s11-20020a056a203d8b00b001336fe06525mr723376pzi.34.1689250612683; Thu, 13 Jul 2023 05:16:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689250612; cv=none; d=google.com; s=arc-20160816; b=DWqD6OdLiXrEg/1WiVgEBF/7wsM1fljXev/wKn+IyxzQhKuqU5Gv+C7yDBiNh18iuh VXY4cqV/wvidKas8Q3hdwDNCL4qXR0Ja+OvgwI6ltuprZbQKwtkaZhDPod5wXn3OpTNs fqtBx8aRd+uR56/8yqNG/qW9F74Z3u8FaxGmaQjZiP/H0FVK2OKAxKZlVBx1pp4XmwUg 1/xMMlpyCr4RXByKQHUSnGRBUgVUWrEgPpUGUFWEA/n3gc5cLSjDPd2DOgzAmkbem1B8 CNv7EakXZPv9LqyVHLZet0hc4/tP/Ua4nc6QJCGzL4rLaIxnShuKqcHC706MngmxrVGQ FtGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=i4BvSXkPJxBG2My9nNlMr+UL5vwTSFvfKXDWWGvTiZQ=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=QLv9c5ou22VUpyPdrYg3FV5sVeAohp4iNRJnu3N1UZDE2l/Or0MYIVonJOVnp89fPm q6/K4c4CaXp9O0j/uDqfBoSDnkenW8yn2Mk0cDZUiIobE2aMR1RshGdAA3ZJTuovgk20 fOHzq4p85bLTq2cC7fw38cqk6LeAc9EVg13eHxFvbOfS5KvXQTi6K8MBehiL269UYh7T omc8JeuZhTu5Sckt1ABBoMFxKEYjO0TT3X5VRNaXAVmTFNMa6HO/c6guw2OdqYZ/anRL vZUWUo5fRQuKRvJYtETKJ5Zrt8u0lfbCFdoa1t2CivJWgPxYAsjuxizL18Dg7YvOy7ny FfRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="04jp033/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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So when recreating the runtime isa-string we can also just go the other way to get the correct starting point for it. Signed-off-by: Heiko Stuebner Reviewed-by: Andrew Jones Reviewed-by: Evan Green Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley --- Changes in v3: - Fix tabbing of print_mmu() Changes in v2: - Delete the whole else & pull print_mmu() above it, since that's common code now --- arch/riscv/kernel/cpu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3af2d214ce21..f808b67f5a27 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f) */ static const char base_riscv_exts[13] = "imafdqcbkjpvh"; -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { int i; seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); + if (IS_ENABLED(CONFIG_32BIT)) + seq_write(f, "rv32", 4); + else + seq_write(f, "rv64", 4); + for (i = 0; i < sizeof(base_riscv_exts); i++) { if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) /* Print only enabled the base ISA extensions */ @@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v) unsigned long cpu_id = (unsigned long)v - 1; struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); struct device_node *node; - const char *compat, *isa; + const char *compat; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); + print_isa(m); + print_mmu(m); if (acpi_disabled) { node = of_get_cpu_node(cpu_id, NULL); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) seq_printf(m, "uarch\t\t: %s\n", compat); of_node_put(node); - } else { - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) - print_isa(m, isa); - - print_mmu(m); } seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); From patchwork Thu Jul 13 12:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119831 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1789734vqm; Thu, 13 Jul 2023 05:32:43 -0700 (PDT) X-Google-Smtp-Source: APBJJlHkdbwqi4nBeuJZ9Q448OCXqogCxXVlB42nK6uHeG6WdKk5tnluZ16L/zdb3ZrsDI0PHEJT X-Received: by 2002:a17:906:df54:b0:971:eb29:a082 with SMTP id if20-20020a170906df5400b00971eb29a082mr1088081ejc.49.1689251563610; Thu, 13 Jul 2023 05:32:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689251563; cv=none; d=google.com; s=arc-20160816; b=OLNLDQN/xA8sFb8O/um0FQq+suYQhBXLSI8/r5BUd0+X8xgK+TZBhnGycqn8ae+RMW iTwHA2Feg+s0RlyxkG1qKVNZTVp1ZuHm5NepJavCivxjyHA9IpA2AFMUQ4IcZt5fk1WU Z6Q2wpp2h6DcKcklQSUkDoLhCb/47UCpQ9FjQS4fMQg8bzfPA5kwWfdAsj0mjL3zU4Ox pDTqckbem/n146gs3tVVJT19dGAJRWyzeQUIqLJ/ZdNUBftU5lSX3bOb+brWg4KWutK5 uS6unrbvTJBrwwURKV8CYg2XwXNE3pSYDQBGoq4b4+qLMGIoScpEeROo0VGmVqNG15df Vzmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vC1BnLacuWIn4JP44zo+QlFO9OWCrIZRrezYlKwlTx8=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=fVTtflSkBEWja3KajMSn4CUbfjyV+a8FNjWkXpULY9i638lPOVCPVGRMMoQHdctSBa LmmHz0NKd6DuVpf+ZqkEOEuo7xcWQNJtHvJ6ERyum3VvU4yhkVoCiU03Mn3dBpN1aanT 9Xp36hra2Fdt3c1zWcAJXZ8beXNJszS6O3C0ux5oZt9NsVvu7w99qmrqiUEVHu0oCHcf pd42AigMf8n5Xld0SzFeljlTsnaUFzNkoLTW28nimP4165ulWSpCsUXGPusF+h7arHpK X8Aa7Bnzcf/z29YHphKY+N0s2DRq1QHihIlHyUJPhPwX/e9nAp598qEqzn6mCwE8axSB hBBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=tJRpUm64; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id xo6-20020a170907bb8600b009889ae99c40si6972054ejc.611.2023.07.13.05.32.18; Thu, 13 Jul 2023 05:32:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=tJRpUm64; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234553AbjGMMMr (ORCPT + 99 others); Thu, 13 Jul 2023 08:12:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234544AbjGMMMk (ORCPT ); Thu, 13 Jul 2023 08:12:40 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A3E926B8; Thu, 13 Jul 2023 05:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250359; x=1720786359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1i34KSawlUL8WNjNkmTiVglWiYjIqUpNKEWr7RWMan4=; b=tJRpUm644RjT8ajQUgOA7tn35xOLCi3JHWrUQ7fsOecP9bu4S8Xc3jw+ NaX/hcsUNPHsrpBoJ9ngjD0IpweeHEtO5pErFidMU69bMXWVXPzdFMo1i 7LP0xxHCBmEXO0PD7wZcczpertKfJ9jH7edJsT4dP0n7zpCWFIVvnu1qm rtPVKFt/bcajtS2n6DGbWnPt4StyWIh/HQepgvr2DR7yv/nLb9cC0rmQs QjyIBP6BHYMD3cLGbxI4FQ+jMyBGGohFld1dMNF+SWHFcz6qwRYyr5Blz fxyrkm1x0X8f92FNyoVdHwN01mLFRjNOO5+Hx4BT8DkYiSGi2/kBeiEiL A==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="222827139" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:36 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 03/11] RISC-V: drop a needless check in print_isa_ext() Date: Thu, 13 Jul 2023 13:11:01 +0100 Message-ID: <20230713-veggie-mug-3d3bf6787ae2@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1275; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=1i34KSawlUL8WNjNkmTiVglWiYjIqUpNKEWr7RWMan4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX15dnT3zoNehbztPtS703Cn0evqXSf3LJDnnbIvR88xU NBKN7ihlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEYk8yMmy41VY7X+Pdp5ctjsmT7j aHfhK+t10mrNpt/vK/GazS9wIY/tm2HFI/t7Zy87PdG0V3eT1fuvLXR8643YfK3/C5tm6fcIYHAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771308647667718502 X-GMAIL-MSGID: 1771308647667718502 isa_ext_arr cannot be empty, as some of the extensions within it are always built into the kernel. When this code was first added, back in commit a9b202606c69 ("RISC-V: Improve /proc/cpuinfo output for ISA extensions"), the array was empty and needed a dummy item & thus there could be no extensions present. When the first multi-letter ones did get added, it was Sscofpmf - which didn't have a Kconfig symbol to disable it. Remove this check, as it has been redundant since Sscofpmf was added. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Reword commit message to explain why this can be dropped --- arch/riscv/kernel/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index f808b67f5a27..e721f15fdf17 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -237,10 +237,6 @@ static void print_isa_ext(struct seq_file *f) arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - /* No extension support available */ - if (arr_sz <= 0) - return; - for (i = 0; i <= arr_sz; i++) { edata = &isa_ext_arr[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) From patchwork Thu Jul 13 12:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119829 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1784167vqm; Thu, 13 Jul 2023 05:23:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlHeoWYIvpnoQaKe/VKs1ziy/KNcoYuWC+G4nY8xWGx206sgqfMmxjaQQiBtvh4HJwziBMy9 X-Received: by 2002:a05:6a00:2390:b0:673:6cb4:7b0c with SMTP id f16-20020a056a00239000b006736cb47b0cmr2492937pfc.2.1689250987525; Thu, 13 Jul 2023 05:23:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689250987; cv=none; d=google.com; s=arc-20160816; b=II5c3o1Lys2mEwxsWE/9MQ/gGERoqQNC1yNDeE7UEF7gz6wcmzcjpSKBCiGS8R+omY Og4+6OwvdwllUR1IY6N4gdk3ziNA1t3ni9H6l+F8+t1GNqoDnFWFYfq8R1DyfUBn1vUh LXdTjyjPr3oBHdQxLQ8Kf9pthiR/pRDqvB/J3fsl1EfxoYBDG1YNL37EAdNxUHoUF0/v M4I+i8wSTnTAA9HHATsu+x/wtQGGTAlLYtiIlrwukW1YHlcyKWGW84MdhYfFcW9SXeBq p26cObsXW5o+50fvPk7VJ7yEGrlZ4M84UZHnlqG3y3EoykvfwjBEPsfIgac8aDYpFPtG Hdfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AzJ8prs2VMctMk6H8W9us1aijZD6DE52Pn0Fb2GHjo8=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=glAnW9sauF9YCtzruGvChuW0gIBjnXCLpesDkejWSyJD4o4x+C7zp6ubN2s7kmOvbN 1z47SRz2n3hsFigGpgewIFk2EzoHLawlKTtpE1Hv6Jkdciy9EeKtOqlBIzxJE0n6YGAM R69V+H77gsAkzmGo/6/8+lt2CXh8x4S3B+ptx5/z1U3Wm3heiHXCjO+q0RLwfmH86wHU sUoGB4qDwdMY3iJhJK4NgL1Vb5WwuF8zsHi4msIBbgusl1jprwjrDxUr5rYJjSoXL8fn FOe/4IrE+0F6w8rTCaa9HihA9viDXWJbCwUoD7iTNisQDfPk1rVw/foC/Q5/g/72l+Kg JUIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=rr7JWoYi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h191-20020a6383c8000000b0055acc7f805bsi152024pge.334.2023.07.13.05.22.54; Thu, 13 Jul 2023 05:23:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=rr7JWoYi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231280AbjGMMNv (ORCPT + 99 others); Thu, 13 Jul 2023 08:13:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234648AbjGMMNh (ORCPT ); Thu, 13 Jul 2023 08:13:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB8392D4B; Thu, 13 Jul 2023 05:13:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250390; x=1720786390; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bOnzuYCARzPhwIulmb5IXa1ikc7VrTQNP62An2jC5Lg=; b=rr7JWoYiUkNiTm6TOgsrgmIBueTtQ/WaECfNfjjuy+sj71NxyEOhKLZL pzKKz1LXi4bG8iW9kR9StSF/4QI43Y2P8+ygUjzVdQLudMlXk1jBlTykp 9xsAYII+JtJ0FqhOzWPPO/+ZxqCj6AJQeIeBe3iMIU/gY2S3WdAbQ1BRY rvCQFaH6d0QIQa5r8eV/Vhxns6/JmPRXJA4t84UnzpusGXToUCQupLxSB lPl+eYpa6Q6tyUeBmcH7ihAFlkp2zX2gOA2UfMWnrGQCAJ+pS5e2lipqw KPumgq7nx5BzysnecS+slv0YBm/vzqpKZkEDk3LkrQhpsSEUHR3RUlxLS Q==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="220194617" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:13:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:41 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:39 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Date: Thu, 13 Jul 2023 13:11:02 +0100 Message-ID: <20230713-spirits-upside-a2c61c65fd5a@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8778; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=bOnzuYCARzPhwIulmb5IXa1ikc7VrTQNP62An2jC5Lg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX17d33KgoebT291Tbn+PSpx3T9Dih+aSJ2lyUjeKPPwV 0xdO6yhlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBExM8y/DN+rPMh2ffHw4QPqkz+St nnPmSu++vG8S/sVa9FiLxl50uG/yk5aeJ87Wt2vhPtav/WEedXveb0rZM7W1JNjCqT/6sw8wIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771308043051587434 X-GMAIL-MSGID: 1771308043051587434 To facilitate using one struct to define extensions, rather than having several, shunt isa_ext_arr to cpufeature.c, where it will be used for probing extension presence also. As that scope of the array as widened, prefix it with riscv & drop the type from the variable name. Since the new array is const, print_isa() needs a wee bit of cleanup to avoid complaints about losing the const qualifier. Reviewed-by: Andrew Jones Reviewed-by: Evan Green Signed-off-by: Conor Dooley --- Changes in v2: - Drop the empty element from the end of the array, it was adding a bug anyway as I was not decrementing the result of ARRAY_SIZE() by one. Likely I meant to drop it originally and forgot, as dropping the decrement was intentional. --- arch/riscv/include/asm/hwcap.h | 3 ++ arch/riscv/kernel/cpu.c | 75 +--------------------------------- arch/riscv/kernel/cpufeature.c | 67 ++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 73 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..7a57e6109aef 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,9 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; +extern const struct riscv_isa_ext_data riscv_isa_ext[]; +extern const size_t riscv_isa_ext_count; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index e721f15fdf17..bf93293d51f3 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,81 +164,10 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted after - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be listed - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be listed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed, they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described above. - */ -static struct riscv_isa_ext_data isa_ext_arr[] = { - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), - __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), - __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; - int i = 0, arr_sz; - - arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - - for (i = 0; i <= arr_sz; i++) { - edata = &isa_ext_arr[i]; + for (int i = 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) continue; seq_printf(f, "_%s", edata->uprop); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..fb476153fffc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,6 +99,73 @@ static bool riscv_isa_extension_check(int id) return true; } +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + * + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. + */ +const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), +}; + +const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); + void __init riscv_fill_hwcap(void) { struct device_node *node; From patchwork Thu Jul 13 12:11:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119827 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1781142vqm; Thu, 13 Jul 2023 05:17:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlHK/h2XSLG4KC5c9HhDs7NvA6lhkSlPfUHO281QjxKgOTRWMrCN+KtCro1SfIxIovMx0O2T X-Received: by 2002:a17:902:f54f:b0:1bb:3a7:6b12 with SMTP id h15-20020a170902f54f00b001bb03a76b12mr870484plf.17.1689250675549; Thu, 13 Jul 2023 05:17:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689250675; cv=none; d=google.com; s=arc-20160816; b=VmJs9q+nQPts5IDgRsnCq7XCSkpyOGb2pwNONcy0vUqHRutm/7b93SeCW5lfGxHZce KN+QKvv7ZiPN1ZbGkGLX8k7Z0pB0R8wGg2vUTCEM3PxxYS+r/VGjch1pmtE2rIYqxSql QLrzZoYqb4KGJ6ZCjbe8QNrcAy6SqlY6kAmjV3mIe6+b/l+tMNyk9KC3CZZ1/gUeyw5G AYM9inUcMSNHQICHPo2NDFFqjkIs0G2S7eY3PLWjPWBqSvXjHdpc9aSTML5RMahUEo9S mHo56i9kUc6Eu7BzAbaOFzGjUn8SKbRwi367qWBwfg3Yw3I4SOBXIzT6cyh/tQQklOb0 Pq5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MvzUb/XCmcdseaIzjOSubaRT5nw7N/+PLIvUECVvYYY=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=Zy33/8WmmDerm/IvCj3OLI2sC/It1qPnxylqQfx3FHB6oV64EswPupVwfcadxIpdbu q88l9U36wBqr1IRdeDeJfjkkASP+cr3L6FZfN/zklPv4lH1tvKXEB5Ay51uhUENziTOy uEnH90O9fdhD+gzclTyS1jlB4of+gHF07w707kWaIC3UUmjTMJsXqSQw6OFrWAf2huPS wkoZcvgv/jlVd8TwRr3LJKNLqN/jykmwJHktkXmS+sz2eFnZOa1Nd5Pwg0fYQo4KTXlW Tz7V5NRI4k7oJ603eYOlQnnBKI/kSVO3ve1hE0celGw6K28CFJP75xYUfZIIcF8EcM+r ejZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2HhA8J9K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mm21-20020a17090b359500b00263d0beafafsi11931227pjb.181.2023.07.13.05.17.43; Thu, 13 Jul 2023 05:17:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2HhA8J9K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234164AbjGMMNa (ORCPT + 99 others); Thu, 13 Jul 2023 08:13:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233846AbjGMMNR (ORCPT ); Thu, 13 Jul 2023 08:13:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 201E0272B; Thu, 13 Jul 2023 05:12:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250376; x=1720786376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1RiFXp6VosblDMvQmJ9JkmMZVqvj4S+xVV3jhRMbmdU=; b=2HhA8J9KgeyvcTbAK2NbYBgoz77rGWYAFuJNmJ52NrJ4kuPDhqjuufUr oJu9Yi+By5oEfb91JJFRLikF8f8Pr1toKfiU1OvguNanvAqlU0JX+QZeO viBL/Up7RpTLqXlQPcWVMaaRUqYRyphDs5hD8j6uAg7G57GJy6bmu18mU wgFW4HAfZfBVz+itpOdl/jQTXG2t6LfeynCzjFjKomrc5sbtESThu2AGF dWK2iRDE+DcdK+OcsfxlxK0zD4xMdaWxdWDhcuUMwsJWJxyI1C/NkWok3 e/yVkASr6Mdr8pgT+ds1jpVSySW6Be7LSrih+Mngx8RGivXs+gDRA8+qs Q==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="220194590" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:41 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Date: Thu, 13 Jul 2023 13:11:03 +0100 Message-ID: <20230713-dastardly-affiliate-4cf819dccde2@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4231; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=1RiFXp6VosblDMvQmJ9JkmMZVqvj4S+xVV3jhRMbmdU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX15TteXZvCs/fMr3ZVNemCf53e52N/EsyeUKOvZVwzHm /VaFjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzktRcjw5zed9uXTF43vcNLfdnr3T szPi2dzNrBJrFX6WG6inedURPDH46Wvf/1RdNb5e84prka5XbvtN32UsmKVYz1tfne3qvnmQE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771307716378640032 X-GMAIL-MSGID: 1771307716378640032 In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather than duplicating the list of extensions with individual SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious comments from the struct, rename uprop to something more suitable for its new use & constify the members. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v5: - Swap sizeof() - 1 for strlen() as pointed out by Evan Changes in v2: - Delete the now unused definition --- arch/riscv/include/asm/hwcap.h | 7 ++----- arch/riscv/kernel/cpu.c | 5 +++-- arch/riscv/kernel/cpufeature.c | 30 +++++++++--------------------- 3 files changed, 14 insertions(+), 28 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7a57e6109aef..2460ac2fc7ed 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -55,7 +55,6 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA @@ -70,10 +69,8 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; + const unsigned int id; + const char *name; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index bf93293d51f3..aa17eeb0ec9a 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -168,9 +168,10 @@ static void print_isa_ext(struct seq_file *f) { for (int i = 0; i < riscv_isa_ext_count; i++) { const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + if (!__riscv_isa_extension_available(NULL, edata->id)) continue; - seq_printf(f, "_%s", edata->uprop); + + seq_printf(f, "_%s", edata->name); } } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fb476153fffc..859e3831fac1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id) return true; } -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } +#define __RISCV_ISA_EXT_DATA(_name, _id) { \ + .name = #_name, \ + .id = _id, \ +} /* * The canonical order of ISA extension names in the ISA string is defined in @@ -350,8 +349,8 @@ void __init riscv_fill_hwcap(void) #define SET_ISA_EXT_MAP(name, bit) \ do { \ - if ((ext_end - ext == sizeof(name) - 1) && \ - !strncasecmp(ext, name, sizeof(name) - 1) && \ + if ((ext_end - ext == strlen(name)) && \ + !strncasecmp(ext, name, strlen(name)) && \ riscv_isa_extension_check(bit)) \ set_bit(bit, isainfo->isa); \ } while (false) \ @@ -366,20 +365,9 @@ void __init riscv_fill_hwcap(void) set_bit(nr, isainfo->isa); } } else { - /* sorted alphabetically */ - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); } #undef SET_ISA_EXT_MAP } From patchwork Thu Jul 13 12:11:04 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n27-20020a635c5b000000b0054033bf35f4si4810955pgm.773.2023.07.13.05.45.23; Thu, 13 Jul 2023 05:45:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=WGeBSf+F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234610AbjGMMNO (ORCPT + 99 others); Thu, 13 Jul 2023 08:13:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234555AbjGMMNH (ORCPT ); Thu, 13 Jul 2023 08:13:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0356F2D52; Thu, 13 Jul 2023 05:12:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250370; x=1720786370; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f+gmfGrxcQqjXfZd/zTckfTRTww6zd62gI4c22r/Xm8=; b=WGeBSf+FFc7Yc6Gn2urT3dvm+Vm+GHxyDTBoVku7VfgO2gDwCVFVGWfH sGTOGFAzU8lT4qNq9+Xu6WqY/cIdcm4sma8KLBnyPa/aqJjFRoTSbRBjh 1Kfz6ijoDAfNAZfydUaQQfb/5OtMQVZBwdMQ7IrPRu56o4fZomIfNE/8H IQqaw3+zk9gnAkD+PkAhGOa/1nOCHzlx0ChCLN0D835KWHHgxLWpx0CGL sBRT6BMXw6Et3w4jQZ/GkALuPwG1d0Ts4wnFQ+kj448X16Cp5MkSinA/I aya9SRLuUCb+DVi7FfO2NgK8FmEQjbby2rF6/uQZ6bPQ13BzZN7skKT5m g==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="235310992" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:12:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:44 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 06/11] RISC-V: add missing single letter extension definitions Date: Thu, 13 Jul 2023 13:11:04 +0100 Message-ID: <20230713-train-feisty-93de38250f98@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1249; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=f+gmfGrxcQqjXfZd/zTckfTRTww6zd62gI4c22r/Xm8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX17bI3rjyOnwwzrWLC0GMSG3z2w8vanr5aRqx39+l64K hSXbdZSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiu6cwMmxLVZkYrfh/+u+YuieTj9 5e0/hzo9mWmzunui3xb2wzudPE8N+La9K6q9sSFBe5ZZYdCv9u+8taTf6wjd9VgwnJ534xCHADAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771309457561033575 X-GMAIL-MSGID: 1771309457561033575 To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Reviewed-by: Andrew Jones Reviewed-by: Evan Green Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2460ac2fc7ed..a20e4ade1b53 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a') From patchwork Thu Jul 13 12:11:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119842 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1797213vqm; Thu, 13 Jul 2023 05:46:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlESMRdTp6ysKkYO55EFh3Mywtch9Uu9LU6YSwVugk/rsO+xKaUjAn51CbFM/1o4WGWcJkEr X-Received: by 2002:a05:6a00:198f:b0:675:b734:d302 with SMTP id d15-20020a056a00198f00b00675b734d302mr1149368pfl.1.1689252364966; Thu, 13 Jul 2023 05:46:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689252364; cv=none; d=google.com; s=arc-20160816; b=bU9bphKQ6/BWyI12oVDpeIdxZ105CwYHwmo6XKm8zfptHxzaKIDyQaOvGZgKUbVAyA IumqbMx/zvAPbAsLmDfMvEMbSUvzLA05rXy9cwlhM69Un9QJG6ot0sIT1+Tu3n7OMKTp HAIOuQ1cElRl6ccsHmudGTMrTieQSSjfttJ/5V+gJgfBAph/zjD/a8EJHELCkjcxkQei 07G1Oxnmg7ZKuGhLc1ehSyom1QcCpC4dItBfBazMcnWi53wR6WELNVckwpTGaQfW2+Cr /o1+lkTjZOn7F7jLtMWx6VqDyiUSm7zE9PL4zMpf/obZKoan/JzDesybCFodsXJx+02J NELQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HBMp8+IyL80A1hD3qniJeqVZuVMi9feiINUkZYowFtE=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=xgJ5q1Zs/JMYcuVqjy3GRScTSJsShva/4nKAiCdBSSHDm/11zt7B+r/P9Q7dx7rnS2 5OPCtcAKw/rigXMFXBOWK5dO5fTdjvB8n0J/PaKN3WJsljo3jL7sgBqO/HcTh5Tl9WDm BLuPGrhHMPfMf+/ShRGSQrCM2cWoIgMZ9r9m4/xzyXdpebesgwSzb5Cs58bWV3MZ2wX7 kABbtzDH0nA5Wb31dbjyP3VZcOAJbiHdxd+iISWmHzQY2B8cBvrutE9dF91o/WZnV/lQ O2vR2VtxF8Tbve19GvSIk1HfbUgPPFIiwUdFheVNMG8Wfobe20I7FKQ0iCkvYGjrJJVF GG0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cDLuPN4k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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As a result, what gets spat out in /proc/cpuinfo will become borked, as single letter extensions will be printed as part of the base extensions and while printing from riscv_isa_arr. Take the opportunity to unify the printing of the isa string, using the new member of riscv_isa_ext_data in the process. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop the multi_letter member, in exchange for calling strnlen() in two places. --- arch/riscv/kernel/cpu.c | 37 ++++++++++------------------------ arch/riscv/kernel/cpufeature.c | 13 ++++++++++++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index aa17eeb0ec9a..4f1f12f34b63 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,41 +164,26 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -static void print_isa_ext(struct seq_file *f) -{ - for (int i = 0; i < riscv_isa_ext_count; i++) { - const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->id)) - continue; - - seq_printf(f, "_%s", edata->name); - } -} - -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - static void print_isa(struct seq_file *f) { - int i; - seq_puts(f, "isa\t\t: "); + if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); else seq_write(f, "rv64", 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + continue; + + /* Only multi-letter extensions are split by underscores */ + if (strnlen(riscv_isa_ext[i].name, 2) != 1) + seq_puts(f, "_"); + + seq_printf(f, "%s", riscv_isa_ext[i].name); } - print_isa_ext(f); + seq_puts(f, "\n"); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 859e3831fac1..d6009bd4c186 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -144,6 +144,19 @@ static bool riscv_isa_extension_check(int id) * New entries to this struct should follow the ordering rules described above. */ const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), + __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), + __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), + __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), + __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b), + __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k), + __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j), + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), From patchwork Thu Jul 13 12:11:06 2023 Content-Type: text/plain; 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Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop unused variables --- arch/riscv/kernel/cpufeature.c | 345 +++++++++++++++++---------------- 1 file changed, 177 insertions(+), 168 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d6009bd4c186..7c661b12ac8d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -178,29 +178,172 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); -void __init riscv_fill_hwcap(void) +static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo, + unsigned long *isa2hwcap, const char *isa) +{ + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ + isa += 4; + + while (*isa) { + const char *ext = isa++; + const char *ext_end = isa; + bool ext_long = false, ext_err = false; + + switch (*ext) { + case 's': + /* + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] != '_' && ext[1] == 'u') { + ++isa; + ext_err = true; + break; + } + fallthrough; + case 'S': + case 'x': + case 'X': + case 'z': + case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ + ext_long = true; + for (; *isa && *isa != '_'; ++isa) + if (unlikely(!isalnum(*isa))) + ext_err = true; + + ext_end = isa; + if (unlikely(ext_err)) + break; + + if (!isdigit(ext_end[-1])) + break; + + while (isdigit(*--ext_end)) + ; + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { + ++ext_end; + break; + } + + while (isdigit(*--ext_end)) + ; + + ++ext_end; + break; + default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ + if (unlikely(!isalpha(*ext))) { + ext_err = true; + break; + } + + if (!isdigit(*isa)) + break; + + while (isdigit(*++isa)) + ; + + if (tolower(*isa) != 'p') + break; + + if (!isdigit(*++isa)) { + --isa; + break; + } + + while (isdigit(*++isa)) + ; + + break; + } + + /* + * The parser expects that at the start of an iteration isa points to the + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". + */ + if (*isa == '_') + ++isa; + +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext == strlen(name)) && \ + !strncasecmp(ext, name, strlen(name)) && \ + riscv_isa_extension_check(bit)) \ + set_bit(bit, isainfo->isa); \ + } while (false) \ + + if (unlikely(ext_err)) + continue; + if (!ext_long) { + int nr = tolower(*ext) - 'a'; + + if (riscv_isa_extension_check(nr)) { + *this_hwcap |= isa2hwcap[nr]; + set_bit(nr, isainfo->isa); + } + } else { + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); + } +#undef SET_ISA_EXT_MAP + } +} + +static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) { struct device_node *node; const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; - unsigned long isa2hwcap[26] = {0}; + int rc; struct acpi_table_header *rhct; acpi_status status; unsigned int cpu; - isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; - isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - - elf_hwcap = 0; - - bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - if (!acpi_disabled) { status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); if (ACPI_FAILURE(status)) @@ -232,158 +375,7 @@ void __init riscv_fill_hwcap(void) } } - /* - * For all possible cpus, we have already validated in - * the boot process that they at least contain "rv" and - * whichever of "32"/"64" this kernel supports, and so this - * section can be skipped. - */ - isa += 4; - - while (*isa) { - const char *ext = isa++; - const char *ext_end = isa; - bool ext_long = false, ext_err = false; - - switch (*ext) { - case 's': - /* - * Workaround for invalid single-letter 's' & 'u'(QEMU). - * No need to set the bit in riscv_isa as 's' & 'u' are - * not valid ISA extensions. It works until multi-letter - * extension starting with "Su" appears. - */ - if (ext[-1] != '_' && ext[1] == 'u') { - ++isa; - ext_err = true; - break; - } - fallthrough; - case 'S': - case 'x': - case 'X': - case 'z': - case 'Z': - /* - * Before attempting to parse the extension itself, we find its end. - * As multi-letter extensions must be split from other multi-letter - * extensions with an "_", the end of a multi-letter extension will - * either be the null character or the "_" at the start of the next - * multi-letter extension. - * - * Next, as the extensions version is currently ignored, we - * eliminate that portion. This is done by parsing backwards from - * the end of the extension, removing any numbers. This may be a - * major or minor number however, so the process is repeated if a - * minor number was found. - * - * ext_end is intended to represent the first character *after* the - * name portion of an extension, but will be decremented to the last - * character itself while eliminating the extensions version number. - * A simple re-increment solves this problem. - */ - ext_long = true; - for (; *isa && *isa != '_'; ++isa) - if (unlikely(!isalnum(*isa))) - ext_err = true; - - ext_end = isa; - if (unlikely(ext_err)) - break; - - if (!isdigit(ext_end[-1])) - break; - - while (isdigit(*--ext_end)) - ; - - if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { - ++ext_end; - break; - } - - while (isdigit(*--ext_end)) - ; - - ++ext_end; - break; - default: - /* - * Things are a little easier for single-letter extensions, as they - * are parsed forwards. - * - * After checking that our starting position is valid, we need to - * ensure that, when isa was incremented at the start of the loop, - * that it arrived at the start of the next extension. - * - * If we are already on a non-digit, there is nothing to do. Either - * we have a multi-letter extension's _, or the start of an - * extension. - * - * Otherwise we have found the current extension's major version - * number. Parse past it, and a subsequent p/minor version number - * if present. The `p` extension must not appear immediately after - * a number, so there is no fear of missing it. - * - */ - if (unlikely(!isalpha(*ext))) { - ext_err = true; - break; - } - - if (!isdigit(*isa)) - break; - - while (isdigit(*++isa)) - ; - - if (tolower(*isa) != 'p') - break; - - if (!isdigit(*++isa)) { - --isa; - break; - } - - while (isdigit(*++isa)) - ; - - break; - } - - /* - * The parser expects that at the start of an iteration isa points to the - * first character of the next extension. As we stop parsing an extension - * on meeting a non-alphanumeric character, an extra increment is needed - * where the succeeding extension is a multi-letter prefixed with an "_". - */ - if (*isa == '_') - ++isa; - -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext == strlen(name)) && \ - !strncasecmp(ext, name, strlen(name)) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - - if (unlikely(ext_err)) - continue; - if (!ext_long) { - int nr = tolower(*ext) - 'a'; - - if (riscv_isa_extension_check(nr)) { - this_hwcap |= isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); - } -#undef SET_ISA_EXT_MAP - } + riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa); /* * Linux requires the following extensions, so we may as well @@ -420,6 +412,23 @@ void __init riscv_fill_hwcap(void) if (!acpi_disabled && rhct) acpi_put_table((struct acpi_table_header *)rhct); +} + +void __init riscv_fill_hwcap(void) +{ + char print_str[NUM_ALPHA_EXTS + 1]; + int i, j; + unsigned long isa2hwcap[26] = {0}; + + isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; + isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; + isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; + isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; + isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; + isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; + + riscv_fill_hwcap_from_isa_string(isa2hwcap); /* We don't support systems with F but without D, so mask those out * here. */ From patchwork Thu Jul 13 12:11:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119833 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1790099vqm; Thu, 13 Jul 2023 05:33:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlGxOEMxin58iCOSmAbgONH8s+f0yNOYwc/vVasZRJY0yZs6UYe0Yj3iopahMFpt8UgWEoPv X-Received: by 2002:a17:906:151:b0:993:fb68:ed6c with SMTP id 17-20020a170906015100b00993fb68ed6cmr2313559ejh.15.1689251600980; Thu, 13 Jul 2023 05:33:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689251600; cv=none; d=google.com; s=arc-20160816; b=nO9up+IQgS2XUzzwco7E1Hb/p9Fta5n6EF8R94kCjuV2+dD1K6U9+7c3zl5tct01P+ wmhrpiWWsN5T/5HGe5CmjqEmkg97JbUQWoukWVAkKqZz0Igcr8MbieirXIvMo77yTQtM uBE/3iocV5/4dpRwIw66gIIbkdyCbQxbqeCuG3wc/XYiNTFg60lCO9U9hLlytz8dbWqM sftE6rl1ui1cLTfEzVUnYealzG/z/a7isJkY45n29F5nUPjUpU1o3roG/Q7q/cKaUfPb IUXP5LgXov2s8uOoz3Hk/IOp4X5GHxKahfj0rKHz56490buvWppgHCmUW/ddvG+5kol1 rXoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RKcLk2fEulrC7zladssw1rHVjrSjOTHjqNoqO8iBA+Q=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=FjYNi+FxhQ7bDIRIfObgxROHB9P5IXVTyvosUqyCPz9ftYCcIRY1KasIBYqddjyF/5 w4769e8wSeZPLsEQgQ/XlhXAhjkTfd0XADkpXOFc6G/U36JjDg+fYRP1nlO8kiv67BRC /1XcwTusHFWFvysaR5a5k2OH5MGvEz9NtWBWH/UjXI+t0Ni/HzfVBu6oHeN9GeQ5+0eC 6YnwJgpufxj/UR5xEoVWdhefSe1s3kmf56pd/X7AYqNpjGWA3i0TobnY8VF+ZHkAMG6o hFxaVPOSGd4ON0NtFDkIfogzTARJV2d3gBc0uzlLgunwR/fJss/aBF/SDrjoqewFbPEE K1fQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=u2WqJ21d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kq21-20020a170906abd500b00984713011c1si7251648ejb.306.2023.07.13.05.32.56; Thu, 13 Jul 2023 05:33:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=u2WqJ21d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234691AbjGMMNx (ORCPT + 99 others); Thu, 13 Jul 2023 08:13:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234028AbjGMMNk (ORCPT ); Thu, 13 Jul 2023 08:13:40 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69D2630D1; Thu, 13 Jul 2023 05:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250393; x=1720786393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SuAv8Leh99onWd/6PJcaTcunFy7r2dXNiII1c8HHGOI=; b=u2WqJ21dG2I4qhGSQymH2rD5vEcwtO/xdKhDX8imetwqUPFAQb42by0y P+Jzki3jpTvCKpd62PttIhbvdqPL0RAQRnltFo5Sa4H9d4nHXHMT6k0tW BLYlN27m2HZDyEnQTyVQYR8N50JdT68QYvrY1C62CLPpb62xqlKJkz4ug +oWLS6NIDWwVaHCr2DXBGLMvpRl3Nk3S5PqvLvchB3CppurIbJSEJ0dJn zcRIieb0ZCRDcrj0d7km8ntUzncqtR+SQ9QDnTvgGe6Fw/NBgPNKHBd5Z m6QHcQmME3MKbb1fz7l+Rwlp+cR+TUaDnq29KsjrX2ccdywfR/MSGwG6f w==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="220194629" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:13:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:12:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:53 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v5 09/11] RISC-V: enable extension detection from dedicated properties Date: Thu, 13 Jul 2023 13:11:07 +0100 Message-ID: <20230713-vocation-profane-39a74b3c2649@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4797; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=SuAv8Leh99onWd/6PJcaTcunFy7r2dXNiII1c8HHGOI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX153FL9etPLdvZjQTYkiZ9X3npRO+ZUSUWxyI58/2utz 9KzWjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExklTojw2SbOdOC/Q3q1VoypHwX7a 6LWZI2u33aqdKNlSLaumKrrRgZfp1YdeRsBrv7cnvJ6yUWD9NX57g3v7WtlXZsZS+9mviIHQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771308686928998719 X-GMAIL-MSGID: 1771308686928998719 Add support for parsing the new riscv,isa-extensions property in riscv_fill_hwcap(), by means of a new "property" member of the riscv_isa_ext_data struct. For now, this shadows the name of the extension for all users, however this may not be the case for all extensions, based on how the dt-binding is written. For the sake of backwards compatibility, fall back to the old scheme if the new properties are not detected. For now, just inform, rather than warn, when that happens. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v5: - Add a missing put of the cpu node where the property is not found - Reword the commit message, s/new/dedicated/ - Remove a this_isa bitmap & replace it with isainfo->isa, to match what is done for the isa string codepath Changes in v2: - Pick a more suitable function name than fill_hwcap_new() - Actually use the property member to read from the DT --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 78 ++++++++++++++++++++++++++++++++-- 2 files changed, 75 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a20e4ade1b53..e3cda14a486b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,7 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { const unsigned int id; const char *name; + const char *property; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7c661b12ac8d..fdc71e52dc2b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_DATA(_name, _id) { \ .name = #_name, \ + .property = #_name, \ .id = _id, \ } @@ -414,11 +415,69 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) acpi_put_table((struct acpi_table_header *)rhct); } +static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) { + unsigned long this_hwcap = 0; + struct device_node *cpu_node; + struct riscv_isainfo *isainfo = &hart_isa[cpu]; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + if (!of_property_present(cpu_node, "riscv,isa-extensions")) { + of_node_put(cpu_node); + continue; + } + + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + riscv_isa_ext[i].property) < 0) + continue; + + if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) + continue; + + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) == 1) + this_hwcap |= isa2hwcap[riscv_isa_ext[i].id]; + + set_bit(riscv_isa_ext[i].id, isainfo->isa); + } + + of_node_put(cpu_node); + + /* + * All "okay" harts should have same isa. Set HWCAP based on + * common capabilities of every "okay" hart, in case they don't. + */ + if (elf_hwcap) + elf_hwcap &= this_hwcap; + else + elf_hwcap = this_hwcap; + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); + else + bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); + } + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + return -ENOENT; + + return 0; +} + void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; unsigned long isa2hwcap[26] = {0}; + int i, j; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -428,10 +487,21 @@ void __init riscv_fill_hwcap(void) isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - riscv_fill_hwcap_from_isa_string(isa2hwcap); + if (!acpi_disabled) { + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } else { + int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); - /* We don't support systems with F but without D, so mask those out - * here. */ + if (ret) { + pr_info("Falling back to deprecated \"riscv,isa\"\n"); + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } + } + + /* + * We don't support systems with F but without D, so mask those out + * here. + */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { pr_info("This kernel does not support systems with F but not D\n"); elf_hwcap &= ~COMPAT_HWCAP_ISA_F; From patchwork Thu Jul 13 12:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119835 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1793153vqm; Thu, 13 Jul 2023 05:38:43 -0700 (PDT) X-Google-Smtp-Source: APBJJlFD+HkV6uSd/00gyWVzUqB1xG7w/5uPlFd1hTs/roFS2RCJ5HgWIVk9rIutKrKWqAvOhM4U X-Received: by 2002:a19:9147:0:b0:4f8:8be4:8a82 with SMTP id y7-20020a199147000000b004f88be48a82mr1051282lfj.22.1689251923129; Thu, 13 Jul 2023 05:38:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689251923; cv=none; d=google.com; s=arc-20160816; b=z8U3liNCokeTAtG3W+3JUff+KJGWQUkAg6jM1tczriMglkThsuiGD08QQLNyqjcEGJ JtPb+7fH2noRb1Wa037SebklqUnEUGrP4GwSzWBaClCdljNEBlXL/xNaaIIzWF5TUSUi VH2oX1Rof22GFF/5axHzRYp9CxrJxIuAbw45gubhLl0Z1mNuCnTvSPcM0rY/OqorTSgc FP83iYtaI5c4hx4ckWsyw7JbA8uqcnhtvTukMmGUDQ0m+vsh+gadjn20d7e9Ov14D95L yKPkAR/4aJlEuYlRDvV1+++c2YIToHnl7qRb5wTpRjvK9dkTTuhY7juCaAZk72ZGWokf 7VRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7mRMEMCtqtAeUOhcKcRhtWdUcJLYolxHwb3sQJY5g/Y=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=UMeSIt8iWlSRIIgDIeLIQT0mNA3T0lXDSC+fMBDaz2Ysi9bWubKd26x25clra/nhtH g5NSniOG8uiZz1zAZHh0eNW3HghhSBllYt0H2ps6/Z6KHZybW6R+f/jmt2t7BRZvUK3X PwyWysduZM53H2T5pOHNxk4/K1moIMORWJyIvJJ6/GPuJqMiQ1W4shjoDtiPUEz1dFNp RG38J85xjsLyLhPAhfBwSYATLvxDDnfVwQbZjVefP5UutKJahsKHKuTL/IlTV2nzS7iH +ghG1Md8AwSVpK0qxZLSVDg/ata5IIy+HiKZYIkSOte8HfrsKwPSc9q+FCl8KWefiPL+ 2iMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=HfgstqKe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v3: - Add some printouts to explain what went wrong while parsing harts, so that if none are found there's at least a hint before we hit a BUG() --- arch/riscv/kernel/cpu.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 4f1f12f34b63..28d5af21f544 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -61,8 +61,35 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) { + pr_warn("CPU with hartid=%lu does not support rv32i", *hart); + return -ENODEV; + } + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) { + pr_warn("CPU with hartid=%lu does not support rv64i", *hart); + return -ENODEV; + } + + if (!of_property_present(node, "riscv,isa-extensions")) + return -ENODEV; + + if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { + pr_warn("CPU with hartid=%lu does not support ima", *hart); + return -ENODEV; + } + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; } From patchwork Thu Jul 13 12:11:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 119832 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1790091vqm; Thu, 13 Jul 2023 05:33:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlHqycQ6nscpixY3HJ+NnqIanEE+3mFD4TGj+fbFrYBvf70zgQNxzu4NcoYUIHFyruEPOSs4 X-Received: by 2002:a17:906:739a:b0:993:f081:2c5d with SMTP id f26-20020a170906739a00b00993f0812c5dmr2457524ejl.0.1689251600467; Thu, 13 Jul 2023 05:33:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689251600; cv=none; d=google.com; s=arc-20160816; b=gHBuGGPO2UDgewaIhurh+W4heOa0v0uyqYeyZk36TmAbSdbfjNz3o/BhCotUIMC5fc YGyn2vhbX846+cLgOdo2roU4LaAcyk127WAbUoXeqHe9Lri4g3AsSLvX8JbCrrmpsPW+ tOrdDUSyQWTApWH58V6pIhtQ6vvSBL/lEPPj1+H0BCnSqYNtR1CADnK9vYp6K9olEZ44 8y+wsCOMO4oBdkwGlGvC9vFPK+NzhwoVGQ0O3AaOBz2OvKvLYMTQNc+PVDsc20F2AvRz SionAp9Hk9heAZ5ZRsrL+Ptt7Qe0tUQ/IvrXPfX4NxSgEJvMTdh6ZopCunQ6hFG1pC5W v5ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gOgRBzj9BnT1hAmuhygIzKsQ9qyHDJCdFkTAa/tNYAc=; fh=NmedlpijBMacxlBO1NzbUohgLks7RaHl1/2Vvbaff2U=; b=b4PBsbfQIEztcy3wmcn53vZEQWJasVdrmmrehasLxcFZ2hfMsWq7cWE3ZzWraRA7Lz +Cb1MJlGPlqeLrTMeps7OI1MU+rb0+2kQ/7404K4wCSm2u1Gh/npwiXeb85CANFplTt9 cQJrqOj2tReJyFoudD9JdvF75sZQQlaZDbXrboPnrYzZAXfClDGLBw9AcjpUJLyoKA/T U7DaPZOPM3mQiFhIj/EQFdDDgdDijil81eQZ6x9Hq/yzpMDDpqDIv7aO2UwRBCeci+xQ bmK2KSh7st1qKyBKm3QSNRWOEDZeUnQfoPSWBhNlgHLuhcIMqmah83u8OCIebGp/JHAd OP9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=wCSgLbYV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j25-20020a170906095900b0098eb8b70f32si6866471ejd.213.2023.07.13.05.32.55; Thu, 13 Jul 2023 05:33:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=wCSgLbYV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234727AbjGMMOE (ORCPT + 99 others); Thu, 13 Jul 2023 08:14:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234666AbjGMMNr (ORCPT ); Thu, 13 Jul 2023 08:13:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A20C2D6D; Thu, 13 Jul 2023 05:13:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689250398; x=1720786398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ao2V3XKzPyOMhVIBq5e6EqE2FH88Dgn3v9ob0DWGpxw=; b=wCSgLbYVDQhniFQEDHfYL5cStT5IggHKWyDawes0KDwJDKfCElevMbes ufPGHajyOrrtvC94CQ09K6C/isgxBwLtXpcZW08fTY6ZtPGqO6wsz4l4I 4g0CB1NuWpiX7UG77p1zzf+No+FNYiom5urW09adb5T2Ydx/tLrRvIutG SAlAbG1Tew8DIbTctpNqEer4CbxJRPAWOjnoLxSck7i78mDdYs6raR9aG Lk661bpqZ9cDLaqRH0lTuKrdTZJpm/e75A1XpTTvtq2nAQa7qYnJLdh9x a6w9OWSrpVgYDDZ0lH3s/EpE/9CaVSz1a8M73wQugYGg0MZFwu0rSWNMG Q==; X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="220194646" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jul 2023 05:13:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 13 Jul 2023 05:13:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 13 Jul 2023 05:12:59 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , , Palmer Dabbelt Subject: [PATCH v5 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Date: Thu, 13 Jul 2023 13:11:09 +0100 Message-ID: <20230713-aviator-plausibly-a35662485c2c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713-target-much-8ac624e90df8@wendy> References: <20230713-target-much-8ac624e90df8@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5841; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Ao2V3XKzPyOMhVIBq5e6EqE2FH88Dgn3v9ob0DWGpxw=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnrX95I9v60+YCl/c5LJ3cqRWZvnjRp565oX06n/HV3lx+c ofDKq6OUhUGMg0FWTJEl8XZfi9T6Py47nHvewsxhZQIZwsDFKQATMexgZNgqPTXXwvqLudMPSY2f8V /b76280eY6dS/jD7am1S1P7WQZGZof1Ub+Pbw85ulcA+vHq+btfvHtIMc3/sxHlo/ZvUzrZ/ICAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771308686538412653 X-GMAIL-MSGID: 1771308686538412653 As it says on the tin, provide Kconfig option to control parsing the "riscv,isa" devicetree property. If either option is used, the kernel will fall back to parsing "riscv,isa", where "riscv,isa-base" and "riscv,isa-extensions" are not present. The Kconfig options are set up so that the default kernel configuration will enable the fallback path, without needing the commandline option. Suggested-by: Andrew Jones Suggested-by: Palmer Dabbelt Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v4: - add __init to fixup k210 build issue - use Drew's revised wording Changes in v3: - Invert the Kconfig entry. It's now default y & not hidden by NONPORTABLE, but its entablement will now activate the fallback - Add a commandline option to enable the fallback on kernels that do not enable it in Kconfig, as Drew suggested - Default the global var to the Kconfig option & override it with the commandline one, rather than have checks for IS_ENABLED() and for the commandline option in riscv_fill_hwcap() & riscv_early_of_processor_hartid() --- .../admin-guide/kernel-parameters.txt | 7 +++++++ arch/riscv/Kconfig | 18 ++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 8 +++++++- arch/riscv/kernel/cpufeature.c | 14 +++++++++++++- 5 files changed, 46 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index a1457995fd41..bdc3fa712e92 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5468,6 +5468,13 @@ [KNL] Disable ring 3 MONITOR/MWAIT feature on supported CPUs. + riscv_isa_fallback [RISCV] + When CONFIG_RISCV_ISA_FALLBACK is not enabled, permit + falling back to detecting extension support by parsing + "riscv,isa" property on devicetree systems when the + replacement properties are not found. See the Kconfig + entry for RISCV_ISA_FALLBACK. + ro [KNL] Mount root device read-only on boot rodata= [KNL] diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4c07b9189c86..f52dd125ac5e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -848,6 +848,24 @@ config XIP_PHYS_ADDR be linked for and stored to. This address is dependent on your own flash usage. +config RISCV_ISA_FALLBACK + bool "Permit falling back to parsing riscv,isa for extension support by default" + default y + help + Parsing the "riscv,isa" devicetree property has been deprecated and + replaced by a list of explicitly defined strings. For compatibility + with existing platforms, the kernel will fall back to parsing the + "riscv,isa" property if the replacements are not found. + + Selecting N here will result in a kernel that does not use the + fallback, unless the commandline "riscv_isa_fallback" parameter is + present. + + Please see the dt-binding, located at + Documentation/devicetree/bindings/riscv/extensions.yaml for details + on the replacement properties, "riscv,isa-base" and + "riscv,isa-extensions". + endmenu # "Boot options" config BUILTIN_DTB diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e3cda14a486b..b7b58258f6c7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ struct riscv_isa_ext_data { extern const struct riscv_isa_ext_data riscv_isa_ext[]; extern const size_t riscv_isa_ext_count; +extern bool riscv_isa_fallback; unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 28d5af21f544..208f1a700121 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -41,7 +41,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) return 0; } -int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) +int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; @@ -87,6 +87,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return 0; old_interface: + if (!riscv_isa_fallback) { + pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", + *hart); + return -ENODEV; + } + if (of_property_read_string(node, "riscv,isa", &isa)) { pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", *hart); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fdc71e52dc2b..71fb840ee246 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -473,6 +473,18 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) return 0; } +#ifdef CONFIG_RISCV_ISA_FALLBACK +bool __initdata riscv_isa_fallback = true; +#else +bool __initdata riscv_isa_fallback; +static int __init riscv_isa_fallback_setup(char *__unused) +{ + riscv_isa_fallback = true; + return 1; +} +early_param("riscv_isa_fallback", riscv_isa_fallback_setup); +#endif + void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; @@ -492,7 +504,7 @@ void __init riscv_fill_hwcap(void) } else { int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); - if (ret) { + if (ret && riscv_isa_fallback) { pr_info("Falling back to deprecated \"riscv,isa\"\n"); riscv_fill_hwcap_from_isa_string(isa2hwcap); }