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[8.43.85.97]) by mx.google.com with ESMTPS id la26-20020a170907781a00b0077ed84da316si4974042ejc.217.2022.10.30.18.41.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 18:41:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4D0E63858422 for ; Mon, 31 Oct 2022 01:41:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id DDB453858C2F for ; Mon, 31 Oct 2022 01:40:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DDB453858C2F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1667180426t9h74ixh Received: from server1.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 31 Oct 2022 09:40:24 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: L22wY/dvqrC5nIkCljHHHmP+GP4Gxx3LjGTFvqllTREe5E/CxzV3hssNdGd79 uZJKICtQP0T330gJzoBP8rZczJLzFuc3GhACNjTAarHsnLQ0wy6YeCOX7AGdCwboJ1LOdyr yJ1Dwh+4KBvl0BIlyv6aRhNfYjFBvRd1f0ePTKHia5HN3KZ8pnTqX+ZJmDrzzb2C0mj7LW9 cHVTdDL2MR+CV7euP/NkAR+7DYiybdkbggvQWHUL/wZCZFLVCATdmdLwFis5+EE8OLBEWNj owujtGOyHb0VSIQFFjO5LKoe2DkGUlWQR2EqXl+HdN1EnfZs8lXcnpEH5eLtsjDUfvQxtL4 mQVyj825pFFNGM/TNHQxJWGH6uMGTj/eP4iqZn8 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix RVV testcases. Date: Mon, 31 Oct 2022 09:40:22 +0800 Message-Id: <20221031014022.250112-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: schwab@linux-m68k.org, kito.cheng@gmail.com, Ju-Zhe Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748165436300642704?= X-GMAIL-MSGID: =?utf-8?q?1748165436300642704?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32. * gcc.target/riscv/rvv/base/abi-3.c: Ditto. * gcc.target/riscv/rvv/base/abi-4.c: Ditto. * gcc.target/riscv/rvv/base/abi-5.c: Ditto. * gcc.target/riscv/rvv/base/abi-6.c: Ditto. * gcc.target/riscv/rvv/base/abi-7.c: Ditto. * gcc.target/riscv/rvv/base/mov-1.c: Ditto. * gcc.target/riscv/rvv/base/mov-10.c: Ditto. * gcc.target/riscv/rvv/base/mov-11.c: Ditto. * gcc.target/riscv/rvv/base/mov-12.c: Ditto. * gcc.target/riscv/rvv/base/mov-13.c: Ditto. * gcc.target/riscv/rvv/base/mov-2.c: Ditto. * gcc.target/riscv/rvv/base/mov-3.c: Ditto. * gcc.target/riscv/rvv/base/mov-4.c: Ditto. * gcc.target/riscv/rvv/base/mov-5.c: Ditto. * gcc.target/riscv/rvv/base/mov-6.c: Ditto. * gcc.target/riscv/rvv/base/mov-7.c: Ditto. * gcc.target/riscv/rvv/base/mov-8.c: Ditto. * gcc.target/riscv/rvv/base/mov-9.c: Ditto. * gcc.target/riscv/rvv/base/pragma-1.c: Ditto. * gcc.target/riscv/rvv/base/user-1.c: Ditto. * gcc.target/riscv/rvv/base/user-2.c: Ditto. * gcc.target/riscv/rvv/base/user-3.c: Ditto. * gcc.target/riscv/rvv/base/user-4.c: Ditto. * gcc.target/riscv/rvv/base/user-5.c: Ditto. * gcc.target/riscv/rvv/base/user-6.c: Ditto. * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 2 +- 27 files changed, 30 insertions(+), 30 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c index 92e61c255ac..9cd94c99308 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */ void foo1 () {__rvv_bool32_t t;} /* { dg-error {unknown type name '__rvv_bool32_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c index b9adb3072f6..628a2753202 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} void foo1 () {__rvv_bool32_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c index 56a0ebed477..b4557aa6939 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} void foo1 () {__rvv_bool32_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c index af716094491..a58167f29ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} void foo1 () {__rvv_bool32_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c index e866c067e05..05b56e1cd28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */ void foo1 () {__rvv_bool32_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c index 407756de183..cc35ba1c6cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */ void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */ void foo1 () {__rvv_bool32_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c index 6a235e308f9..15e9c71f662 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c index 10aa8297c30..e864554def6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c index f8da5bb6b93..df5a36d0d68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c index 5b8ce40b62d..43a196a3e73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c index 8c630f3bedb..23591aa8f7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c index b9bdd515747..90e67652056 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c index a7a89db2735..dc3ca1f55cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c index e8cfb4b10b4..2d3744de66f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c index 5ca232ba867..13cc6699d6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c index 41fc73bb099..23b9da126de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c index d4636e0adfb..e87de71c677 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c index 9447b05899d..1ea447b07bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c index 6d39e3c0f4d..7ed10bc5833 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include @@ -7,12 +7,12 @@ /* Test tieable of RVV types with same LMUL. */ /* ** mov1: +** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1 ** vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au] +** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2 ** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) ** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) -** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1 ** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) -** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),2 ** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) ** ret */ @@ -28,10 +28,10 @@ void mov1 (int8_t *in, int8_t *out, int M) /* ** mov2: +** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1 ** vsetvli\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au] ** vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) ** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) -** addi\t(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),1 ** vse8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c index 3d81b179235..b271b0a1f3c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc -mabi=ilp32" } */ #pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' extension enabled} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c index 00fb73f220f..63eea3fe901 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c index 92f4ee02d20..59ffe1062de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c index 3a425721863..86105e80d3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c index 76c5e607137..c854e3f8d92 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c index de850e5e10d..f2b24733e57 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c index 1d79b6b8eac..2c2c1ca3636 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */ +/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c index 661f2c9170e..87698f306bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ #include #include