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Thu, 13 Jul 2023 11:20:24 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36DBKJ51011992; Thu, 13 Jul 2023 11:20:19 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3rq0vm0p8u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 13 Jul 2023 11:20:19 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36DBKJEb011969; Thu, 13 Jul 2023 11:20:19 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36DBKIFg011966; Thu, 13 Jul 2023 11:20:19 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 6F3C147C7; Thu, 13 Jul 2023 16:50:18 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH v8 1/3] dt-bindings: PCI: qcom: ep: Add interconnects path Date: Thu, 13 Jul 2023 16:50:11 +0530 Message-Id: <1689247213-13569-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com> References: <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UByQcKmYHZC2P1v21HJjIyAkGNCiF8I8 X-Proofpoint-ORIG-GUID: UByQcKmYHZC2P1v21HJjIyAkGNCiF8I8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-13_04,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 mlxlogscore=999 phishscore=0 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307130099 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771305567740730118 X-GMAIL-MSGID: 1771305567740730118 Some platforms may not boot if a device driver doesn't initialize the interconnect path. Mostly it is handled by the bootloader but we have starting to see cases where bootloader simply ignores them. Add the "pcie-mem" interconnect path as a required property to the bindings. Signed-off-by: Krishna chaitanya chundru Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 8111122..bc32e13 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -71,6 +71,13 @@ properties: description: GPIO used as WAKE# output signal maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + items: + - const: pcie-mem + resets: maxItems: 1 @@ -98,6 +105,8 @@ required: - interrupts - interrupt-names - reset-gpios + - interconnects + - interconnect-names - resets - reset-names - power-domains @@ -167,7 +176,9 @@ examples: - | #include #include + #include #include + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, @@ -194,6 +205,8 @@ examples: interrupts = , ; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "pcie-mem"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; From patchwork Thu Jul 13 11:20:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 119784 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1754149vqm; Thu, 13 Jul 2023 04:29:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlG54E4ZOPdwhDeVWgLh7lj1O8eahZ5VVZbAjYlBQDZs9Xp3PE6LnMMHoSoYFMNvosVYCxbO X-Received: by 2002:a17:906:715:b0:992:a618:c3c2 with SMTP id y21-20020a170906071500b00992a618c3c2mr1304316ejb.76.1689247749018; Thu, 13 Jul 2023 04:29:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689247749; cv=none; d=google.com; s=arc-20160816; b=JhszBaOQBMOGqgj9mSrtUPd0FNLr7ifNpeeiQfcQzsHSBnlu5ySbMjgpzQltmUFA0p B+dGjGROZ4FJX4XeOauqP/4AZseHGGy7mQRdmPLUnoBWOt0h3UgyfT6YIuXppY067HSc ofwpme5/uSaW+YLRiwWeog/jsr9TeAqsx/wWyVHBzTyjg39/nCpfzjY6Akfk0HWVapMp Cxzecz1QpZTao735fg1cw1NGLLLQszlxMlsAvLik3CkrrunAofFciy5hiATpbkWYaV8C cRDm/H0CjkNlr0rt6DPRIas3vlHa+moj3OkeBGtnFLGTWOu8BW5ZJcVMD50r5z1F+9Nx TLWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=THevGgIaAz40LxJ7PoX5+QlN0ue7D25a3gYMNyvw4/8=; fh=PA5QN8KvJWBPXXO+zbqZHCT6mCzOzdrcr0HhI4/KCYw=; b=GgrZ6hlmNvViwYAv3Hj5skj0KNfDvDKDQ4ulUmxRLL60pnfMfWlTh5W26rU/DPC7iN MefLvaCmVwdSYx5CmWIHjDbvgUnbIQde6rjytm1htejbsBI3saqYRJsJ5RyCaB63CYml YCZXpXT/pgSSX97nSSymW6BK7A//Z4+KOn924xmabVy0U7W1k9ihfMzk6FBZRfyYXGdQ DPGgWxIe2V0xXMqThcch3xKuxzb3vBUdrzwfkcGwKbn3qn/Be2oriJRFQMuvtKr3oNcp wPGbOSOSQfwfyf9WS8JdqG4A7t0/LrFLjuxfmNjMAslYWlG3s9/RJcJs1YdQ4Z7RtSvc Nc7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="l6/utQTF"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 1a35830..77fa97c 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -332,6 +332,9 @@ ; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie-mem"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; From patchwork Thu Jul 13 11:20:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 119785 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1755094vqm; Thu, 13 Jul 2023 04:30:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlHXornjeWLDm1cCHeQ6h0BDQpGliCfPAn5bAp7KPCdA6/pNkS19tr+Zno1n5j5qtAqJEic5 X-Received: by 2002:a17:906:539a:b0:993:dd1d:8252 with SMTP id g26-20020a170906539a00b00993dd1d8252mr1168550ejo.22.1689247854936; Thu, 13 Jul 2023 04:30:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689247854; cv=none; d=google.com; s=arc-20160816; b=YGt78aDAuQvw+apaeNTpMYSeljNxbMKlPVTI871zMC8h10sbFkAATr+IRrZ3Z+xu4N IROu1nwdpqOj6Nq9ANGdfmLSzw5+0KooMvYIvkMiUNNGhmAkgRdJPiTH3aqtVy4UQHw5 VXNZkrRsVrL6GvA+JBI/XHOYigWy7NQK1H4nk1qriSL8mf3TbhKI8qFM7ulTmolAeBJi YMOijRBMISv62Ah6FxuLx/D3soZ0E+I7SuGsPfoXx0M8tdtTvl4m5sX5tEhcZe9+3zbj dMKt3y2e33AVvt2PkY3ZPPOZQQd1QfFnTSKwm03oH/GH0uYbVU8HkO3vIN436sTXIDu0 risA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=v89CRS7CxCh3o1XBNy4m1cpnYqKFuJYcIzlFhO7tpZk=; fh=YGwQkGPlUGKIFct+ZojP5owKVkfEOhHMSUOncW4VrC4=; b=r/VQmtQLYEeHQPeHQqqDkFPiequpC7nwawuZauSkMXmPfvnvVluIrErzjYh1P2U/iU DVYXRnUsplyUojfaevL3xWyQslzirLpdl2RgJKb7bNh3fB7MaWvwJPlmgchsgaWAPx1R 5wl5n6qsnnCI6KEiNqUgsMfN/u0k8gBTTwjvSagHRJdDYDn0MD0DtoKwLeeJzRt+Mpfm TdE+7JcWhJj/qiSTblaFfAMJzdKbcR2LOIYajg2bQuULvpyPQjpJ7wbD2Rr/khndlge+ DK21++zLSCjHAEDYXa06k8M49CNVcDhXF6kjtgnn+0WrjPfMQhZq/Cl1j3MzbCHjgjec HZUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DBYvn4lh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Thu, 13 Jul 2023 11:20:23 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36DBKK21012007; Thu, 13 Jul 2023 11:20:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3rq0vm0p93-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 13 Jul 2023 11:20:20 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36DBKJvn011991; Thu, 13 Jul 2023 11:20:19 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 36DBKJ6a011979; Thu, 13 Jul 2023 11:20:19 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D58BD4AC7; Thu, 13 Jul 2023 16:50:18 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v8 3/3] PCI: qcom-ep: Add ICC bandwidth voting support Date: Thu, 13 Jul 2023 16:50:13 +0530 Message-Id: <1689247213-13569-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com> References: <1689247213-13569-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VEvxgUv7VLUcS0E7ZmLY8kdRamiban9L X-Proofpoint-ORIG-GUID: VEvxgUv7VLUcS0E7ZmLY8kdRamiban9L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-13_04,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 suspectscore=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307130099 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771304758593996767 X-GMAIL-MSGID: 1771304758593996767 Add support for voting interconnect (ICC) bandwidth based on the link speed and width. This commit is inspired from the basic interconnect support added to pcie-qcom driver in commit c4860af88d0c ("PCI: qcom: Add basic interconnect support"). The interconnect support is kept optional to be backward compatible with legacy devicetrees. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 72 +++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0fe7f06..cf9fc94 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,7 @@ #define PARF_SYS_CTRL 0x00 #define PARF_DB_CTRL 0x10 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_MHI_BASE_ADDR_LOWER 0x178 #define PARF_MHI_BASE_ADDR_UPPER 0x17c @@ -133,6 +135,11 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ +#define PCIE_GEN1_BW_MBPS 250 +#define PCIE_GEN2_BW_MBPS 500 +#define PCIE_GEN3_BW_MBPS 985 +#define PCIE_GEN4_BW_MBPS 1969 + #define to_pcie_ep(x) dev_get_drvdata((x)->dev) enum qcom_pcie_ep_link_status { @@ -178,6 +185,8 @@ struct qcom_pcie_ep { struct phy *phy; struct dentry *debugfs; + struct icc_path *icc_mem; + struct clk_bulk_data *clks; int num_clks; @@ -253,8 +262,49 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) +{ + struct dw_pcie *pci = &pcie_ep->pci; + u32 offset, status, bw; + int speed, width; + int ret; + + if (!pcie_ep->icc_mem) + return; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); + + switch (speed) { + case 1: + bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); + break; + case 2: + bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); + break; + case 3: + bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); + break; + default: + dev_warn(pci->dev, "using default GEN4 bandwidth\n"); + fallthrough; + case 4: + bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); + break; + } + + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); + if (ret) + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); +} + static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) { + struct dw_pcie *pci = &pcie_ep->pci; int ret; ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); @@ -277,8 +327,24 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) if (ret) goto err_phy_exit; + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial peak bandwidth corresponding to single-lane Gen 1 + * for the pcie-mem path. + */ + ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + goto err_phy_off; + } + return 0; +err_phy_off: + phy_power_off(pcie_ep->phy); err_phy_exit: phy_exit(pcie_ep->phy); err_disable_clk: @@ -289,6 +355,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { + icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); @@ -550,6 +617,10 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev, if (IS_ERR(pcie_ep->phy)) ret = PTR_ERR(pcie_ep->phy); + pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc_mem)) + ret = PTR_ERR(pcie_ep->icc_mem); + return ret; } @@ -573,6 +644,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED; + qcom_pcie_ep_icc_update(pcie_ep); pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");