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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o17-20020a170906601100b009930740da67si5852717ejj.380.2023.07.12.23.07.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 23:07:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=siuZWJz7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9DBF3853D3F for ; Thu, 13 Jul 2023 06:05:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C9DBF3853D3F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689228344; bh=eocWNT2SYyZPflBUrQdFtGAviFyOdKAlaxRMjrUHf98=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=siuZWJz7KjB075RiHmskZGCURHOGkc6IxlOHuzUM5JE9BX8OPpSNO6vxPYn1h9Skw MMfpf8Cng/F6+G89BFRF0A9v9EY0FyNoYL8GQNz/ftrVN94s8r7RnZ88SlaZNntqJe JWUL2/ElTw4Q6gw5LU+SiR51dbG5H0mazRY0vc+4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id D5BE73857733 for ; Thu, 13 Jul 2023 06:03:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D5BE73857733 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="451457706" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="451457706" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:03:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="715822154" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="715822154" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 12 Jul 2023 23:03:38 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 595E91005698; Thu, 13 Jul 2023 14:03:37 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, Kong Lingling Subject: [PATCH 1/4] Support Intel AVX-VNNI-INT16 Date: Thu, 13 Jul 2023 14:03:32 +0800 Message-Id: <20230713060335.203711-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713060335.203711-1-haochen.jiang@intel.com> References: <20230713060335.203711-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771284386750234948 X-GMAIL-MSGID: 1771284386750234948 From: Kong Lingling gcc/ChangeLog * common/config/i386/cpuinfo.h (get_available_features): Detect avxvnniint16. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New. (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto. (ix86_handle_option): Handle -mavxvnniint16. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVXVNNIINT16. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for avxvnniint16. * config.gcc: Add avxvnniint16.h. * config/i386/avxvnniint16intrin.h: New file. * config/i386/cpuid.h (bit_AVXVNNIINT16): New. * config/i386/i386-builtin.def: Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVXVNNIINT16__. * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16. (ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h. * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16). * config/i386/i386.opt: Add option -mavxvnniint16. * config/i386/immintrin.h: Include avxvnniint16.h. * config/i386/sse.md (vpdp_): New define_insn. * doc/extend.texi: Document avxvnniint16. * doc/invoke.texi: Document -mavxvnniint16. * doc/sourcebuild.texi: Document target avxvnniint16. gcc/testsuite/ChangeLog * g++.dg/other/i386-2.C: Add -mavxvnniint16. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-check.h: Add avxvnniint16 check. * gcc.target/i386/sse-12.c: Add -mavxvnniint16. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * lib/target-supports.exp (check_effective_target_avxvnniint16): New. * gcc.target/i386/avxvnniint16-1.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusd-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwusds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwsuds-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuud-2.c: Ditto. * gcc.target/i386/avxvnniint16-vpdpwuuds-2.c: Ditto. Co-authored-by: Haochen Jiang --- gcc/common/config/i386/cpuinfo.h | 2 + gcc/common/config/i386/i386-common.cc | 22 ++- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 2 + gcc/config.gcc | 2 +- gcc/config/i386/avxvnniint16intrin.h | 138 ++++++++++++++++++ gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-builtin.def | 14 ++ gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 4 +- gcc/config/i386/i386.opt | 5 + gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sse.md | 32 ++++ gcc/doc/extend.texi | 5 + gcc/doc/invoke.texi | 10 +- gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/avx-check.h | 3 + .../gcc.target/i386/avxvnniint16-1.c | 43 ++++++ .../gcc.target/i386/avxvnniint16-vpdpwsud-2.c | 71 +++++++++ .../i386/avxvnniint16-vpdpwsuds-2.c | 72 +++++++++ .../gcc.target/i386/avxvnniint16-vpdpwusd-2.c | 71 +++++++++ .../i386/avxvnniint16-vpdpwusds-2.c | 72 +++++++++ .../gcc.target/i386/avxvnniint16-vpdpwuud-2.c | 71 +++++++++ .../i386/avxvnniint16-vpdpwuuds-2.c | 71 +++++++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 4 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- gcc/testsuite/lib/target-supports.exp | 12 ++ 34 files changed, 735 insertions(+), 15 deletions(-) create mode 100644 gcc/config/i386/avxvnniint16intrin.h create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 7c2565c1d93..3599f9def2c 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -875,6 +875,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVXVNNIINT8); if (edx & bit_AVXNECONVERT) set_feature (FEATURE_AVXNECONVERT); + if (edx & bit_AVXVNNIINT16) + set_feature (FEATURE_AVXVNNIINT16); } if (avx512_usable) { diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 8cea3669239..32c6d00580d 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -119,6 +119,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) +#define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -228,7 +229,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX2_UNSET \ (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ - | OPTION_MASK_ISA2_AVX512F_UNSET) + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ @@ -301,6 +302,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX +#define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1268,6 +1270,24 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavxvnniint16: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET; + opts->x_ix86_isa_flags2_explicit |= + OPTION_MASK_ISA2_AVXVNNIINT16_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags2 &= + ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET; + opts->x_ix86_isa_flags2_explicit |= + OPTION_MASK_ISA2_AVXVNNIINT16_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 254dfec70e5..ae4e6a02f7f 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -255,6 +255,7 @@ enum processor_features FEATURE_PREFETCHI, FEATURE_RAOINT, FEATURE_AMX_COMPLEX, + FEATURE_AVXVNNIINT16, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index d4b0b23b417..fc6abdedf24 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -186,4 +186,6 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("raoint", FEATURE_RAOINT, P_NONE, "-mraoint") ISA_NAMES_TABLE_ENTRY("amx-complex", FEATURE_AMX_COMPLEX, P_NONE, "-mamx-complex") + ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16, + P_NONE, "-mavxvnniint16") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index 1446eb2b3ca..fc74d776048 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -435,7 +435,7 @@ i[34567]86-*-* | x86_64-*-*) mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h - raointintrin.h amxcomplexintrin.h" + raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/avxvnniint16intrin.h b/gcc/config/i386/avxvnniint16intrin.h new file mode 100644 index 00000000000..f87d76cb9f3 --- /dev/null +++ b/gcc/config/i386/avxvnniint16intrin.h @@ -0,0 +1,138 @@ +/* Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _AVXVNNIINT16INTRIN_H_INCLUDED +#define _AVXVNNIINT16INTRIN_H_INCLUDED + +#if !defined(__AVXVNNIINT16__) +#pragma GCC push_options +#pragma GCC target("avxvnniint16") +#define __DISABLE_AVXVNNIINT16__ +#endif /* __AVXVNNIINT16__ */ + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwsud_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwsud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwsuds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwsuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwusd_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwusd128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwusds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwusds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwuud_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwuud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_dpwuuds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B) +{ + return (__m128i) + __builtin_ia32_vpdpwuuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwsud_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwsud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwsuds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwsuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwusd_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwusd256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwusds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwusds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwuud_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwuud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_dpwuuds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B) +{ + return (__m256i) + __builtin_ia32_vpdpwuuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B); +} + +#ifdef __DISABLE_AVXVNNIINT16__ +#undef __DISABLE_AVXVNNIINT16__ +#pragma GCC pop_options +#endif /* __DISABLE_AVXVNNIINT16__ */ + +#endif /* __AVXVNNIINT16INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 4cc44615cf6..98d0f193d22 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -144,6 +144,7 @@ /* %edx */ #define bit_AVXVNNIINT8 (1 << 4) #define bit_AVXNECONVERT (1 << 5) +#define bit_AVXVNNIINT16 (1 << 10) #define bit_PREFETCHI (1 << 14) /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 7ba5b6a9d11..ff5b3dcbcd3 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2740,6 +2740,20 @@ BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsuds_v4si, "__builtin_ia32 BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128", IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuuds_v4si, "__builtin_ia32_vpdpbuuds128", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +/* AVXVNNIINT16 */ +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256", IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusds_v8si, "__builtin_ia32_vpdpwusds256", IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256", IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsuds_v8si, "__builtin_ia32_vpdpwsuds256", IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256", IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuuds_v8si, "__builtin_ia32_vpdpwuuds256", IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128", IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusds_v4si, "__builtin_ia32_vpdpwusds128", IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128", IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsuds_v4si, "__builtin_ia32_vpdpwsuds128", IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128", IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuuds_v4si, "__builtin_ia32_vpdpwuuds128", IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) + /* VPCLMULQDQ */ BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpclmulqdq_v2di, "__builtin_ia32_vpclmulqdq_v2di", IX86_BUILTIN_VPCLMULQDQ2, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT) BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX, 0, CODE_FOR_vpclmulqdq_v4di, "__builtin_ia32_vpclmulqdq_v4di", IX86_BUILTIN_VPCLMULQDQ4, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index e7bd7cc706c..d3514dd46ac 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -677,6 +677,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__RAOINT__"); if (isa_flag2 & OPTION_MASK_ISA2_AMX_COMPLEX) def_or_undef (parse_in, "__AMX_COMPLEX__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16) + def_or_undef (parse_in, "__AVXVNNIINT16__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 0634c6f5bac..fbf22f7270a 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -117,3 +117,4 @@ DEF_PTA(AMX_FP16) DEF_PTA(PREFETCHI) DEF_PTA(RAOINT) DEF_PTA(AMX_COMPLEX) +DEF_PTA(AVXVNNIINT16) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 37cb5a0dcc4..d981666dd87 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -239,7 +239,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mamx-fp16", OPTION_MASK_ISA2_AMX_FP16 }, { "-mprefetchi", OPTION_MASK_ISA2_PREFETCHI }, { "-mraoint", OPTION_MASK_ISA2_RAOINT }, - { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX } + { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }, + { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, }; static struct ix86_target_opts isa_opts[] = { @@ -1091,6 +1092,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("prefetchi", OPT_mprefetchi), IX86_ATTR_ISA ("raoint", OPT_mraoint), IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex), + IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index d74f6b1f8fc..618d713530f 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1278,3 +1278,8 @@ Enum(lam_type) String(u57) Value(lam_u57) mamx-complex Target Mask(ISA2_AMX_COMPLEX) Var(ix86_isa_flags2) Save Support AMX-COMPLEX built-in functions and code generation. + +mavxvnniint16 +Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and +AVXVNNIINT16 built-in functions and code generation. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index b220d871942..52dc35d8398 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -48,6 +48,8 @@ #include +#include + #include #include diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6bf9c99a2c1..85a5f801e7a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -204,6 +204,14 @@ UNSPEC_VPDPBSUDS UNSPEC_VPDPBUUD UNSPEC_VPDPBUUDS + + ;; For AVX-VNNI-INT16 support + UNSPEC_VPDPWUSD + UNSPEC_VPDPWUSDS + UNSPEC_VPDPWSUD + UNSPEC_VPDPWSUDS + UNSPEC_VPDPWUUD + UNSPEC_VPDPWUUDS ]) (define_c_enum "unspecv" [ @@ -30209,3 +30217,27 @@ "vcvtneo2ps\t{%1, %0|%0, %1}" [(set_attr "prefix" "vex") (set_attr "mode" "")]) + +(define_int_iterator VPDPWPROD + [UNSPEC_VPDPWUSD + UNSPEC_VPDPWUSDS + UNSPEC_VPDPWSUD + UNSPEC_VPDPWSUDS + UNSPEC_VPDPWUUD + UNSPEC_VPDPWUUDS]) + +(define_int_attr vpdpwprodtype + [(UNSPEC_VPDPWUSD "wusd") (UNSPEC_VPDPWUSDS "wusds") + (UNSPEC_VPDPWSUD "wsud") (UNSPEC_VPDPWSUDS "wsuds") + (UNSPEC_VPDPWUUD "wuud") (UNSPEC_VPDPWUUDS "wuuds")]) + +(define_insn "vpdp_" + [(set (match_operand:VI4_AVX 0 "register_operand" "=x") + (unspec:VI4_AVX + [(match_operand:VI4_AVX 1 "register_operand" "0") + (match_operand:VI4_AVX 2 "register_operand" "x") + (match_operand:VI4_AVX 3 "nonimmediate_operand" "xm")] + VPDPWPROD))] + "TARGET_AVXVNNIINT16" + "vpdp\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "prefix" "vex")]) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 7e4c5541b11..565bf1352e2 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7163,6 +7163,11 @@ Enable/disable the generation of the RAOINT instructions. @itemx no-amx-complex Enable/disable the generation of the AMX-COMPLEX instructions. +@cindex @code{target("avxvnniint16")} function attribute, x86 +@item avxvnniint16 +@itemx no-avxvnniint16 +Enable/disable the generation of the AVXVNNIINT16 instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cbc1282c274..359887db5fd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 --mprefetchi -mraoint -mamx-complex +-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -33552,8 +33552,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex mamx-complex @itemx -mamx-complex +@need 200 +@opindex mavxvnniint16 +@itemx -mavxvnniint16 These switches enable the use of instructions in the MMX, SSE, -SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP, @@ -33563,8 +33565,8 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, -AMX-COMPLEX or CLDEMOTE extended instruction sets. Each has a corresponding -@option{-mno-} option to disable use of these instructions. +AMX-COMPLEX, AVXVNNIINT16 or CLDEMOTE extended instruction sets. Each has a +corresponding @option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see @ref{x86 Built-in Functions}, for details of the functions enabled and diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index ffb6eb1a48c..40919b30a62 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2511,6 +2511,9 @@ Target supports the execution of @code{avxneconvert} instructions. @item avxvnniint8 Target supports the execution of @code{avxvnniint8} instructions. +@item avxvnniint16 +Target supports the execution of @code{avxvnniint16} instructions. + @item amx_tile Target supports the execution of @code{amx-tile} instructions. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 6fe07e18fc6..53622df2bb8 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 55c81677300..3b76cee3af8 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc/testsuite/gcc.target/i386/avx-check.h index 666eff50780..3d417ea1ed5 100644 --- a/gcc/testsuite/gcc.target/i386/avx-check.h +++ b/gcc/testsuite/gcc.target/i386/avx-check.h @@ -31,6 +31,9 @@ main () #endif #ifdef AVXNECONVERT && __builtin_cpu_supports ("avxneconvert") +#endif +#ifdef AVXVNNIINT16 + && __builtin_cpu_supports ("avxvnniint16") #endif ) { diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c new file mode 100644 index 00000000000..6ae57b150fe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-mavxvnniint16 -O2" } */ +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + + +#include + +volatile __m256i x,y,z; +volatile __m128i x_,y_,z_; +volatile __mmask8 m; + +void extern +avxvnniint16_test (void) +{ + x = _mm256_dpwusd_avx_epi32 (x, y, z); + x_ = _mm_dpwusd_avx_epi32 (x_, y_, z_); + + x = _mm256_dpwusds_avx_epi32 (x, y, z); + x_ = _mm_dpwusds_avx_epi32 (x_, y_, z_); + + x = _mm256_dpwsud_avx_epi32 (x, y, z); + x_ = _mm_dpwsud_avx_epi32 (x_, y_, z_); + + x = _mm256_dpwsuds_avx_epi32 (x, y, z); + x_ = _mm_dpwsuds_avx_epi32 (x_, y_, z_); + + x = _mm256_dpwuud_avx_epi32 (x, y, z); + x_ = _mm_dpwuud_avx_epi32 (x_, y_, z_); + + x = _mm256_dpwuuds_avx_epi32 (x, y, z); + x_ = _mm_dpwuuds_avx_epi32 (x_, y_, z_); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c new file mode 100644 index 00000000000..bc57a8a8078 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c @@ -0,0 +1,71 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (int *r, int *dst, short *s1, unsigned short *s2, int size) +{ + int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (int) s1[i] * (unsigned int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + int test = (int) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test; + } +} + +void +TEST (void) +{ + int i; + union256i_d res_256; + union256i_w src1_256; + union256i_uw src2_256; + int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwsud_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_d (res_256, res_ref_256)) + abort (); + + union128i_d res_128; + union128i_w src1_128; + union128i_uw src2_128; + int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwsud_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_d (res_128, res_ref_128)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c new file mode 100644 index 00000000000..fbcf46a4827 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c @@ -0,0 +1,72 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (int *r, int *dst, short *s1, unsigned short *s2, int size) +{ + int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (int) s1[i] * (unsigned int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + long long test = (long long) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF : + (test < 0xffffffff80000000LL ? 0x80000000 : test); + } +} + +void +TEST (void) +{ + int i; + union256i_d res_256; + union256i_w src1_256; + union256i_uw src2_256; + int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwsuds_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_d (res_256, res_ref_256)) + abort (); + + union128i_d res_128; + union128i_w src1_128; + union128i_uw src2_128; + int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwsuds_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_d (res_128, res_ref_128)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c new file mode 100644 index 00000000000..54cf271acbf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c @@ -0,0 +1,71 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (int *r, int *dst, unsigned short *s1, short *s2, int size) +{ + int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (unsigned int) s1[i] * (int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + int test = (int) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test; + } +} + +void +TEST (void) +{ + int i; + union256i_d res_256; + union256i_uw src1_256; + union256i_w src2_256; + int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwusd_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_d (res_256, res_ref_256)) + abort (); + + union128i_d res_128; + union128i_uw src1_128; + union128i_w src2_128; + int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwusd_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_d (res_128, res_ref_128)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c new file mode 100644 index 00000000000..ed9594c708b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c @@ -0,0 +1,72 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (int *r, int *dst, unsigned short *s1, short *s2, int size) +{ + int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (unsigned int) s1[i] * (int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + long long test = (long long) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF : + (test < 0xffffffff80000000LL ? 0x80000000 : test); + } +} + +void +TEST (void) +{ + int i; + union256i_d res_256; + union256i_uw src1_256; + union256i_w src2_256; + int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwusds_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_d (res_256, res_ref_256)) + abort (); + + union128i_d res_128; + union128i_uw src1_128; + union128i_w src2_128; + int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwusds_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_d (res_128, res_ref_128)) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c new file mode 100644 index 00000000000..8bdc4330ef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c @@ -0,0 +1,71 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (unsigned int *r, unsigned int *dst, unsigned short *s1, unsigned short *s2, int size) +{ + unsigned int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (unsigned int) s1[i] * (unsigned int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + unsigned int test = (unsigned) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test; + } +} + +void +TEST (void) +{ + int i; + union256i_ud res_256; + union256i_uw src1_256; + union256i_uw src2_256; + unsigned int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwuud_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_ud (res_256, res_ref_256)) + abort (); + + union128i_ud res_128; + union128i_uw src2_128; + union128i_uw src1_128; + unsigned int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwuud_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_ud (res_128, res_ref_128)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c new file mode 100644 index 00000000000..32204122f1c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c @@ -0,0 +1,71 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavxvnniint16" } */ +/* { dg-require-effective-target avxvnniint16 } */ +#define AVXVNNIINT16 +#ifndef CHECK +#define CHECK "avx-check.h" +#endif + +#ifndef TEST +#define TEST avx_test +#endif + +#include CHECK + +static void +CALC (unsigned int *r, unsigned int *dst, unsigned short *s1, unsigned short *s2, int size) +{ + unsigned int tempres[16]; + for (int i = 0; i < size; i++) + tempres[i] = (unsigned int) s1[i] * (unsigned int) s2[i]; + for (int i = 0; i < size / 2; i++) + { + unsigned int test = (unsigned) dst[i] + tempres[i * 2] + tempres[i * 2 + 1]; + r[i] = test > 0xFFFFFFFF ? 0xFFFFFFFF : test; + } +} + +void +TEST (void) +{ + int i; + union256i_ud res_256; + union256i_uw src1_256; + union256i_uw src2_256; + unsigned int res_ref_256[8]; + + for (i = 0; i < 16; i++) + { + int sign = i % 2 ? 1 : -1; + src1_256.a[i] = 10 + 3 * i + sign; + src2_256.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 8; i++) + res_256.a[i] = 0x7fffffff; + + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16); + res_256.x = _mm256_dpwuuds_avx_epi32 (res_256.x, src1_256.x, src2_256.x); + if (check_union256i_ud (res_256, res_ref_256)) + abort (); + + union128i_ud res_128; + union128i_uw src2_128; + union128i_uw src1_128; + unsigned int res_ref_128[4]; + + for (i = 0; i < 8; i++) + { + int sign = i % 2 ? 1 : -1; + src1_128.a[i] = 10 + 3 * i * i + sign; + src2_128.a[i] = sign * 10 * i * i; + } + + for (i = 0; i < 4; i++) + res_128.a[i] = 0x7fffffff; + + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8); + res_128.x = _mm_dpwuuds_avx_epi32 (res_128.x, src1_128.x, src2_128.x); + if (check_union128i_ud (res_128, res_ref_128)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index f466962c36c..bba0fa37efd 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -88,6 +88,7 @@ extern void test_amx_fp16 (void) __attribute__((__target__("amx-fp16"))); extern void test_prefetchi (void) __attribute__((__target__("prefetchi"))); extern void test_raoint (void) __attribute__((__target__("raoint"))); extern void test_amx_complex (void) __attribute__((__target__("amx-complex"))); +extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -177,6 +178,7 @@ extern void test_no_amx_fp16 (void) __attribute__((__target__("no-amx-fp16"))); extern void test_no_prefetchi (void) __attribute__((__target__("no-prefetchi"))); extern void test_no_raoint (void) __attribute__((__target__("no-raoint"))); extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex"))); +extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index ae4ffd1975f..2b7d78c51d3 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index f046a68ddbb..33693484d2a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 05322f7e914..51c2946b25a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 53c38b70241..4982fde2a76 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 50bf85a3392..7e9c9f2ca2b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -847,6 +847,6 @@ #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16") #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 33482b2fa9a..60de239f1ce 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9856,6 +9856,18 @@ proc check_effective_target_amx_complex { } { } "-mamx-complex" ] } +# Return 1 if avxvnniint16 instructions can be compiled. +proc check_effective_target_avxvnniint16 { } { + return [check_no_compiler_messages avxvnniint16 object { + typedef int __v8si __attribute__ ((__vector_size__ (32))); + __v8si + _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C) + { + return __builtin_ia32_vpdpwsud256 (__A, __B, __C); + } + } "-O0 -mavxvnniint16" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { From patchwork Thu Jul 13 06:03:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 119557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1616557vqm; Wed, 12 Jul 2023 23:05:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlGf+JjPHemeajdYy1Qoz/nkGfrcsHLBA9LWhuauOBpy/zkVHDZev2O+1Tsux+QxV77kpOar X-Received: by 2002:a17:906:297:b0:98e:2b00:c509 with SMTP id 23-20020a170906029700b0098e2b00c509mr572228ejf.30.1689228339267; Wed, 12 Jul 2023 23:05:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689228339; cv=none; d=google.com; s=arc-20160816; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id lw28-20020a170906bcdc00b0098e1263aadbsi7227467ejb.100.2023.07.12.23.05.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 23:05:39 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=uk3YJStk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 363123856967 for ; Thu, 13 Jul 2023 06:04:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 363123856967 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689228286; bh=xV3FrvbGTyGvpzl/DSLu0kV7mFJs93nYwUvgz8/0oBA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=uk3YJStkn01q8qgS5lB/2LlamiqthwGwXh4sa56Tg6dU/csMBn51JsdA474QgqAV8 ToI7hoNRW2MfsEUd9pTabgHRpv7J3HXxAt4nW9FkwC5Xha2nff2g4IS20sQTiilRuw tOC8CUCMc3M8IPwq61KMd4Le7LBzJztw3Hn+rfI8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id D496F385771B for ; Thu, 13 Jul 2023 06:03:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D496F385771B X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="451457704" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="451457704" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:03:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="715822152" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="715822152" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 12 Jul 2023 23:03:38 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5F7D9100569D; Thu, 13 Jul 2023 14:03:37 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 2/4] Support Intel SM3 Date: Thu, 13 Jul 2023 14:03:33 +0800 Message-Id: <20230713060335.203711-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713060335.203711-1-haochen.jiang@intel.com> References: <20230713060335.203711-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771284295007075405 X-GMAIL-MSGID: 1771284295007075405 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SM3. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM3_SET, OPTION_MASK_ISA2_SM3_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM3. (ix86_handle_option): Handle -msm3. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM3. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for SM3. * config.gcc: Add sm3intrin.h * config/i386/cpuid.h (bit_SM3): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM3__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4SI_FTYPE_V4SI_V4SI_V4SI_INT. * config/i386/i386-isa.def (SM3): Add DEF_PTA(SM3). * config/i386/i386-options.cc (isa2_opts): Add -msm3. (ix86_valid_target_attribute_inner_p): Handle sm3. * config/i386/i386.opt: Add option -msm3. * config/i386/immintrin.h: Include sm3intrin.h. * config/i386/sse.md (vsm3msg1): New define insn. (vsm3msg2): Ditto. (vsm3rnds2): Ditto. * doc/extend.texi: Document sm3. * doc/invoke.texi: Document -msm3. * doc/sourcebuild.texi: Document target sm3. * config/i386/sm3intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm3. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/avx-1.c: Add new define for immediate. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm3. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm3. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm3): New. * gcc.target/i386/sm3-1.c: New test. * gcc.target/i386/sm3-check.h: Ditto. * gcc.target/i386/sm3msg1-2.c: Ditto. * gcc.target/i386/sm3msg2-2.c: Ditto. * gcc.target/i386/sm3rnds2-2.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 2 + gcc/common/config/i386/i386-common.cc | 20 +++- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config.gcc | 3 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-builtin-types.def | 3 + gcc/config/i386/i386-builtin.def | 5 + gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-expand.cc | 1 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 2 + gcc/config/i386/i386.opt | 5 + gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sm3intrin.h | 72 ++++++++++++ gcc/config/i386/sse.md | 43 ++++++++ gcc/doc/extend.texi | 5 + gcc/doc/invoke.texi | 7 +- gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/avx-1.c | 3 + gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/sm3-1.c | 17 +++ gcc/testsuite/gcc.target/i386/sm3-check.h | 37 +++++++ gcc/testsuite/gcc.target/i386/sm3msg1-2.c | 54 +++++++++ gcc/testsuite/gcc.target/i386/sm3msg2-2.c | 57 ++++++++++ gcc/testsuite/gcc.target/i386/sm3rnds2-2.c | 104 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 5 +- gcc/testsuite/gcc.target/i386/sse-14.c | 5 +- gcc/testsuite/gcc.target/i386/sse-22.c | 7 +- gcc/testsuite/gcc.target/i386/sse-23.c | 5 +- gcc/testsuite/lib/target-supports.exp | 15 +++ 34 files changed, 484 insertions(+), 12 deletions(-) create mode 100644 gcc/config/i386/sm3intrin.h create mode 100644 gcc/testsuite/gcc.target/i386/sm3-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sm3-check.h create mode 100644 gcc/testsuite/gcc.target/i386/sm3msg1-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sm3msg2-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sm3rnds2-2.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 3599f9def2c..e5cdffe017a 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -877,6 +877,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVXNECONVERT); if (edx & bit_AVXVNNIINT16) set_feature (FEATURE_AVXVNNIINT16); + if (eax & bit_SM3) + set_feature (FEATURE_SM3); } if (avx512_usable) { diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 32c6d00580d..57b008ca3af 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -120,6 +120,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 +#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -303,6 +304,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16 +#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -351,7 +353,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET \ - (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET) + (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \ + | OPTION_MASK_ISA2_SM3_UNSET) #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET @@ -1288,6 +1291,21 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_msm3: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index ae4e6a02f7f..c3403090c3b 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -256,6 +256,7 @@ enum processor_features FEATURE_RAOINT, FEATURE_AMX_COMPLEX, FEATURE_AVXVNNIINT16, + FEATURE_SM3, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index fc6abdedf24..961a7f0ccd4 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -188,4 +188,5 @@ ISA_NAMES_TABLE_START P_NONE, "-mamx-complex") ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16, P_NONE, "-mavxvnniint16") + ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index fc74d776048..fbd7360e355 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -435,7 +435,8 @@ i[34567]86-*-* | x86_64-*-*) mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h - raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h" + raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h + sm3intrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 98d0f193d22..28a36ad0628 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -132,6 +132,7 @@ /* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */ /* %eax */ +#define bit_SM3 (1 << 1) #define bit_RAOINT (1 << 3) #define bit_AVXVNNI (1 << 4) #define bit_AVX512BF16 (1 << 5) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index cb2d0cd56ed..899eac1e014 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1416,3 +1416,6 @@ DEF_FUNCTION_TYPE (LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT) # PREFETCHI builtins DEF_FUNCTION_TYPE (VOID, PCVOID, INT) DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT) + +# SM3 builtins +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ff5b3dcbcd3..17db19c2495 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1655,6 +1655,11 @@ BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI) BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +/* SM3 */ +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_ia32_vsm3msg1", IX86_BUILTIN_VSM3MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) +BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) + /* AVX512VL. */ BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index d3514dd46ac..0cb5a6dcce5 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -679,6 +679,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AMX_COMPLEX__"); if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16) def_or_undef (parse_in, "__AVXVNNIINT16__"); + if (isa_flag2 & OPTION_MASK_ISA2_SM3) + def_or_undef (parse_in, "__SM3__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 648d6098eff..f6ad54c0cfe 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -11202,6 +11202,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V4SF_FTYPE_V4SF_V4SF_V4SI_INT: case V8SF_FTYPE_V8SF_V8SF_V8SI_INT: case V16SF_FTYPE_V16SF_V16SF_V16SI_INT: + case V4SI_FTYPE_V4SI_V4SI_V4SI_INT: nargs = 4; nargs_constant = 1; break; diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index fbf22f7270a..432c36e7f79 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -118,3 +118,4 @@ DEF_PTA(PREFETCHI) DEF_PTA(RAOINT) DEF_PTA(AMX_COMPLEX) DEF_PTA(AVXVNNIINT16) +DEF_PTA(SM3) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index d981666dd87..db2ff0c7ae1 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -241,6 +241,7 @@ static struct ix86_target_opts isa2_opts[] = { "-mraoint", OPTION_MASK_ISA2_RAOINT }, { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }, { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, + { "-msm3", OPTION_MASK_ISA2_SM3 } }; static struct ix86_target_opts isa_opts[] = { @@ -1093,6 +1094,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("raoint", OPT_mraoint), IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex), IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16), + IX86_ATTR_ISA ("sm3", OPT_msm3), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 618d713530f..80a8611993c 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1283,3 +1283,8 @@ mavxvnniint16 Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVXVNNIINT16 built-in functions and code generation. + +msm3 +Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SM3 built-in functions and code generation. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 52dc35d8398..7731990131c 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -108,6 +108,8 @@ #include +#include + #include #include diff --git a/gcc/config/i386/sm3intrin.h b/gcc/config/i386/sm3intrin.h new file mode 100644 index 00000000000..378c3dd41d9 --- /dev/null +++ b/gcc/config/i386/sm3intrin.h @@ -0,0 +1,72 @@ +/* Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _SM3INTRIN_H_INCLUDED +#define _SM3INTRIN_H_INCLUDED + +#ifndef __SM3__ +#pragma GCC push_options +#pragma GCC target("sm3") +#define __DISABLE_SM3__ +#endif /* __SM3__ */ + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A, (__v4si) __B, + (__v4si) __C); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_sm3msg2_epi32 (__m128i __A, __m128i __B, __m128i __C) +{ + return (__m128i) __builtin_ia32_vsm3msg2 ((__v4si) __A, (__v4si) __B, + (__v4si) __C); +} + +#ifdef __OPTIMIZE__ +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_sm3rnds2_epi32 (__m128i __A, __m128i __B, __m128i __C, const int __D) +{ + return (__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) __A, (__v4si) __B, + (__v4si) __C, __D); +} +#else +#define _mm_sm3rnds2_epi32(A, B, C, D) \ + ((__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) (A), (__v4si) (B), \ + (__v4si) (C), (int) (D))) +#endif + +#ifdef __DISABLE_SM3__ +#undef __DISABLE_SM3__ +#pragma GCC pop_options +#endif /* __DISABLE_SM3__ */ + +#endif /* _SM3INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 85a5f801e7a..25a1e5dd780 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -196,6 +196,11 @@ UNSPEC_COMPLEX_FMUL UNSPEC_COMPLEX_FCMUL UNSPEC_COMPLEX_MASK + + ;; For SM3 support + UNSPEC_SM3MSG1 + UNSPEC_SM3MSG2 + UNSPEC_SM3RNDS2 ;; For AVX-VNNI-INT8 support UNSPEC_VPDPBSSD @@ -28597,6 +28602,44 @@ (set_attr "length_immediate" "1") (set_attr "mode" "TI")]) +(define_insn "vsm3msg1" + [(set (match_operand:V4SI 0 "register_operand" "=x") + (unspec:V4SI + [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "x") + (match_operand:V4SI 3 "vector_operand" "xBm")] + UNSPEC_SM3MSG1))] + "TARGET_SM3" + "vsm3msg1\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "other") + (set_attr "mode" "TI")]) + +(define_insn "vsm3msg2" + [(set (match_operand:V4SI 0 "register_operand" "=x") + (unspec:V4SI + [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "x") + (match_operand:V4SI 3 "vector_operand" "xBm")] + UNSPEC_SM3MSG2))] + "TARGET_SM3" + "vsm3msg2\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "other") + (set_attr "mode" "TI")]) + +(define_insn "vsm3rnds2" + [(set (match_operand:V4SI 0 "register_operand" "=x") + (unspec:V4SI + [(match_operand:V4SI 1 "register_operand" "0") + (match_operand:V4SI 2 "register_operand" "x") + (match_operand:V4SI 3 "vector_operand" "xBm") + (match_operand:SI 4 "const_0_to_255_operand" "n")] + UNSPEC_SM3RNDS2))] + "TARGET_SM3" + "vsm3rnds2\t{%4, %3, %2, %0|%0, %2, %3, %4}" + [(set_attr "type" "other") + (set_attr "mode" "TI") + (set_attr "length_immediate" "1")]) + (define_insn_and_split "avx512f__" [(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m") (vec_concat:AVX512MODE2P diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 565bf1352e2..e76cd399a83 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7168,6 +7168,11 @@ Enable/disable the generation of the AMX-COMPLEX instructions. @itemx no-avxvnniint16 Enable/disable the generation of the AVXVNNIINT16 instructions. +@cindex @code{target("sm3")} function attribute, x86 +@item sm3 +@itemx no-sm3 +Enable/disable the generation of the SM3 instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 359887db5fd..2671d70736f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 --mprefetchi -mraoint -mamx-complex -mavxvnniint16 +-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -33555,6 +33555,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex mavxvnniint16 @itemx -mavxvnniint16 +@need 200 +@opindex msm3 +@itemx -msm3 These switches enable the use of instructions in the MMX, SSE, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, @@ -33565,7 +33568,7 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, -AMX-COMPLEX, AVXVNNIINT16 or CLDEMOTE extended instruction sets. Each has a +AMX-COMPLEX, AVXVNNIINT16, SM3 or CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 40919b30a62..dae51132c42 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2589,6 +2589,9 @@ Target supports the execution of @code{raoint} instructions. @item rdrand Target supports x86 @code{rdrand} instruction. +@item sm3 +Target supports the execution of @code{sm3} instructions. + @item sqrt_insn Target has a square root instruction that the compiler can generate. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 53622df2bb8..2ec93261cac 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 3b76cee3af8..fe03143e39b 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 0b2b68b678d..a6589deca84 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -839,6 +839,9 @@ #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1) +/* sm3intrin.h */ +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) + #include #include #include diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index bba0fa37efd..8dd8d9bf9d8 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -89,6 +89,7 @@ extern void test_prefetchi (void) __attribute__((__target__("prefe extern void test_raoint (void) __attribute__((__target__("raoint"))); extern void test_amx_complex (void) __attribute__((__target__("amx-complex"))); extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16"))); +extern void test_sm3 (void) __attribute__((__target__("sm3"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -179,6 +180,7 @@ extern void test_no_prefetchi (void) __attribute__((__target__("no-pr extern void test_no_raoint (void) __attribute__((__target__("no-raoint"))); extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex"))); extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16"))); +extern void test_no_sm3 (void) __attribute__((__target__("no-sm3"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/sm3-1.c b/gcc/testsuite/gcc.target/i386/sm3-1.c new file mode 100644 index 00000000000..0a8ea658130 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm3-1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msm3" } */ +/* { dg-final { scan-assembler "vsm3msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsm3msg2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsm3rnds2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ + +#include + +volatile __m128i x, y, z; + +void extern +sm3_test (void) +{ + x = _mm_sm3msg1_epi32 (x, y, z); + x = _mm_sm3msg2_epi32 (x, y, z); + x = _mm_sm3rnds2_epi32 (x, y, z, 1); +} diff --git a/gcc/testsuite/gcc.target/i386/sm3-check.h b/gcc/testsuite/gcc.target/i386/sm3-check.h new file mode 100644 index 00000000000..ad9847402fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm3-check.h @@ -0,0 +1,37 @@ +#include +#include "m128-check.h" + +static void sm3_test (void); + +static unsigned +rol32 (unsigned w, int n) +{ + int count = n % 32; + return ((w << n) | (w >> (32 - n))); +} + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sm3_test (); +} + +int +main () +{ + /* Run SM3 test only if host has SM3 support. */ + if (__builtin_cpu_supports ("sm3")) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } + +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/sm3msg1-2.c b/gcc/testsuite/gcc.target/i386/sm3msg1-2.c new file mode 100644 index 00000000000..e08abf5539d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm3msg1-2.c @@ -0,0 +1,54 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msm3" } */ +/* { dg-require-effective-target sm3 } */ + +#include "sm3-check.h" +#include +#include + +static unsigned +p1 (unsigned w) +{ + return rol32 (w, 15) ^ rol32 (w, 23) ^ w; +} + +static void +compute_sm3msg1 (int *src0, int *src1, int *src2, int *res) +{ + unsigned w0, w1, w2, w3, w7, w8, w9, w10, w13, w14, w15; + + w0 = src2[0]; + w1 = src2[1]; + w2 = src2[2]; + w3 = src2[3]; + w7 = src0[0]; + w8 = src0[1]; + w9 = src0[2]; + w10 = src0[3]; + w13 = src1[0]; + w14 = src1[1]; + w15 = src1[2]; + + res[0] = p1 (w7 ^ w0 ^ rol32 (w13, 15)); + res[1] = p1 (w8 ^ w1 ^ rol32 (w14, 15)); + res[2] = p1 (w9 ^ w2 ^ rol32 (w15, 15)); + res[3] = p1 (w10 ^ w3); +} + +static void +sm3_test (void) +{ + union128i_d s1, s2, s3, res; + int res_ref[4]; + + s1.x = _mm_set_epi32 (111, 222, 333, 444); + s2.x = _mm_set_epi32 (555, 666, 777, 888); + s3.x = _mm_set_epi32 (999, 123, 456, 789); + + res.x = _mm_sm3msg1_epi32 (s1.x, s2.x, s3.x); + + compute_sm3msg1 (s1.a, s2.a, s3.a, res_ref); + + if (check_union128i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sm3msg2-2.c b/gcc/testsuite/gcc.target/i386/sm3msg2-2.c new file mode 100644 index 00000000000..f5986313c7d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm3msg2-2.c @@ -0,0 +1,57 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msm3" } */ +/* { dg-require-effective-target sm3 } */ + +#include "sm3-check.h" +#include +#include + +static void +compute_sm3msg2 (int *src0, int *src1, int *src2, int *res) +{ + unsigned wtmp0, wtmp1, wtmp2, wtmp3, w3, w4, w5, w6, w10, w11, w12, w13, + w16, w17, w18, w19; + + wtmp0 = src0[0]; + wtmp1 = src0[1]; + wtmp2 = src0[2]; + wtmp3 = src0[3]; + w3 = src1[0]; + w4 = src1[1]; + w5 = src1[2]; + w6 = src1[3]; + w10 = src2[0]; + w11 = src2[1]; + w12 = src2[2]; + w13 = src2[3]; + + w16 = rol32 (w3, 7) ^ w10 ^ wtmp0; + w17 = rol32 (w4, 7) ^ w11 ^ wtmp1; + w18 = rol32 (w5, 7) ^ w12 ^ wtmp2; + w19 = rol32 (w6, 7) ^ w13 ^ wtmp3; + + w19 = w19 ^ rol32 (w16, 6) ^ rol32 (w16, 15) ^ rol32 (w16, 30) ; + + res[0] = w16; + res[1] = w17; + res[2] = w18; + res[3] = w19; +} + +static void +sm3_test (void) +{ + union128i_d s1, s2, s3, res; + int res_ref[4]; + + s1.x = _mm_set_epi32 (111, 222, 333, 444); + s2.x = _mm_set_epi32 (555, 666, 777, 888); + s3.x = _mm_set_epi32 (999, 123, 456, 789); + + res.x = _mm_sm3msg2_epi32 (s1.x, s2.x, s3.x); + + compute_sm3msg2 (s1.a, s2.a, s3.a, res_ref); + + if (check_union128i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sm3rnds2-2.c b/gcc/testsuite/gcc.target/i386/sm3rnds2-2.c new file mode 100644 index 00000000000..ffa3ed125f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm3rnds2-2.c @@ -0,0 +1,104 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msm3" } */ +/* { dg-require-effective-target sm3 } */ + +#include "sm3-check.h" +#include +#include + +static unsigned +p0 (unsigned w) +{ + return (w ^ rol32 (w, 9) ^ rol32 (w, 17)); +} + +static unsigned +ff (unsigned x, unsigned y, unsigned z, int round) +{ + if (round < 16) + return (x ^ y ^ z); + else + return ((x & y) | (x & z) | (y & z)); +} + +static unsigned +gg (unsigned x, unsigned y, unsigned z, int round) +{ + if (round < 16) + return (x ^ y ^ z); + else + return ((x & y) | ((~x) & z)); +} + +static void +compute_sm3rnds2 (int *src0, int *src1, int *src2, int imm, int *res) +{ + unsigned s1, s2, t1, t2, co; + unsigned w[6], a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3]; + int round, i; + + a[0] = src1[3]; + b[0] = src1[2]; + c[0] = src0[3]; + d[0] = src0[2]; + e[0] = src1[1]; + f[0] = src1[0]; + g[0] = src0[1]; + h[0] = src0[0]; + w[0] = src2[0]; + w[1] = src2[1]; + w[4] = src2[2]; + w[5] = src2[3]; + + c[0] = rol32 (c[0], 9); + d[0] = rol32 (d[0], 9); + g[0] = rol32 (g[0], 19); + h[0] = rol32 (h[0], 19); + + round = imm & 0x3e; + if (round < 16) + co = 0x79cc4519; + else + co = 0x7a879d8a; + co = rol32 (co, round); + + for (i = 0; i < 2; i++) + { + s1 = rol32 ((rol32 (a[i], 12) + e[i] + co), 7); + s2 = s1 ^ rol32 (a[i], 12); + t1 = ff (a[i], b[i], c[i], round) + d[i] + s2 + (w[i] ^ w[i + 4]); + t2 = gg (e[i], f[i], g[i], round) + h[i] + s1 + w[i]; + d[i + 1] = c[i]; + c[i + 1] = rol32 (b[i], 9); + b[i + 1] = a[i]; + a[i + 1] = t1; + h[i + 1] = g[i]; + g[i + 1] = rol32 (f[i], 19); + f[i + 1] = e[i]; + e[i + 1] = p0 (t2); + co = rol32 (co, 1); + } + + res[3] = a[2]; + res[2] = b[2]; + res[1] = e[2]; + res[0] = f[2]; +} + +static void +sm3_test (void) +{ + union128i_d s1, s2, s3, res; + int res_ref[4]; + + s1.x = _mm_set_epi32 (111, 222, 333, 444); + s2.x = _mm_set_epi32 (555, 666, 777, 888); + s3.x = _mm_set_epi32 (999, 123, 456, 789); + + res.x = _mm_sm3rnds2_epi32 (s1.x, s2.x, s3.x, 22); + + compute_sm3rnds2 (s1.a, s2.a, s3.a, 22, res_ref); + + if (check_union128i_d (res, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 2b7d78c51d3..5058be6f6e9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 33693484d2a..d30b365564a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ /* { dg-add-options bind_pic_locally } */ #include @@ -846,4 +846,7 @@ #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1) +/* sm3intrin.h */ +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) + #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 51c2946b25a..7842005a98b 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ /* { dg-add-options bind_pic_locally } */ #include @@ -1054,3 +1054,6 @@ test_2 (_mm512_gf2p8affineinv_epi64_epi8, __m512i, __m512i, __m512i, 1) test_2 (_mm_gf2p8affine_epi64_epi8, __m128i, __m128i, __m128i, 1) test_2 (_mm256_gf2p8affine_epi64_epi8, __m256i, __m256i, __m256i, 1) test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1) + +/* sm3intrin.h */ +test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 4982fde2a76..7537db1ac30 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) @@ -1099,3 +1099,6 @@ test_1 ( __bextri_u32, unsigned int, unsigned int, 1) #ifdef __x86_64__ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1) #endif + +/* sm3intrin.h */ +test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 7e9c9f2ca2b..3fc61b50fe6 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -847,6 +847,9 @@ #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16") +/* sm3intrin.h */ +#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) + +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3") #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 60de239f1ce..c911a824d31 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9868,6 +9868,21 @@ proc check_effective_target_avxvnniint16 { } { } "-O0 -mavxvnniint16" ] } +# Return 1 if sm3 instructions can be compiled. +proc check_effective_target_sm3 { } { + return [check_no_compiler_messages sm3 object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + __m128i + _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C) + { + return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A, + (__v4si) __B, + (__v4si) __C); + } + } "-msm3" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { From patchwork Thu Jul 13 06:03:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 119558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1617095vqm; Wed, 12 Jul 2023 23:06:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlE9sE6kNt9/KuyC5KQDJrDl4nhkZnjNfN7OfcpWbhVj++STxyMryVN/F/LYJXsu6ydHIcDO X-Received: by 2002:a05:6402:254c:b0:51e:5bd5:fe7e with SMTP id l12-20020a056402254c00b0051e5bd5fe7emr5563697edb.17.1689228413064; Wed, 12 Jul 2023 23:06:53 -0700 (PDT) ARC-Seal: i=1; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i1-20020aa7dd01000000b0051e226c4e6dsi7159810edv.278.2023.07.12.23.06.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 23:06:53 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=vb8+WlpL; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 626F8385DC26 for ; Thu, 13 Jul 2023 06:05:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 626F8385DC26 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689228334; bh=dsE/KYwXJ6zBL6sgJzdlWIxEY8xPqEBva497Y8Nl4KQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=vb8+WlpLK+IdBdy2yiOMZU0UUY3zp+mKY9WOEnqERjGLkWjqNgPiT4aF18+7SWfYq 4oJNO9U7UyONR8k1StMfQvo+MsUUDsrB6WI2XP5D8t1qNk+P502NJkp4TQn4adEuUx otOXU96xhvGjEkmIenMRLKndLUw4ZzT0HnasPIjo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 9462B3858002 for ; Thu, 13 Jul 2023 06:03:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9462B3858002 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="451457701" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="451457701" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:03:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="715822149" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="715822149" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 12 Jul 2023 23:03:38 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 64B571005052; Thu, 13 Jul 2023 14:03:37 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 3/4] Support Intel SHA512 Date: Thu, 13 Jul 2023 14:03:34 +0800 Message-Id: <20230713060335.203711-4-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713060335.203711-1-haochen.jiang@intel.com> References: <20230713060335.203711-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771284372725575672 X-GMAIL-MSGID: 1771284372725575672 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detect SHA512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET, OPTION_MASK_ISA2_SHA512_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SHA512. (ix86_handle_option): Handle -msha512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SHA512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sha512. * config.gcc: Add sha512intrin.h. * config/i386/cpuid.h (bit_SHA512): New. * config/i386/i386-builtin-types.def: Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI). * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SHA512__. * config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI. * config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512). * config/i386/i386-options.cc (isa2_opts): Add -msha512. (ix86_valid_target_attribute_inner_p): Handle sha512. * config/i386/i386.opt: Add option -msha512. * config/i386/immintrin.h: Include sha512intrin.h. * config/i386/sse.md (vsha512msg1): New define insn. (vsha512msg2): Ditto. (vsha512rnds2): Ditto. * doc/extend.texi: Document sha512. * doc/invoke.texi: Document -msha512. * doc/sourcebuild.texi: Document target sha512. * config/i386/sha512intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/others/i386-2.C: Add -msha512. * g++.dg/others/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msha512. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sha512. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sha512): New. * gcc.target/i386/sha512-1.c: New test. * gcc.target/i386/sha512-check.h: Ditto. * gcc.target/i386/sha512msg1-2.c: Ditto. * gcc.target/i386/sha512msg2-2.c: Ditto. * gcc.target/i386/sha512rnds2-2.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 2 + gcc/common/config/i386/i386-common.cc | 19 ++++- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-builtin-types.def | 3 + gcc/config/i386/i386-builtin.def | 5 ++ gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-expand.cc | 2 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 4 +- gcc/config/i386/i386.opt | 10 +++ gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sha512intrin.h | 64 ++++++++++++++ gcc/config/i386/sse.md | 40 +++++++++ gcc/doc/extend.texi | 5 ++ gcc/doc/invoke.texi | 10 ++- gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/sha512-1.c | 18 ++++ gcc/testsuite/gcc.target/i386/sha512-check.h | 43 ++++++++++ gcc/testsuite/gcc.target/i386/sha512msg1-2.c | 48 +++++++++++ gcc/testsuite/gcc.target/i386/sha512msg2-2.c | 47 ++++++++++ gcc/testsuite/gcc.target/i386/sha512rnds2-2.c | 85 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 4 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- gcc/testsuite/lib/target-supports.exp | 14 +++ 33 files changed, 436 insertions(+), 14 deletions(-) create mode 100644 gcc/config/i386/sha512intrin.h create mode 100644 gcc/testsuite/gcc.target/i386/sha512-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sha512-check.h create mode 100644 gcc/testsuite/gcc.target/i386/sha512msg1-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sha512msg2-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sha512rnds2-2.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index e5cdffe017a..0cfde3ebccd 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -879,6 +879,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_AVXVNNIINT16); if (eax & bit_SM3) set_feature (FEATURE_SM3); + if (eax & bit_SHA512) + set_feature (FEATURE_SHA512); } if (avx512_usable) { diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 57b008ca3af..97c3cdfe5e1 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -121,6 +121,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 +#define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -305,6 +306,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16 #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 +#define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -354,7 +356,7 @@ along with GCC; see the file COPYING3. If not see OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET \ (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \ - | OPTION_MASK_ISA2_SM3_UNSET) + | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET) #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET @@ -1306,6 +1308,21 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_msha512: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index c3403090c3b..a6e34d14f8e 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -257,6 +257,7 @@ enum processor_features FEATURE_AMX_COMPLEX, FEATURE_AVXVNNIINT16, FEATURE_SM3, + FEATURE_SHA512, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 961a7f0ccd4..250dc87764f 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -189,4 +189,5 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16, P_NONE, "-mavxvnniint16") ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") + ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index fbd7360e355..4e753ba7c64 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -436,7 +436,7 @@ i[34567]86-*-* | x86_64-*-*) avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h - sm3intrin.h" + sm3intrin.h sha512intrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 28a36ad0628..f9103f1b1c9 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -132,6 +132,7 @@ /* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */ /* %eax */ +#define bit_SHA512 (1 << 0) #define bit_SM3 (1 << 1) #define bit_RAOINT (1 << 3) #define bit_AVXVNNI (1 << 4) diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 899eac1e014..e9463120eea 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1419,3 +1419,6 @@ DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT) # SM3 builtins DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT) + +# SHA512 builtins +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 17db19c2495..b9e2bad8522 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1660,6 +1660,11 @@ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +/* SHA512 */ +BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg1, "__builtin_ia32_vsha512msg1", IX86_BUILTIN_VSHA512MSG1, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI) +BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg2, "__builtin_ia32_vsha512msg2", IX86_BUILTIN_VSHA512MSG2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI) +BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512rnds2, "__builtin_ia32_vsha512rnds2", IX86_BUILTIN_VSHA512RNDS2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V2DI) + /* AVX512VL. */ BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 0cb5a6dcce5..c6311f12cf9 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -681,6 +681,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AVXVNNIINT16__"); if (isa_flag2 & OPTION_MASK_ISA2_SM3) def_or_undef (parse_in, "__SM3__"); + if (isa_flag2 & OPTION_MASK_ISA2_SHA512) + def_or_undef (parse_in, "__SHA512__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index f6ad54c0cfe..e99dcf19364 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -10733,6 +10733,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V4SF_FTYPE_V4SF_UINT: case V4SF_FTYPE_V4SF_DI: case V4SF_FTYPE_V4SF_SI: + case V4DI_FTYPE_V4DI_V2DI: case V2DI_FTYPE_V2DI_V2DI: case V2DI_FTYPE_V16QI_V16QI: case V2DI_FTYPE_V4SI_V4SI: @@ -11030,6 +11031,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V8HI_FTYPE_V8DI_V8HI_UQI: case V8SI_FTYPE_V8DI_V8SI_UQI: case V4SI_FTYPE_V4SI_V4SI_V4SI: + case V4DI_FTYPE_V4DI_V4DI_V2DI: case V16SI_FTYPE_V16SI_V16SI_V16SI: case V8DI_FTYPE_V8DI_V8DI_V8DI: case V32HI_FTYPE_V32HI_V32HI_V32HI: diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 432c36e7f79..28f221753a9 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -119,3 +119,4 @@ DEF_PTA(RAOINT) DEF_PTA(AMX_COMPLEX) DEF_PTA(AVXVNNIINT16) DEF_PTA(SM3) +DEF_PTA(SHA512) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index db2ff0c7ae1..d79ab01bd79 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -241,7 +241,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mraoint", OPTION_MASK_ISA2_RAOINT }, { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }, { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, - { "-msm3", OPTION_MASK_ISA2_SM3 } + { "-msm3", OPTION_MASK_ISA2_SM3 }, + { "-msha512", OPTION_MASK_ISA2_SHA512 } }; static struct ix86_target_opts isa_opts[] = { @@ -1095,6 +1096,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex), IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16), IX86_ATTR_ISA ("sm3", OPT_msm3), + IX86_ATTR_ISA ("sha512", OPT_msha512), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 80a8611993c..cf9dbca58b3 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1288,3 +1288,13 @@ msm3 Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and SM3 built-in functions and code generation. + +mvpinsrvpextr +Target Mask(ISA2_VPINSRVPEXTR) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, +AVX512VL and VPINSRVPEXTR built-in functions and code generation. + +msha512 +Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SHA512 built-in functions and code generation. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 7731990131c..6f2bcef6a8a 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -110,6 +110,8 @@ #include +#include + #include #include diff --git a/gcc/config/i386/sha512intrin.h b/gcc/config/i386/sha512intrin.h new file mode 100644 index 00000000000..884c2bc6340 --- /dev/null +++ b/gcc/config/i386/sha512intrin.h @@ -0,0 +1,64 @@ +/* Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _SHA512INTRIN_H_INCLUDED +#define _SHA512INTRIN_H_INCLUDED + +#ifndef __SHA512__ +#pragma GCC push_options +#pragma GCC target("sha512") +#define __DISABLE_SHA512__ +#endif /* __SHA512__ */ + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_sha512msg1_epi64 (__m256i __A, __m128i __B) +{ + return (__m256i) __builtin_ia32_vsha512msg1 ((__v4di) __A, (__v2di) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_sha512msg2_epi64 (__m256i __A, __m256i __B) +{ + return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A, (__v4di) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_sha512rnds2_epi64 (__m256i __A, __m256i __B, __m128i __C) +{ + return (__m256i) __builtin_ia32_vsha512rnds2 ((__v4di) __A, (__v4di) __B, + (__v2di) __C); +} + +#ifdef __DISABLE_SHA512__ +#undef __DISABLE_SHA512__ +#pragma GCC pop_options +#endif /* __DISABLE_SHA512__ */ + +#endif /* _SHA512INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 25a1e5dd780..e16b2b5a6c4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -217,6 +217,12 @@ UNSPEC_VPDPWSUDS UNSPEC_VPDPWUUD UNSPEC_VPDPWUUDS + + ;; For SHA512 support + UNSPEC_SHA512MSG1 + UNSPEC_SHA512MSG2 + UNSPEC_SHA512RNDS2 + ]) (define_c_enum "unspecv" [ @@ -28640,6 +28646,40 @@ (set_attr "mode" "TI") (set_attr "length_immediate" "1")]) +(define_insn "vsha512msg1" + [(set (match_operand:V4DI 0 "register_operand" "=x") + (unspec:V4DI + [(match_operand:V4DI 1 "register_operand" "0") + (match_operand:V2DI 2 "register_operand" "x")] + UNSPEC_SHA512MSG1))] + "TARGET_SHA512" + "vsha512msg1\t{%2, %0|%0, %2}" + [(set_attr "type" "sselog1") + (set_attr "mode" "OI")]) + +(define_insn "vsha512msg2" + [(set (match_operand:V4DI 0 "register_operand" "=x") + (unspec:V4DI + [(match_operand:V4DI 1 "register_operand" "0") + (match_operand:V4DI 2 "register_operand" "x")] + UNSPEC_SHA512MSG2))] + "TARGET_SHA512" + "vsha512msg2\t{%2, %0|%0, %2}" + [(set_attr "type" "sselog1") + (set_attr "mode" "OI")]) + +(define_insn "vsha512rnds2" + [(set (match_operand:V4DI 0 "register_operand" "=x") + (unspec:V4DI + [(match_operand:V4DI 1 "register_operand" "0") + (match_operand:V4DI 2 "register_operand" "x") + (match_operand:V2DI 3 "register_operand" "x")] + UNSPEC_SHA512RNDS2))] + "TARGET_SHA512" + "vsha512rnds2\t{%3, %2, %0|%0, %2, %3}" + [(set_attr "type" "sselog1") + (set_attr "mode" "OI")]) + (define_insn_and_split "avx512f__" [(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m") (vec_concat:AVX512MODE2P diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index e76cd399a83..5250990050b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7173,6 +7173,11 @@ Enable/disable the generation of the AVXVNNIINT16 instructions. @itemx no-sm3 Enable/disable the generation of the SM3 instructions. +@cindex @code{target("sha512")} function attribute, x86 +@item sha512 +@itemx no-sha512 +Enable/disable the generation of the SHA512 instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2671d70736f..433ccf35505 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 --mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 +-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -33558,6 +33558,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex msm3 @itemx -msm3 +@need 200 +@opindex msha512 +@itemx -msha512 These switches enable the use of instructions in the MMX, SSE, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, @@ -33568,8 +33571,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, -AMX-COMPLEX, AVXVNNIINT16, SM3 or CLDEMOTE extended instruction sets. Each has a -corresponding @option{-mno-} option to disable use of these instructions. +AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512 or CLDEMOTE extended instruction sets. +Each has a corresponding @option{-mno-} option to disable use of these +instructions. These extensions are also available as built-in functions: see @ref{x86 Built-in Functions}, for details of the functions enabled and diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index dae51132c42..54a062db3fe 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2589,6 +2589,9 @@ Target supports the execution of @code{raoint} instructions. @item rdrand Target supports x86 @code{rdrand} instruction. +@item sha512 +Target supports the execution of @code{sha512} instructions. + @item sm3 Target supports the execution of @code{sm3} instructions. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 2ec93261cac..985f14abcbc 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index fe03143e39b..274b0e6256f 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 8dd8d9bf9d8..eb9309819ab 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -90,6 +90,7 @@ extern void test_raoint (void) __attribute__((__target__("raoin extern void test_amx_complex (void) __attribute__((__target__("amx-complex"))); extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16"))); extern void test_sm3 (void) __attribute__((__target__("sm3"))); +extern void test_sha512 (void) __attribute__((__target__("sha512"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -181,6 +182,7 @@ extern void test_no_raoint (void) __attribute__((__target__("no-ra extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex"))); extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16"))); extern void test_no_sm3 (void) __attribute__((__target__("no-sm3"))); +extern void test_no_sha512 (void) __attribute__((__target__("no-sha512"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/sha512-1.c b/gcc/testsuite/gcc.target/i386/sha512-1.c new file mode 100644 index 00000000000..c66e8124d6b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sha512-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msha512" } */ +/* { dg-final { scan-assembler "vsha512msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsha512msg2\[ \\t\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsha512rnds2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include + +volatile __m128i x; +volatile __m256i y; + +void extern +sha512_test (void) +{ + y = _mm256_sha512msg1_epi64(y, x); + y = _mm256_sha512msg2_epi64(y, y); + y = _mm256_sha512rnds2_epi64(y, y, x); +} diff --git a/gcc/testsuite/gcc.target/i386/sha512-check.h b/gcc/testsuite/gcc.target/i386/sha512-check.h new file mode 100644 index 00000000000..083bf3b6a1b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sha512-check.h @@ -0,0 +1,43 @@ +#include +#include "m256-check.h" + +static void sha512_test (void); + +static unsigned long long +ror64 (unsigned long long w, int n) +{ + int count = n % 64; + return ((w >> n) | (w << (64 - n))); +} + +static unsigned long long +shr64 (unsigned long long w, int n) +{ + return (w >> n); +} + +static void +__attribute__ ((noinline)) +do_test(void) +{ + sha512_test (); +} + +int +main () +{ + /* Check CPU support for SHA512. */ + if (__builtin_cpu_supports ("sha512")) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } + +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/sha512msg1-2.c b/gcc/testsuite/gcc.target/i386/sha512msg1-2.c new file mode 100644 index 00000000000..b7baff1cfb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sha512msg1-2.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msha512" } */ +/* { dg-require-effective-target sha512 } */ + +#include "sha512-check.h" +#include +#include + +static unsigned long long +s0 (unsigned long long w) +{ + return ror64 (w, 1) ^ ror64 (w, 8) ^ shr64 (w, 7); +} + +static void +compute_sha512msg1(long long* src1, long long* src2, long long* res) +{ + unsigned long long w0, w1, w2, w3, w4; + + w0 = src1[0]; + w1 = src1[1]; + w2 = src1[2]; + w3 = src1[3]; + w4 = src2[0]; + + res[0] = w0 + s0 (w1); + res[1] = w1 + s0 (w2); + res[2] = w2 + s0 (w3); + res[3] = w3 + s0 (w4); +} + +static void +sha512_test(void) +{ + union256i_q s1, res; + union128i_q s2; + long long res_ref[4]; + + s1.x = _mm256_set_epi64x (111, 222, 333, 444); + s2.x = _mm_set_epi64x (0, 555); + + res.x = _mm256_sha512msg1_epi64 (s1.x, s2.x); + + compute_sha512msg1 (s1.a, s2.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sha512msg2-2.c b/gcc/testsuite/gcc.target/i386/sha512msg2-2.c new file mode 100644 index 00000000000..e5033903f06 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sha512msg2-2.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msha512" } */ +/* { dg-require-effective-target sha512 } */ + +#include "sha512-check.h" +#include + +static unsigned long long +s1 (unsigned long long w) +{ + return ror64 (w, 19) ^ ror64 (w, 61) ^ shr64 (w, 6); +} + +static void +compute_sha512msg2 (long long* src1, long long* src2, long long* res) +{ + unsigned long long w14, w15, w16, w17, w18, w19; + + w14 = src2[2]; + w15 = src2[3]; + w16 = src1[0] + s1 (w14); + w17 = src1[1] + s1 (w15); + w18 = src1[2] + s1 (w16); + w19 = src1[3] + s1 (w17); + + res[0] = w16; + res[1] = w17; + res[2] = w18; + res[3] = w19; +} + +static void +sha512_test (void) +{ + union256i_q s1, s2, res; + long long res_ref[4]; + + s1.x = _mm256_set_epi64x (111, 222, 333, 444); + s2.x = _mm256_set_epi64x (555, 666, 0, 0); + + res.x = _mm256_sha512msg2_epi64 (s1.x, s2.x); + + compute_sha512msg2 (s1.a, s2.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c b/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c new file mode 100644 index 00000000000..3bc6a00a05b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c @@ -0,0 +1,85 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msha512" } */ +/* { dg-require-effective-target sha512 } */ + +#include "sha512-check.h" +#include +#include + +static unsigned long long +ch (unsigned long long e, unsigned long long f, unsigned long long g) +{ + return (e & f) ^ (~e & g); +} + +static unsigned long long +maj (unsigned long long a, unsigned long long b, unsigned long long c) +{ + return (a & b) ^ (a & c) ^ (b & c); +} + +static unsigned long long +s0 (unsigned long long w) +{ + return ror64 (w, 28) ^ ror64 (w, 34) ^ ror64 (w, 39); +} + +static unsigned long long +s1 (unsigned long long w) +{ + return ror64 (w, 14) ^ ror64 (w, 18) ^ ror64 (w, 41); +} + +static void +compute_sha512rnds2(long long* src0, long long* src1, long long* src2, long long* res) +{ + unsigned long long wk[2] = { src2[0], src2[1] }; + unsigned long long a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3]; + + a[0] = src1[3]; + b[0] = src1[2]; + c[0] = src0[3]; + d[0] = src0[2]; + e[0] = src1[1]; + f[0] = src1[0]; + g[0] = src0[1]; + h[0] = src0[0]; + + int i; + for (i = 0; i <= 1; i++) + { + a[i + 1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i] + + maj (a[i], b[i], c[i]) + s0 (a[i]); + b[i + 1] = a[i]; + c[i + 1] = b[i]; + d[i + 1] = c[i]; + e[i + 1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i] + d[i]; + f[i + 1] = e[i]; + g[i + 1] = f[i]; + h[i + 1] = g[i]; + } + + res[0] = f[2]; + res[1] = e[2]; + res[2] = b[2]; + res[3] = a[2]; +} + +static void +sha512_test (void) +{ + union256i_q s0, s1, res; + union128i_q s2; + long long res_ref[4]; + + s0.x = _mm256_set_epi64x (111, 222, 333, 444); + s1.x = _mm256_set_epi64x (555, 666, 777, 888); + s2.x = _mm_set_epi64x (999, 123); + + res.x = _mm256_sha512rnds2_epi64 (s0.x, s1.x, s2.x); + + compute_sha512rnds2 (s0.a, s1.a, s2.a, res_ref); + + if (check_union256i_q (res, res_ref)) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 5058be6f6e9..976541389ea 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index d30b365564a..8c314e70e31 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 7842005a98b..2b4d7bc9079 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index 7537db1ac30..d6f19b5e20a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 3fc61b50fe6..1df66b525ca 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -850,6 +850,6 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512") #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index c911a824d31..f376d835f8b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9883,6 +9883,20 @@ proc check_effective_target_sm3 { } { } "-msm3" ] } +# Return 1 if sha512 instructions can be compiled. +proc check_effective_target_sha512 { } { + return [check_no_compiler_messages sha512 object { + typedef long long __m256i __attribute__ ((__vector_size__ (32))); + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + __m256i + _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B) + { + return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A, + (__v4di) __B); + } + } "-msha512" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { From patchwork Thu Jul 13 06:03:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 119556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1616424vqm; Wed, 12 Jul 2023 23:05:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlE6d+5bzxRLt0GlY0olhXEz8b7SnaBdYfcYOZJ2P00+jtLyOVWTX9DBe00LPaYo99P6hIBV X-Received: by 2002:a05:6402:1612:b0:51d:d4dd:a0e1 with SMTP id f18-20020a056402161200b0051dd4dda0e1mr676933edv.15.1689228320212; Wed, 12 Jul 2023 23:05:20 -0700 (PDT) ARC-Seal: i=1; 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[8.43.85.97]) by mx.google.com with ESMTPS id l12-20020aa7c30c000000b0051e02815eb5si6798621edq.476.2023.07.12.23.05.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 23:05:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=SeNZgmMX; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ACA3F385B516 for ; Thu, 13 Jul 2023 06:04:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ACA3F385B516 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689228276; bh=2rblkLE+5SUk70e+B5W7bggjWd08vSIGMbeT7lQNd58=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=SeNZgmMXX6EO6qHkfHTotR7pX8CBDV7dR1kSIVvX07z2OBUYU2qN/y+TJ0xoie4rQ +sW+vAka8VoofXxQN9edSpYmsZQ0Eonv99DMhVApYWwbFweGBhSvbf8O4BbDItHBpO BniyxlSZfdnCuP6zdlSjNs+H77pllH2jAiZSyQEo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id EDF3C3857C51 for ; Thu, 13 Jul 2023 06:03:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDF3C3857C51 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="451457699" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="451457699" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:03:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="715822147" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="715822147" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga007.jf.intel.com with ESMTP; 12 Jul 2023 23:03:38 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 69ACB10079B6; Thu, 13 Jul 2023 14:03:37 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 4/4] Support Intel SM4 Date: Thu, 13 Jul 2023 14:03:35 +0800 Message-Id: <20230713060335.203711-5-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713060335.203711-1-haochen.jiang@intel.com> References: <20230713060335.203711-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771284274775747522 X-GMAIL-MSGID: 1771284274775747522 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Detech SM4. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET, OPTION_MASK_ISA2_SM4_UNSET): New. (OPTION_MASK_ISA2_AVX_UNSET): Add SM4. (ix86_handle_option): Handle -msm4. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_SM4. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for sm4. * config.gcc: Add sm4intrin.h. * config/i386/cpuid.h (bit_SM4): New. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __SM4__. * config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4). * config/i386/i386-options.cc (isa2_opts): Add -msm4. (ix86_valid_target_attribute_inner_p): Handle sm4. * config/i386/i386.opt: Add option -msm4. * config/i386/immintrin.h: Include sm4intrin.h * config/i386/sse.md (vsm4key4_): New define insn. (vsm4rnds4_): Ditto. * doc/extend.texi: Document sm4. * doc/invoke.texi: Document -msm4. * doc/sourcebuild.texi: Document target sm4. * config/i386/sm4intrin.h: New file. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Add -msm4. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/sse-12.c: Add -msm4. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Add sm4. * gcc.target/i386/sse-23.c: Ditto. * lib/target-supports.exp (check_effective_target_sm4): New. * gcc.target/i386/sm4-1.c: New test. * gcc.target/i386/sm4-check.h: Ditto. * gcc.target/i386/sm4key4-2.c: Ditto. * gcc.target/i386/sm4rnds4-2.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 2 + gcc/common/config/i386/i386-common.cc | 20 +- gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-builtin.def | 6 + gcc/config/i386/i386-c.cc | 2 + gcc/config/i386/i386-isa.def | 1 + gcc/config/i386/i386-options.cc | 4 +- gcc/config/i386/i386.opt | 5 + gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sm4intrin.h | 70 +++++++ gcc/config/i386/sse.md | 26 +++ gcc/doc/extend.texi | 5 + gcc/doc/invoke.texi | 9 +- gcc/doc/sourcebuild.texi | 3 + gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/sm4-1.c | 20 ++ gcc/testsuite/gcc.target/i386/sm4-check.h | 183 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/sm4key4-2.c | 14 ++ gcc/testsuite/gcc.target/i386/sm4rnds4-2.c | 14 ++ gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 4 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- gcc/testsuite/lib/target-supports.exp | 14 ++ 30 files changed, 409 insertions(+), 14 deletions(-) create mode 100644 gcc/config/i386/sm4intrin.h create mode 100644 gcc/testsuite/gcc.target/i386/sm4-1.c create mode 100644 gcc/testsuite/gcc.target/i386/sm4-check.h create mode 100644 gcc/testsuite/gcc.target/i386/sm4key4-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sm4rnds4-2.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 0cfde3ebccd..f9434f038ea 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -881,6 +881,8 @@ get_available_features (struct __processor_model *cpu_model, set_feature (FEATURE_SM3); if (eax & bit_SHA512) set_feature (FEATURE_SHA512); + if (eax & bit_SM4) + set_feature (FEATURE_SM4); } if (avx512_usable) { diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 97c3cdfe5e1..610cabe52c1 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -122,6 +122,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 +#define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -307,6 +308,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16 #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 +#define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -356,7 +358,8 @@ along with GCC; see the file COPYING3. If not see OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET \ (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \ - | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET) + | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \ + | OPTION_MASK_ISA2_SM4_UNSET) #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET @@ -1323,6 +1326,21 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_msm4: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index a6e34d14f8e..be04d85c9d5 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -258,6 +258,7 @@ enum processor_features FEATURE_AVXVNNIINT16, FEATURE_SM3, FEATURE_SHA512, + FEATURE_SM4, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 250dc87764f..2297903a45e 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -190,4 +190,5 @@ ISA_NAMES_TABLE_START P_NONE, "-mavxvnniint16") ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512") + ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index 4e753ba7c64..305e859880f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -436,7 +436,7 @@ i[34567]86-*-* | x86_64-*-*) avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h - sm3intrin.h sha512intrin.h" + sm3intrin.h sha512intrin.h sm4intrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index f9103f1b1c9..03fd6fc9478 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -134,6 +134,7 @@ /* %eax */ #define bit_SHA512 (1 << 0) #define bit_SM3 (1 << 1) +#define bit_SM4 (1 << 2) #define bit_RAOINT (1 << 3) #define bit_AVXVNNI (1 << 4) #define bit_AVX512BF16 (1 << 5) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index b9e2bad8522..8738b3b6a8a 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1660,6 +1660,12 @@ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI) BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT) +/* SM4 */ +BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v4si, "__builtin_ia32_vsm4key4128", IX86_BUILTIN_VSM4KEY4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v8si, "__builtin_ia32_vsm4key4256", IX86_BUILTIN_VSM4KEY4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v4si, "__builtin_ia32_vsm4rnds4128", IX86_BUILTIN_VSM4RNDS4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v8si, "__builtin_ia32_vsm4rnds4256", IX86_BUILTIN_VSM4RNDS4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI) + /* SHA512 */ BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg1, "__builtin_ia32_vsha512msg1", IX86_BUILTIN_VSHA512MSG1, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI) BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg2, "__builtin_ia32_vsha512msg2", IX86_BUILTIN_VSHA512MSG2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index c6311f12cf9..0adec145600 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -683,6 +683,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__SM3__"); if (isa_flag2 & OPTION_MASK_ISA2_SHA512) def_or_undef (parse_in, "__SHA512__"); + if (isa_flag2 & OPTION_MASK_ISA2_SM4) + def_or_undef (parse_in, "__SM4__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 28f221753a9..aeafcf870ac 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -120,3 +120,4 @@ DEF_PTA(AMX_COMPLEX) DEF_PTA(AVXVNNIINT16) DEF_PTA(SM3) DEF_PTA(SHA512) +DEF_PTA(SM4) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index d79ab01bd79..347ed2d210a 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -242,7 +242,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }, { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 }, { "-msm3", OPTION_MASK_ISA2_SM3 }, - { "-msha512", OPTION_MASK_ISA2_SHA512 } + { "-msha512", OPTION_MASK_ISA2_SHA512 }, + { "-msm4", OPTION_MASK_ISA2_SM4 } }; static struct ix86_target_opts isa_opts[] = { @@ -1097,6 +1098,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16), IX86_ATTR_ISA ("sm3", OPT_msm3), IX86_ATTR_ISA ("sha512", OPT_msha512), + IX86_ATTR_ISA ("sm4", OPT_msm4), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index cf9dbca58b3..db9956885e2 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1298,3 +1298,8 @@ msha512 Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and SHA512 built-in functions and code generation. + +msm4 +Target Mask(ISA2_SM4) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and +SM4 built-in functions and code generation. diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index 6f2bcef6a8a..ea14354efbc 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -112,6 +112,8 @@ #include +#include + #include #include diff --git a/gcc/config/i386/sm4intrin.h b/gcc/config/i386/sm4intrin.h new file mode 100644 index 00000000000..f58a782bfdc --- /dev/null +++ b/gcc/config/i386/sm4intrin.h @@ -0,0 +1,70 @@ +/* Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _SM4INTRIN_H_INCLUDED +#define _SM4INTRIN_H_INCLUDED + +#ifndef __SM4__ +#pragma GCC push_options +#pragma GCC target("sm4") +#define __DISABLE_SM4__ +#endif /* __SM4__ */ + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_sm4key4_epi32 (__m128i __A, __m128i __B) +{ + return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A, (__v4si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_sm4key4_epi32 (__m256i __A, __m256i __B) +{ + return (__m256i) __builtin_ia32_vsm4key4256 ((__v8si) __A, (__v8si) __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_sm4rnds4_epi32 (__m128i __A, __m128i __B) +{ + return (__m128i) __builtin_ia32_vsm4rnds4128 ((__v4si) __A, (__v4si) __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_sm4rnds4_epi32 (__m256i __A, __m256i __B) +{ + return (__m256i) __builtin_ia32_vsm4rnds4256 ((__v8si) __A, (__v8si) __B); +} + +#ifdef __DISABLE_SM4__ +#undef __DISABLE_SM4__ +#pragma GCC pop_options +#endif /* __DISABLE_SM4__ */ + +#endif /* _SM4INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e16b2b5a6c4..7471932b27e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -223,6 +223,10 @@ UNSPEC_SHA512MSG2 UNSPEC_SHA512RNDS2 + ;; For SM4 support + UNSPEC_SM4KEY4 + UNSPEC_SM4RNDS4 + ]) (define_c_enum "unspecv" [ @@ -28680,6 +28684,28 @@ [(set_attr "type" "sselog1") (set_attr "mode" "OI")]) +(define_insn "vsm4key4_" + [(set (match_operand:VI4_AVX 0 "register_operand" "=x") + (unspec:VI4_AVX + [(match_operand:VI4_AVX 1 "register_operand" "x") + (match_operand:VI4_AVX 2 "vector_operand" "xBm")] + UNSPEC_SM4KEY4))] + "TARGET_SM4" + "vsm4key4\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "other") + (set_attr "mode" "")]) + +(define_insn "vsm4rnds4_" + [(set (match_operand:VI4_AVX 0 "register_operand" "=x") + (unspec:VI4_AVX + [(match_operand:VI4_AVX 1 "register_operand" "x") + (match_operand:VI4_AVX 2 "vector_operand" "xBm")] + UNSPEC_SM4RNDS4))] + "TARGET_SM4" + "vsm4rnds4\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "other") + (set_attr "mode" "")]) + (define_insn_and_split "avx512f__" [(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m") (vec_concat:AVX512MODE2P diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 5250990050b..8c83c58a30a 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7178,6 +7178,11 @@ Enable/disable the generation of the SM3 instructions. @itemx no-sha512 Enable/disable the generation of the SHA512 instructions. +@cindex @code{target("sm4")} function attribute, x86 +@item sm4 +@itemx no-sm4 +Enable/disable the generation of the SM4 instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 433ccf35505..dd28320185d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options. -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 --mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 +-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -33561,6 +33561,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex msha512 @itemx -msha512 +@need 200 +@opindex msm4 +@itemx -msm4 These switches enable the use of instructions in the MMX, SSE, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, @@ -33571,8 +33574,8 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, -AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512 or CLDEMOTE extended instruction sets. -Each has a corresponding @option{-mno-} option to disable use of these +AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4 or CLDEMOTE extended instruction +sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 54a062db3fe..e5d15d67253 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2595,6 +2595,9 @@ Target supports the execution of @code{sha512} instructions. @item sm3 Target supports the execution of @code{sm3} instructions. +@item sm4 +Target supports the execution of @code{sm4} instructions. + @item sqrt_insn Target has a square root instruction that the compiler can generate. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 985f14abcbc..7d68967488d 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 274b0e6256f..9b775c33ab4 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index eb9309819ab..577bfc75edf 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -91,6 +91,7 @@ extern void test_amx_complex (void) __attribute__((__target__("amx-complex"))); extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16"))); extern void test_sm3 (void) __attribute__((__target__("sm3"))); extern void test_sha512 (void) __attribute__((__target__("sha512"))); +extern void test_sm4 (void) __attribute__((__target__("sm4"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -183,6 +184,7 @@ extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-comple extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16"))); extern void test_no_sm3 (void) __attribute__((__target__("no-sm3"))); extern void test_no_sha512 (void) __attribute__((__target__("no-sha512"))); +extern void test_no_sm4 (void) __attribute__((__target__("no-sm4"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/sm4-1.c b/gcc/testsuite/gcc.target/i386/sm4-1.c new file mode 100644 index 00000000000..2d3d6c6aab8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm4-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msm4" } */ +/* { dg-final { scan-assembler "vsm4key4\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsm4key4\[ \\t\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsm4rnds4\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */ +/* { dg-final { scan-assembler "vsm4rnds4\[ \\t\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */ + +#include + +volatile __m128i a, b, c; +volatile __m256i d, e, f; + +void extern +sm4_test (void) +{ + a = _mm_sm4key4_epi32 (b, c); + d = _mm256_sm4key4_epi32 (e, f); + a = _mm_sm4rnds4_epi32 (b, c); + d = _mm256_sm4rnds4_epi32 (e, f); +} diff --git a/gcc/testsuite/gcc.target/i386/sm4-check.h b/gcc/testsuite/gcc.target/i386/sm4-check.h new file mode 100644 index 00000000000..435fcf2b17d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm4-check.h @@ -0,0 +1,183 @@ +#include +#include "m256-check.h" + +static void sm4_test (void); + +typedef union +{ + unsigned int x; + unsigned char a[4]; +} union32ui_ub; + +unsigned char sbox[256] = { +0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, +0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05, +0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, +0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, +0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, +0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, +0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, +0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, +0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, +0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, +0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, +0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, +0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, +0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, +0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, +0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, +0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, +0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, +0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, +0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3, +0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, +0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, +0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, +0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, +0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, +0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, +0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, +0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, +0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, +0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, +0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, +0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 +}; + +static unsigned +rol32 (unsigned w, int n) +{ + int count = n % 32; + return ((w << count) | (w >> (32 - count))); +} + +static unsigned char +sbox_byte (unsigned w, int i) +{ + union32ui_ub tmp; + tmp.x = w; + return sbox[tmp.a[i]]; +} + +static unsigned +lower_t (unsigned w) +{ + union32ui_ub tmp; + tmp.a[0] = sbox_byte (w, 0); + tmp.a[1] = sbox_byte (w, 1); + tmp.a[2] = sbox_byte (w, 2); + tmp.a[3] = sbox_byte (w, 3); + return tmp.x; +} + +static unsigned +l_key (unsigned w) +{ + return w ^ rol32 (w, 13) ^ rol32 (w, 23); +} + +static unsigned +l_rnds (unsigned w) +{ + unsigned tmp = w; + tmp = tmp ^ rol32 (w, 2); + tmp = tmp ^ rol32 (w, 10); + tmp = tmp ^ rol32 (w, 18); + tmp = tmp ^ rol32 (w, 24); + return tmp; +} + +#define SM4_FUNC(name) \ +static unsigned \ +t_##name (unsigned w) \ +{ \ + return l_##name (lower_t (w)); \ +} \ + \ +static unsigned \ +f_##name (unsigned x0, unsigned x1, unsigned x2, unsigned x3, unsigned k) \ +{ \ + return x0 ^ t_##name (x1 ^ x2 ^ x3 ^ k); \ +} \ + \ +static void \ +compute_sm4##name##4 (int *dst, int *src1, int *src2, int vl) \ +{ \ + unsigned c[4], p[4]; \ + \ + int kl = vl / 128; \ + int i; \ + \ + for (i = 0; i < kl; i++) \ + { \ + p[0] = src1[4 * i]; \ + p[1] = src1[4 * i + 1]; \ + p[2] = src1[4 * i + 2]; \ + p[3] = src1[4 * i + 3]; \ + \ + c[0] = f_##name (p[0], p[1], p[2], p[3], src2[4 * i]); \ + c[1] = f_##name (p[1], p[2], p[3], c[0], src2[4 * i + 1]); \ + c[2] = f_##name (p[2], p[3], c[0], c[1], src2[4 * i + 2]); \ + c[3] = f_##name (p[3], c[0], c[1], c[2], src2[4 * i + 3]); \ + \ + dst[4 * i] = c[0]; \ + dst[4 * i + 1] = c[1]; \ + dst[4 * i + 2] = c[2]; \ + dst[4 * i + 3] = c[3]; \ + } \ +} + +#define SM4_AVX_SIMULATE(name) \ + union128i_d src1, src2, res1; \ + int dst1[4] = {0, 0, 0, 0}; \ + \ + src1.x = _mm_set_epi32 (111, 222, 333, 444); \ + src2.x = _mm_set_epi32 (555, 666, 777, 888); \ + res1.x = _mm_set_epi32 (0, 0, 0, 0); \ + \ + res1.x = _mm_sm4##name##4_epi32 (src1.x, src2.x); \ + \ + compute_sm4##name##4 (dst1, src1.a, src2.a, 128); \ + \ + if (check_union128i_d (res1, dst1)) \ + abort (); \ + \ + union256i_d src3, src4, res2; \ + int dst2[8] = {0, 0, 0, 0, 0, 0, 0, 0}; \ + \ + src3.x = _mm256_set_epi32 (111, 222, 333, 444, 555, 666, 777, 888); \ + src4.x = _mm256_set_epi32 (999, 123, 456, 789, 135, 792, 468, 147); \ + res2.x = _mm256_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0); \ + \ + res2.x = _mm256_sm4##name##4_epi32 (src3.x, src4.x); \ + \ + compute_sm4##name##4 (dst2, src3.a, src4.a, 256); \ + \ + if (check_union256i_d (res2, dst2)) \ + abort (); + +static void +__attribute__ ((noinline)) +do_test (void) +{ + sm4_test (); +} + +int +main () +{ + /* Check CPU support for SM4. */ + if (__builtin_cpu_supports ("sm4")) + { + do_test (); +#ifdef DEBUG + printf ("PASSED\n"); +#endif + return 0; + } + +#ifdef DEBUG + printf ("SKIPPED\n"); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/sm4key4-2.c b/gcc/testsuite/gcc.target/i386/sm4key4-2.c new file mode 100644 index 00000000000..a8bec560214 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm4key4-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msm4" } */ +/* { dg-require-effective-target sm4 } */ + +#include "sm4-check.h" + +char key; +SM4_FUNC (key); + +static void +sm4_test (void) +{ + SM4_AVX_SIMULATE (key); +} diff --git a/gcc/testsuite/gcc.target/i386/sm4rnds4-2.c b/gcc/testsuite/gcc.target/i386/sm4rnds4-2.c new file mode 100644 index 00000000000..0860d0dd412 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sm4rnds4-2.c @@ -0,0 +1,14 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -msm4" } */ +/* { dg-require-effective-target sm4 } */ + +#include "sm4-check.h" + +char rnds; +SM4_FUNC (rnds); + +static void +sm4_test (void) +{ + SM4_AVX_SIMULATE (rnds); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 976541389ea..a553a5202d1 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 8c314e70e31..946182f0e76 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 2b4d7bc9079..0d07aadc7f8 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index d6f19b5e20a..e6681f7dd12 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 1df66b525ca..92b1c467d95 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -850,6 +850,6 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") #include diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f376d835f8b..8ea0d9feb1c 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9897,6 +9897,20 @@ proc check_effective_target_sha512 { } { } "-msha512" ] } +# Return 1 if sm4 instructions can be compiled. +proc check_effective_target_sm4 { } { + return [check_no_compiler_messages sm4 object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + __m128i + _mm_sm4key4_epi32 (__m128i __A, __m128i __B) + { + return (__m128i) __builtin_ia32_vsm4key4128 ((__v4si) __A, + (__v4si) __B); + } + } "-msm4" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object {