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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v1: Add ipq5332 to interrupts sections --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index ae24dac..9447b54 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - qcom,ipq4019-dwc3 + - qcom,ipq5332-dwc3 - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 - qcom,ipq8074-dwc3 @@ -246,6 +247,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-dwc3 - qcom,msm8994-dwc3 - qcom,qcs404-dwc3 then: @@ -410,6 +412,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-dwc3 - qcom,sdm660-dwc3 then: properties: From patchwork Wed Jul 12 11:38:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 119141 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1108947vqm; Wed, 12 Jul 2023 05:21:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlFl8dP2kF37odIJoh9KKnZrVtOCTms+xNrqQECZWZN6MToMHkzymvoPaVsa/7K4OBTH3LUX X-Received: by 2002:a17:903:2447:b0:1b8:a70d:412a with SMTP id l7-20020a170903244700b001b8a70d412amr18783676pls.67.1689164498702; Wed, 12 Jul 2023 05:21:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689164498; cv=none; d=google.com; s=arc-20160816; b=Wr5CJxnSxcRysOBgQvwXUD+YmOZRIP71zURN0rzuqYWa10hK0pLxH2GrMpRSj65Ifj HB2xJdLPl0R6Gnp3JDyWf1RL63w/aSr9iDSGe1chS4+7flmegKsR/ZcB5wM0KPGYLx0w E0YqBf5kMPrJk3/TFMmBk+TbhLBR4pKzleE0LymvlaqoprAwoO/sVX4GG0qMRmfwXdsz mQsim4PNWBSkypoBz11qMSrbkj9Ij66FJzIT4OuK+np32hQGGMz20r/vGAjx1vIEdz87 f4OBHiMYqlaShF7kkiZ/wwqX5sh+aLVxh1Rk6HQQthcl64O4HrgK0owSxKCVTyr8EHL3 cI2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=S8kgrjTTL4lWCAvjC5av2SNwL0eEAEeHJCs6sq7OfSg=; fh=5k38RZtG+6HomFK06DPIqaSvDTnJ/15hPHIK1s7dPN4=; b=xL1LZKXg589PEpcLg7u7tRN9bxHy3zuX7A6D+EBjE5IJX5YZULhyU5N3NRE41v6d8i WQqIouHPI8SYDrVYYr+FQqJY4S5NYJAz2WP4ESkHFSHC95vKu2j2/6HIbPVaD4BCuRFZ NyccXpl/5rwI4liIdL2EH8jtR2BtF//bKWSoN3Szc+1tSnsK8DOJVIOVYVrGPbKAQGKS ojB/NN9ArtOAjraCGhAfVmMYa9nq/Qflm5qNoIYyJG76sr0dLK6mMH0TjLollPgAYjHo /u304xA9RmcP4JloqV8fi+wVwCGQJtKreNK3AUu+V6/ODlBDFyPRLu+8k6Dhls829FFc lgEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YS5bP+xB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Sricharan Ramabadhran Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- v4: Move M31 URL to description Remove maxItems and relevant content from clock-names Change node name to generic name 'make dt_binding_check DT_SCHEMA_FILES=qcom' passed v3: Incorporate review comments. Will bring in ipq5018 compatible string while posting ipq5018 usb patchset. v1: Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml Drop default binding "m31,usb-hsphy" Add clock Remove 'oneOf' from compatible Remove 'qscratch' region from register space as it is not needed Remove reset-names Fix the example definition --- .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml new file mode 100644 index 0000000..eea90ff --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: M31 USB PHY + +maintainers: + - Sricharan Ramabadhran + - Varadarajan Narayanan + +description: + USB M31 PHY (https://www.m31tech.com) found in Qualcomm + IPQ5018, IPQ5332 SoCs. + +properties: + compatible: + enum: + - qcom,ipq5332-usb-hsphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: cfg_ahb + + resets: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + usbphy0: usb-phy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "cfg_ahb"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + }; From patchwork Wed Jul 12 11:38:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 119116 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1094397vqm; Wed, 12 Jul 2023 05:00:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlGabcxvz9r0n32SYeP9BXfDGgLOxGfJ7msvo+0eXY6D8v9wdC3J41RG8HhFjN25F23hdKT8 X-Received: by 2002:a05:6512:2398:b0:4f1:4cdc:ec03 with SMTP id c24-20020a056512239800b004f14cdcec03mr18663311lfv.18.1689163222658; Wed, 12 Jul 2023 05:00:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689163222; cv=none; d=google.com; s=arc-20160816; b=BxEsL2g0YuL2Um/PR8vNKmbj7R6EmgTPz3hVcsX/93xu1Fr2g3Wkuz1z8rteqYQuOz lTTNTk53n0EA4O8YDq4rLspkqbjkS54FU7VhpNaL2dL72EFcBJH8sWvh/wmkTcEfj972 gILmu0IEohLDZVfLFN6uIazE9Ep/9rl4Xna96g5+jE096PhgqrkYyeT15ObKPAhdBg1v sB9TF6DhM2Jrm/U7CZvfhveBkXk0wtZ3hjesoV5l0eQ3YvyEqDaI+G0d8vubN4qrH2e+ gjsv+4l3sK+AeM2lSkDcrAuAl5mVjeWBV4Ass1hVAQta99nHDb+b1YPuAKM4wayXc5Sx yRMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=9W2CzbsgCDcZp7mvX+M2W0SEHEUd5pqL2CuMumFS0/0=; fh=5k38RZtG+6HomFK06DPIqaSvDTnJ/15hPHIK1s7dPN4=; b=ma3xR28cK0xgeY/no/OlYOVW1BfAvsvVw+ep4r1HnWo9tUzEXbp6ScPkAAAXjXNXU/ aL9CwDMct4YCMGHfFa4jRuPaNli3EOlBzv2afHkz12Twj5MT6rb6Jqf9x6LRjcrLZ3pQ l3EE4lwkudqgccat+h0o+r6IJXqlETXQE5LtUNveCWTwKu1T8KwRlemayrbYHZqUpsaP ymmkbQDayl48gRn16b4ElpXqcylo1TP3YYjpEnTfw9SBpZinQHZI2XTdIEcA5dhFHZYV ReadxUoWv6V55PKOX/joDWyAEg/NjwDOBOjQqe+F3kthr7aLn3RAvCGLYw1rMK5ukOwP TI8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="pV/5e/Ym"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan --- v4: Remove unused enum Error handling for devm_clk_get v1: Combine driver, makefile and kconfig into 1 patch Remove 'qscratch' region and its usage. The controller driver takes care of those settings Use compatible/data to handle ipq5332 init Drop the default case Get resources by index instead of name as there is only one resource Add clock Fix review comments in the driver --- drivers/phy/qualcomm/Kconfig | 11 ++ drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-m31.c | 256 ++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-m31.c diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 97ca595..76be191 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -197,3 +197,14 @@ config PHY_QCOM_SGMII_ETH help Enable this to support the internal SerDes/SGMII PHY on various Qualcomm chipsets. + +config PHY_QCOM_M31_USB + tristate "Qualcomm M31 HS PHY driver support" + depends on (USB || USB_GADGET) && ARCH_QCOM + select USB_PHY + help + Enable this to support M31 HS PHY transceivers on Qualcomm chips + with DWC3 USB core. It handles PHY initialization, clock + management required after resetting the hardware and power + management. This driver is required even for peripheral only or + host only mode configurations. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index b030858..0b5dd66 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2)+= phy-qcom-snps-femto-v2.o obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o obj-$(CONFIG_PHY_QCOM_SGMII_ETH) += phy-qcom-sgmii-eth.o +obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c new file mode 100644 index 0000000..fd568ef --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-m31.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2014-2016, 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB2PHY_PORT_UTMI_CTRL1 0x40 + +#define USB2PHY_PORT_UTMI_CTRL2 0x44 + #define UTMI_ULPI_SEL BIT(7) + #define UTMI_TEST_MUX_SEL BIT(6) + +#define HS_PHY_CTRL_REG 0x10 + #define UTMI_OTG_VBUS_VALID BIT(20) + #define SW_SESSVLD_SEL BIT(28) + +#define USB_PHY_UTMI_CTRL0 0x3c + +#define USB_PHY_UTMI_CTRL5 0x50 + #define POR_EN BIT(1) + #define ATERESET ~BIT(0) + +#define USB_PHY_HS_PHY_CTRL_COMMON0 0x54 + #define COMMONONN BIT(7) + #define FSEL BIT(4) + #define RETENABLEN BIT(3) + #define FREQ_24MHZ (5 << 4) + +#define USB_PHY_HS_PHY_CTRL2 0x64 + #define USB2_SUSPEND_N_SEL BIT(3) + #define USB2_SUSPEND_N BIT(2) + #define USB2_UTMI_CLK_EN BIT(1) + +#define USB_PHY_CFG0 0x94 + #define UTMI_PHY_OVERRIDE_EN BIT(1) + +#define USB_PHY_REFCLK_CTRL 0xa0 + #define CLKCORE BIT(1) + +#define USB2PHY_PORT_POWERDOWN 0xa4 + #define POWER_UP BIT(0) + #define POWER_DOWN 0 + +#define USB_PHY_FSEL_SEL 0xb8 + #define FREQ_SEL BIT(0) + +#define USB2PHY_USB_PHY_M31_XCFGI_1 0xbc + #define USB2_0_TX_ENABLE BIT(2) + +#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8 + #define HSTX_SLEW_RATE_565PS GENMASK(1, 0) + #define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3) + #define ODT_VALUE_38_02_OHM GENMASK(7, 6) + +#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc + #define ODT_VALUE_45_02_OHM BIT(2) + #define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0) + +#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4 + #define XCFG_COARSE_TUNE_NUM BIT(1) + #define XCFG_FINE_TUNE_NUM BIT(3) + +struct m31_phy_regs { + u32 off; + u32 val; + u32 delay; +}; + +struct m31_priv_data { + bool ulpi_mode; + const struct m31_phy_regs *regs; +}; + +#define M31_REG(__o, __v, __d) \ + { .off = __o, .val = __v, .delay = __d } + +#define M31_REG_INVALID 0xffffffffu + +struct m31_phy_regs m31_ipq5332_regs[] = { + M31_REG(USB_PHY_CFG0, UTMI_PHY_OVERRIDE_EN, 0), + M31_REG(USB_PHY_UTMI_CTRL5, POR_EN, 15), + M31_REG(USB_PHY_FSEL_SEL, FREQ_SEL, 0), + M31_REG(USB_PHY_HS_PHY_CTRL_COMMON0, + COMMONONN | FREQ_24MHZ | RETENABLEN, 0), + M31_REG(USB_PHY_UTMI_CTRL5, POR_EN & ATERESET, 0), + M31_REG(USB_PHY_HS_PHY_CTRL2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0), + M31_REG(USB2PHY_USB_PHY_M31_XCFGI_11, + XCFG_COARSE_TUNE_NUM | XCFG_FINE_TUNE_NUM, 0), + M31_REG(USB2PHY_USB_PHY_M31_XCFGI_4, + HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | + ODT_VALUE_38_02_OHM, 0), + M31_REG(USB2PHY_USB_PHY_M31_XCFGI_1, USB2_0_TX_ENABLE, 0), + M31_REG(USB2PHY_USB_PHY_M31_XCFGI_5, + ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA, 4), + M31_REG(USB_PHY_UTMI_CTRL5, 0x0, 0), + M31_REG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N | USB2_UTMI_CLK_EN, 0), + M31_REG(M31_REG_INVALID, 0, 0), +}; + +struct m31usb_phy { + struct usb_phy phy; + void __iomem *base; + const struct m31_phy_regs *regs; + + struct clk *cfg_ahb_clk; + struct reset_control *phy_reset; + + bool cable_connected; + bool suspended; + bool ulpi_mode; +}; + +static void m31usb_phy_enable_clock(struct m31usb_phy *qphy) +{ + const struct m31_phy_regs *regs = qphy->regs; + + for (; regs->off != M31_REG_INVALID; regs++) { + writel(regs->val, qphy->base + regs->off); + if (regs->delay) + udelay(regs->delay); + } +} + +static int m31usb_phy_init(struct usb_phy *phy) +{ + int ret; + struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy); + + ret = clk_prepare_enable(qphy->cfg_ahb_clk); + if (ret) { + dev_err(phy->dev, "failed to enable cfg ahb clock, %d\n", ret); + return ret; + } + + /* Perform phy reset */ + reset_control_assert(qphy->phy_reset); + udelay(5); + reset_control_deassert(qphy->phy_reset); + + /* configure for ULPI mode if requested */ + if (qphy->ulpi_mode) + writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2); + + /* Enable the PHY */ + writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN); + + /* Make sure above write completed */ + wmb(); + + /* Turn on phy ref clock */ + m31usb_phy_enable_clock(qphy); + + return 0; +} + +static void m31usb_phy_shutdown(struct usb_phy *phy) +{ + struct m31usb_phy *qphy = container_of(phy, struct m31usb_phy, phy); + + /* Disable the PHY */ + writel_relaxed(POWER_DOWN, qphy->base + USB2PHY_PORT_POWERDOWN); + /* Make sure above write completed */ + wmb(); + + clk_disable_unprepare(qphy->cfg_ahb_clk); +} + +static int m31usb_phy_probe(struct platform_device *pdev) +{ + const struct m31_priv_data *data; + struct device *dev = &pdev->dev; + struct m31usb_phy *qphy; + int ret; + + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); + if (!qphy) + return -ENOMEM; + + qphy->phy.dev = dev; + + qphy->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qphy->base)) + return PTR_ERR(qphy->base); + + qphy->phy_reset = devm_reset_control_get_exclusive_by_index(dev, 0); + if (IS_ERR(qphy->phy_reset)) + return PTR_ERR(qphy->phy_reset); + + qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); + if (IS_ERR(qphy->cfg_ahb_clk)) { + ret = PTR_ERR(qphy->cfg_ahb_clk); + dev_err(dev, "failed to get cfg_ahb clock, %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, qphy); + + data = of_device_get_match_data(dev); + qphy->regs = data->regs; + qphy->ulpi_mode = data->ulpi_mode; + + qphy->phy.label = "m31-usb-phy"; + qphy->phy.init = m31usb_phy_init; + qphy->phy.shutdown = m31usb_phy_shutdown; + qphy->phy.type = USB_PHY_TYPE_USB2; + + ret = usb_add_phy_dev(&qphy->phy); + + return ret; +} + +static void m31usb_phy_remove(struct platform_device *pdev) +{ + struct m31usb_phy *qphy = platform_get_drvdata(pdev); + + usb_remove_phy(&qphy->phy); +} + +static const struct m31_priv_data m31_ipq5332_data = { + .ulpi_mode = false, + .regs = m31_ipq5332_regs, +}; + +static const struct of_device_id m31usb_phy_id_table[] = { + { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, m31usb_phy_id_table); + +static struct platform_driver m31usb_phy_driver = { + .probe = m31usb_phy_probe, + .remove_new = m31usb_phy_remove, + .driver = { + .name = "qcom-m31usb-phy", + .of_match_table = m31usb_phy_id_table, + }, +}; + +module_platform_driver(m31usb_phy_driver); + +MODULE_DESCRIPTION("USB2 Qualcomm M31 HSPHY driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Jul 12 11:38:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 119114 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1094235vqm; Wed, 12 Jul 2023 05:00:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlHTKyFnnczEYGwWMlZooNRSH1hvk49/6fIwWHyY3ejFQBZvR/8gSV1CKCRxNxKpYRfTfb3s X-Received: by 2002:a05:6512:39cf:b0:4f9:6256:2a7e with SMTP id k15-20020a05651239cf00b004f962562a7emr18094660lfu.31.1689163209259; Wed, 12 Jul 2023 05:00:09 -0700 (PDT) ARC-Seal: i=1; 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Signed-off-by: Varadarajan Narayanan --- v4: Change node name Remove blank line 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed v1: Rename phy node Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy Remove 'qscratch' from phy node Fix alignment and upper-case hex no.s Add clock definition for the phy Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() in dwc3/core.c takes the frequency from ref clock and calculates fladj as appropriate. --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db..8118356 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -405,6 +405,59 @@ status = "disabled"; }; }; + + usbphy0: usb-phy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "cfg_ahb"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + + status = "disabled"; + }; + + usb2: usb2@8a00000 { + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + + interrupts = ; + interrupt-names = "hs_phy_irq"; + + clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "core", + "iface", + "sleep", + "mock_utmi"; + + resets = <&gcc GCC_USB_BCR>; + + qcom,select-utmi-as-pipe-clk; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + usb2_0_dwc: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x08a00000 0xe000>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = ; + usb-phy = <&usbphy0>; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; }; timer { From patchwork Wed Jul 12 11:38:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 119128 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1103681vqm; Wed, 12 Jul 2023 05:13:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlExHGgrIhjrhBjjF/etiJ7Y0kW7fHbsSfA0RGz69xHpDJ9RHG8/dCicoQfnHpnr0zWybgkp X-Received: by 2002:a17:903:2449:b0:1b8:9b1d:d7f1 with SMTP id l9-20020a170903244900b001b89b1dd7f1mr16551209pls.47.1689163981901; Wed, 12 Jul 2023 05:13:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689163981; cv=none; d=google.com; s=arc-20160816; b=hf7dxOIe1Fd/+WWw3q1mR2JdVxtch+V/NSAa2ET/mMEvkm8XsrH9A9PNsdzBfNMb4B aZsIhZhBak+bg9kLg91HqbUL810mqjnWMMaZ5ZFNkgcGycZXHCrzelkip9XxU3V69j6e 3aJllGL9lv4nLv0vaIkbAWspFFGd3oNKEC6X3MzsKTZgXKb2doWErOzyvh7AojHl3t6j BEOPpzUcOj8dS3TCo7/gfhlo57bMKXCr8MBC4JuugBXNlSI+VR7gVw0MVFYEhZYHsBnR esMfw0Ndln2bmNscZQbOZ5lqGSjmFd7dKtx/GCcew369+xHBSMJrU4CAQX0iNM/xiDur MfXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=naxU+m/X6BWT4Ppq8p46MPOyw5VGSp+2XgsgQpgrn5w=; fh=5k38RZtG+6HomFK06DPIqaSvDTnJ/15hPHIK1s7dPN4=; b=jpdA+OD3sWBR8BajoLkHFGC1ugOmOYoX9ZvdttDVYQeQJcl5Y+ekvGX6hTI5M5eT7b 1oLOm0I0CcLBs3TFBpqUbNjdljHGzkg7p893eGOVJX9FAUQc0/1YQwqnnpYDA4Uwv2vN K+Osq0DnQ7Px1jeKuTNVU0ICP2rJuJ6g+ZaJBwAw9AaEFbLULYZLgcC64YPW+HTWgM7j /jleKlyu+TNt9zSjmUO7cJx2lx1zZVtFabTJ5QdCWnFdCLDB4SItK1c81OkcFHTke2Ea 2Vl6zamjEYiSjlUc8Ke7LS6krtQKOHGOsxpzMszEyCPWCK0nBC3hXa19szrwkCzntjYp prAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MIt+fkCv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan --- v1: Enable usb-phy node --- arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index f96b0c8..f5dea16 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -79,3 +79,15 @@ bias-pull-up; }; }; + +&usbphy0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_0_dwc { + dr_mode = "host"; +}; From patchwork Wed Jul 12 11:38:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 119115 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp1094314vqm; Wed, 12 Jul 2023 05:00:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlEyEZH75p/IhioWchg+GX+mDUCqEUwX/umrr9+FU/21DmCSYJPUkhES7DggDbu0CRudcOM5 X-Received: by 2002:a17:906:20d8:b0:993:eef2:5d56 with SMTP id c24-20020a17090620d800b00993eef25d56mr14594992ejc.0.1689163216073; Wed, 12 Jul 2023 05:00:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689163216; cv=none; d=google.com; s=arc-20160816; b=Ey9WlEGPyTppFXq1HUptKfrw77i3yEwS3GI2uJ3/YBMcwn3bvWbn0P84/rGbDTqU4H D0zGrxraGLXPEF5PBIIYdUCKVW1U4deAl3PMlAwtkm1L2EdzIQFT9NWeFGfiF/j0AKwU ewezR6gjHE6zZYmXGN8hITu6KKm1RCsu8mZCdqJe3R9w8jMF2zL+pgrwr+DgHCK/Hg7+ mT2OUPeTLAiAIHqhfzfPlH9kbJ0z9QCPRk8V9EfNQN9mzbTsMtJSIQaXVJPUzEoQFjPr vfdGZLNiJCOIdoxuVlBroZJU8sQc7gS/B9O8y+0765BvHKXccpe5ClB2kcOCEUFd9lAT hjYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=2T4fWhSe+mQVomdVoARjDRyJ2B1YT3HrKfkKxJCRtKw=; fh=5k38RZtG+6HomFK06DPIqaSvDTnJ/15hPHIK1s7dPN4=; b=sdfD9f7ZTzyftkK4U1VWOUoIHpQC1YdTPAgkqNAzGdUFlA2IAtk7PN2C39dujeo5qV yll8unqmmLY6Pes56CcXfpj7i6a7GcdJD4VtyMV7hQk/TjhcPTAA87DcUNE9EMYmXw24 65l1wFhbNEUYkrrToB3kqsZ2cKA07qYKo/MM77wCF/hfO0WX9jm5oA+wlPVbKcdZxcYE IQYjLUGR9fkm+hGFXrqzLGk7aB7eBrT0Mn+o+7I7+k3lNqqO4T1jzDp3x/j29kf+VdAp gHgsURcUY/LNCy8/OUv+hrHohq37UyDUgh+Eu5sQPG3FZT+US9B9jvedc3WGwUlEatXA gIng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=h8mbvGrJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varadarajan Narayanan --- v2: Add full stop to commit log. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 347307e..cb9d728 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1386,6 +1386,7 @@ CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m CONFIG_PHY_QCOM_USB_HS_28NM=m CONFIG_PHY_QCOM_USB_SS=m +CONFIG_PHY_QCOM_M31_USB=m CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y CONFIG_PHY_RCAR_GEN3_PCIE=y CONFIG_PHY_RCAR_GEN3_USB2=y