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Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bhupesh Sharma --- .../devicetree/bindings/ufs/qcom,ufs.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index f2d6298d926c..b517d76215e3 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -28,6 +28,7 @@ properties: - qcom,msm8998-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc + - qcom,sm6115-ufshc - qcom,sm6350-ufshc - qcom,sm8150-ufshc - qcom,sm8250-ufshc @@ -178,6 +179,31 @@ allOf: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm6115-ufshc + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: core_clk + - const: bus_aggr_clk + - const: iface_clk + - const: core_clk_unipro + - const: ref_clk + - const: tx_lane0_sync_clk + - const: rx_lane0_sync_clk + - const: ice_core_clk + reg: + minItems: 2 + maxItems: 2 + # TODO: define clock bindings for qcom,msm8994-ufshc unevaluatedProperties: false From patchwork Sun Oct 30 09:42:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12980 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720170wru; Sun, 30 Oct 2022 02:44:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6J9Zwpfw1piKqHBlvJ1rrRbY6GI1eZ3aBHIELaIGJMDdY0zuWSPFJ+P3paoBUmK+8kRfC8 X-Received: by 2002:a17:907:d1d:b0:7ad:4a55:9f01 with SMTP id gn29-20020a1709070d1d00b007ad4a559f01mr7413989ejc.723.1667123073896; Sun, 30 Oct 2022 02:44:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123073; cv=none; d=google.com; s=arc-20160816; b=SfGP45yN5edLeCCVHvohXP4ttK+Xc2QUMxJtxipfAYXE3hlTv6dz3z0SJf9kIBgs8W zEvp8TRNnsUXjsmPvz7GnQGo25wRfMRh8W29yaF/UyTGApuaLy2X2pcIWR1wQV5mghiQ WcNqfzs6d+PhBUudfezpbXt0/V5krFytTCBRzQlW76HPlM5ZrUkjWfopNNOuoEmKB+WD H2yAbZGZPsJeFbP9+FJGQOVMmYjryvlqFcSrC97bBTYZFXbU2foaiwH8yhnyor2w3tZ3 sgQwhbuFlfee8ep7JoPkJyNi1/M6pCAAsgMMvF/p0UNN41j84A+l9FMzvfuASqApNZOA ODgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0isp5Nh3x+mDnBNT4ggWZavrByNMZ7wrWYq2EVps+II=; b=BnW/T6mCf14LBohgF72+ZC2xpFARXycMGNQxgC2mGrEF26G5hbvrvlDOcqxnkLDgQt W6CnycckWmREMuXiV8NUfUxaGI7xIRsP7UQjrjNjzqF2vKnCnozyZgWr73gssBhJV3Ct PdJtLgH+/sVvdvcph6sYXtfQV1NYzl/XrZXwkxNhBdX8CQGJ4czQwy8O8URPczmvTing f9LyOeGH11NJAfrMk0N5iiiZHgtXYFjtXgn2zvvOhNopnZKhHmfPOrMFXieYf4rCo+x8 DBqQCAVUMcmqDjZLBHBDgLmsDEwT9C2xoqREqkYtBSRvVnFxiLm8vbfbGRE1IMkJWvcF QCqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="Dfq/bh4R"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Add support for the same in dt-bindings. Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Caleb Connolly --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..7048a1fd77a7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -54,6 +54,8 @@ description: | sdm845 sdx55 sdx65 + sm4250 + sm6115 sm6125 sm6350 sm7225 @@ -708,6 +710,11 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - oneplus,billie2 + - const: qcom,sm4250 + - items: - enum: - sony,pdx201 From patchwork Sun Oct 30 09:42:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12981 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720336wru; Sun, 30 Oct 2022 02:45:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM67lmNH8YN6JVUz2EHguNZenjz82oHhb2O7GU2qp5VnNfkXVg+mvquEOl45jB5x8eFuhi/7 X-Received: by 2002:a17:907:7e90:b0:78d:50f7:8abd with SMTP id qb16-20020a1709077e9000b0078d50f78abdmr7305362ejc.523.1667123103966; Sun, 30 Oct 2022 02:45:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123103; cv=none; d=google.com; s=arc-20160816; b=hgHcEw5VxP0UYEg1FDUGivHmNweRimtwZ9gFhFJMcQ+XPHU1KPpdD+jNGtHdM2v6s9 r2CJ9v6xEiGNZISs1xnFA6N/WHjfXtmiefGZq8VlphqKync6qtFgTgzsXZpWTK3RQ34p f+e1O8P27oa+8yKazMzfb9vm/kW0y5+PdlkoAB0sJ13++nLvBhxMrdqfVhzD6abpYrgu TPBVfhMomYr0t0/CVF4poKS/62DxNn2ps+kZ+9z4mnp6kzozJdQIZkUb+xH2YsglAJPK D8/Ddll84B82Swo5vIAoQ7cKGf+3DAVwBwKcbiseqPwDoPuMizz1EOWuWfujXvcML0KX ezcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cEHqsPqv95R3eGrYKhg4ruWGo3ymO/H/xi/Qhw4VFG0=; b=Rpk7toBnTTAkn5TKeL8zMxkRknMZNgHqvLNU8kYK9rEYfxQN8/dX9aFklFqnLMIZtj xGfo6TniUYagBlzuXltfjWzRfbwof7iGcPYF0mhzbv8wL7efztyrr6PDSVvibsBNfYGq UowXoTkJN1SOJOB6AdLY4GItQaqyvjG4AlMBtLAYzgG3QqQsioJmlWAwXZKKWLKxUtsB 8Yj8L4y6PCZQWiB1NdRMiUCjm50yQhqi3jrf/WNjOzx0vhwevIpTD9OnDELIWi+tuIRm MJZdkuWFeqlyYpQdPcQmmQQRQ0yCbTF2zqlDxWPsVo51R2S90ZQKwd3XWKlAcclai8WJ 4cXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=WK2hF+vu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev Acked-by: Rob Herring --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 0c2894498845..232895fa1d8d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,sc7280-gpi-dma + - qcom,sm6115-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma From patchwork Sun Oct 30 09:42:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12982 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720429wru; Sun, 30 Oct 2022 02:45:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6STAB/58cTurTeKcyg21XWlVBlRyGE//ePG1AxMLVqzQrs1rAW3kA8ka/h+5QmJ+qbE54s X-Received: by 2002:a17:907:7627:b0:78d:b6f5:9f15 with SMTP id jy7-20020a170907762700b0078db6f59f15mr7588090ejc.149.1667123118491; Sun, 30 Oct 2022 02:45:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123118; cv=none; d=google.com; s=arc-20160816; b=xCfGiGntqbY2Wuqe9PqaUH7Vp81TkqqbmWvwVJHDedZlx/ZNgoWmccRQ+67gb9pKkA 9h7CA+0Ya45d6N934l6NGnKsSBKov7MtNKNDCed984I3hxCSOLh0joqsPcg+f54SSQpZ ajtvOxQSu6GPKUTo6MYTjAlazbmVOG9TbDWwJJhBnjCOJCORnF20ziSETTKW/8tdPrMw uGMQF0uvbqhjNzZjmwAHELPYoUYjI+EmN0R2EncDtUrO3CghWp1sS4G5F+u1C5D0SIj8 rGrr7w0ZNEcHKsvnCDvgl44toTozqu7D0rwnZiiFEYCfTifwP6rZmzLYMoHlkvSdQNMG 37nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rUpdkVpaImdCke90/hvYwepQ6uJUg8seHB9Am7OQuCE=; b=ULwwgLw4C5FM6C/ihr4ZLEmxwxVjf2uKoDeWyriJzqE+2IVvdPoRn4R/+WBT+LiUn8 WNnw4cvkAiSpuNmkvzPYUqFNj8V2ESOge9HBlD/PgE3BwfWH+6R96KZDnz39oTbNt7JU /Hny5FrWMwD0GhAcwD8GHLJwUtvtst8woL4IPD1XEeJuLpC7Z5a0XXh1B751fUWrsOX8 4EqCRNpMvzS/kofDyzj+5mPmkaQlRU+OkDb6Bsn9SMwrsNElicUED2qBdzp4QTasS9qX PrdKyx7YPrKJK/m4JRyQ4sD1bqZBA1Z/A6uLSigaOItQPdDfT0EOJTyVOhwkQMYe4k0n 8M+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=YDoaDcvG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..71f8f638a1f8 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -41,6 +41,7 @@ properties: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sm6115-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8150-smmu-500 From patchwork Sun Oct 30 09:42:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12986 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720747wru; Sun, 30 Oct 2022 02:46:28 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7GQzSH35RetvAArxzRhWi1D3Z7n7VasdesYmJ14W+lZPskxLBV1gN5Gn4xUzO2VbdoeRva X-Received: by 2002:a17:903:124e:b0:179:da2f:244e with SMTP id u14-20020a170903124e00b00179da2f244emr8557041plh.169.1667123188037; Sun, 30 Oct 2022 02:46:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123188; cv=none; d=google.com; s=arc-20160816; b=uo157y1IqZyqVpkqARRkBpDV7l0gS2EJwa4dSpV6wgaNnsO3nxWO2jpdR/2K88cuCi 82RjzpJD8tv+Cdk6DwwZgWzCRbPI3umJKIzxg9ILc2TtN4z/GqLSCjbLTLDvgA26z6za M2Pt60ZilFptuNxJO+QVmT4FKRkW0DMQ46FNqT4nQgSmp+6TQezfscbBfL6hEjZiE7JJ KwsE4v57g19eeVDfTF7/oAUOBIMHA2Mme1mM0i79iORpIxzZWBy2oZ0GbTLUHBe3Qhj8 /GwMOue9nLx2kkM8PlEx6v/ydE8BwlE99AJFC6MdEBCBNh36beucyA+8cUCcOKECzUxV mO7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g/VLR/q0mJpm1g0Mv+FaKiNU++ksU9JCwtcy+gU033k=; b=ZLP83G8GxNPQdGgfpWNO2rJlonAudg8yW35eiEHNeAW9mENkVdlOOhVmzyZaLyzGDW cCghyt6pVZlgoolEeZ9BkkAAti9PuhQyEXBZgYb0lQ4gj0XkKfY2+1i6ezghYT8ABVaS vtkDN/B6kTzs7D2OgBDW2AElUI+FpnNwb7P+lJiiK8xYq45Toh+Um318d+xBcZvg6m2M HDgxmNmYPRDCaMeV7ZZbEYee+wv5Xn8bCywwQ4zaTPSNHcNcr4xVOwY5lMdQ4szTX47X lPv6Zl+6zG5/rPHSsGyLG9B1vND03B+MLHwmS09FYWRS/vrEPfSS9UiHBRc+hOuUXCF6 9N+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=kz4BtlEx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b2708de25ea3..526fec79b4fe 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -432,6 +432,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,sc8280xp-smmu-500" }, { .compatible = "qcom,sdm630-smmu-v2" }, { .compatible = "qcom,sdm845-smmu-500" }, + { .compatible = "qcom,sm6115-smmu-500" }, { .compatible = "qcom,sm6125-smmu-500" }, { .compatible = "qcom,sm6350-smmu-500" }, { .compatible = "qcom,sm6375-smmu-500" }, From patchwork Sun Oct 30 09:42:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12985 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720614wru; Sun, 30 Oct 2022 02:46:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6++DDMNDZcWVxtmaJpb7gdVKOYR6xraczd70GowtHh9oAfZwahsagr8G3HwvBjfADwrRwt X-Received: by 2002:a17:906:8a63:b0:7ad:95cf:726a with SMTP id hy3-20020a1709068a6300b007ad95cf726amr7555329ejc.82.1667123161071; Sun, 30 Oct 2022 02:46:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123161; cv=none; d=google.com; s=arc-20160816; b=JU/8b8i2c17bJ8sR+1ngSRiLcf/gclbg0ppp568L9Lm27oKzN3sV4CZu8hIrrp+vxV 5wcNayJRfXj1vi8JFDLgXy7xCpvI+2DXBlSGg+pcZwM9Mrxdu+6zrOoGoFY3ncI+r/Wa 66J/FiSlZcZmMV17akDT8g7CbEc1BhG3DrqXXtC+S8CAkkaBPGK4zXmNcR8QIAWIaqJM pTSFoLNdUTWWtsCzRE8Vz5m0HhA73WeVFyABbLy62lZdVoGciz6eVDZ/gx+ECSxk/P2a sxnDMsea89hP2zQTkQLPB3r7W/rnDPX3ojRAZ3PfKl9DPLZHMoU3Uo4fY7PL2JURuxtt iwKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QKLnyS1dI/VsC5RjU6rtIktExiExbn9qlM4kF/V4ru8=; b=TRCLdlD89+2SIIdpXO397gjuW9J+wDIH/llu/HigaigEf1hrUkb0OAjxSNgpIA4L1o ZiW8fEB+8p3pEu7AaM5FbI1ZTAS3mvSVr7ML9fAXa+ZDUT0ap3gEGTlgXnVHbhKwDoPF BsohduiyHNaHe/v5MS9XRmhkGKJqWzluelAUY9OwIkIfCS5uVRXTejt4GhH8sNaPZYK8 4nfmJQL67akpuDu/grbtw1HvWuSwcG/M+TXGvj5nc4tGZqRSFW8dTHLFI8DprxZyz5Ho DittuIgjNN/21S/mRjlTT9jcpK0MhAZZn2sdsFBgrwJfoWo8om73oWApjYsAVsqRxbWM GsWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=imswqNBk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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This includes: - GCC - Pinctrl - RPM (CC+PD) - USB - MMC - UFS Signed-off-by: Iskren Chernev Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 854 +++++++++++++++++++++++++++ 1 file changed, 854 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6115.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi new file mode 100644 index 000000000000..0340ed21be05 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6115", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: memory@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + cdsp_sec_mem: memory@46200000 { + reg = <0x0 0x46200000 0x0 0x1e00000>; + no-map; + }; + + pil_modem_mem: memory@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: memory@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: memory@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_cdsp_mem: memory@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@53800000 { + reg = <0x0 0x53800000 0x0 0x2800000>; + no-map; + }; + + pil_ipa_fw_mem: memory@56100000 { + reg = <0x0 0x56100000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@56110000 { + reg = <0x0 0x56110000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: memory@56115000 { + reg = <0x0 0x56115000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: memory@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: memory@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: memory@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x00340000 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 121>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-sm6115"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_1_hsphy: phy@1613000 { + compatible = "qcom,sm6115-qusb2-phy"; + reg = <0x01613000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + + status = "disabled"; + }; + + qfprom@1b40000 { + compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; + reg = <0x01b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clock-names = "iface", "core", "xo"; + + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + power-domains = <&rpmpd SM6115_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0x00a0 0x0>; + resets = <&gcc GCC_SDCC2_BCR>; + + bus-width = <4>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <1>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x100 0>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + + freq-table-hz = <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6115-qmp-ufs-phy"; + reg = <0x04807000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@4807400 { + reg = <0x4807400 0x098>, + <0x4807600 0x130>, + <0x4807c00 0x16c>; + #phy-cells = <0>; + }; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; + reg = <0x04ef8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <66666667>; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + qcom,select-utmi-as-pipe-clk; + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x04e00000 0xcd00>; + interrupts = ; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + reg = <0x0c600000 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,sm6115-apcs-hmss-global"; + reg = <0x0f111000 0x1000>; + + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <19200000>; + + frame@f121000 { + reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f123000 { + reg = <0x0f123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f124000 { + reg = <0x0f124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f125000 { + reg = <0x0f125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f126000 { + reg = <0x0f126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f127000 { + reg = <0x0f127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f128000 { + reg = <0x0f128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Sun Oct 30 09:42:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12983 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720502wru; Sun, 30 Oct 2022 02:45:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM50YNk1GrnKBsxhlESryhHXBnw/dzT0Af2Ls12GDG0iSYaQzIkeWYWlgiAb79RGvWtLF9rx X-Received: by 2002:a17:906:5dac:b0:791:93de:c61d with SMTP id n12-20020a1709065dac00b0079193dec61dmr7393770ejv.751.1667123131688; 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Signed-off-by: Iskren Chernev Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm4250.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi new file mode 100644 index 000000000000..c5add8f44fc0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +#include "sm6115.dtsi" + +&CPU0 { + compatible = "qcom,kryo240"; +}; + +&CPU1 { + compatible = "qcom,kryo240"; +}; + +&CPU2 { + compatible = "qcom,kryo240"; +}; + +&CPU3 { + compatible = "qcom,kryo240"; +}; + +&CPU4 { + compatible = "qcom,kryo240"; +}; + +&CPU5 { + compatible = "qcom,kryo240"; +}; + +&CPU6 { + compatible = "qcom,kryo240"; +}; + +&CPU7 { + compatible = "qcom,kryo240"; +}; From patchwork Sun Oct 30 09:42:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iskren Chernev X-Patchwork-Id: 12984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1720522wru; Sun, 30 Oct 2022 02:45:36 -0700 (PDT) X-Google-Smtp-Source: AMsMyM49+m9wShe8MVWjkf5R0Toiq/DiM3/9rhVOTPgrDfMg6y4YTP6yHFs8qcFpAw/e2z4ge97X X-Received: by 2002:a17:907:7213:b0:791:8aa5:5635 with SMTP id dr19-20020a170907721300b007918aa55635mr7534900ejc.348.1667123136041; Sun, 30 Oct 2022 02:45:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667123136; cv=none; d=google.com; s=arc-20160816; b=mFg/hbCIpN5lftDbFioy2I0zYNtXtyUakqCxyO2KyjSskpdLgPagWqSqTMbaEXZDcl NIgmfcAUbCp1qlSt7NV2KYRks4pFIYUIIG7q/BrukDTGYot/K0sPtiLCZUOhQXVTrs9J Vrrraudu3oRV0ni9fH58FlRgeqxKS8g8GVIsHpsATa/rfbDuPl9x1r0bCBFgsjjSxOSB NWYq/rjG5wEVPBFT/WrMhThFqZdi7eeHTwi1xAscK5ixalAFiEbq9OqFRIQi5699wtUF X0F8+NXfXycNtm1z+kTAsAqGAPnIOb3hLy+f4knthSxlhwpciiMpeLidLt7KGoXVHPiF SoUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wGW3s7VAfdS0LxK3XABjCKqjaFAM6/EYoTFRFX90Zzg=; b=ypZv6OVVHZH3spRvePX3J7l5rd7IHErP6GJLW6pvfsyywo24utWy/RlfMuKf9+YXSq ZRL9g4Ye7xRsxAr75wG7fBqcSH20nX9l/TkXbxhTQbNEN7nRzT6WHeBNzuHJVYjh6Okp 2zZdOyd4U3/+HFdGjPNAtlkwD8yi2euE2nBLgge2ag3o9ddtUjuLeIrWFdEX69xI/QzR /P9IhnezHRYK3Q3ybym96XRPMZr2gm7Qac+HIs68rQVmL0VlaLtLZLGgKFY7VR/U3k+H v33p/nZaODIDw8EymYXbihL44A1dYbLwsR47WsU1wDmz2/rRgp0bAw8vTtjJGY1fNnLQ 8wqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=U+dZIB5R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Piccoli" , linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Subject: [PATCH v5 8/8] arm64: dts: qcom: sm4250: Add support for oneplus-billie2 Date: Sun, 30 Oct 2022 11:42:58 +0200 Message-Id: <20221030094258.486428-9-iskren.chernev@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221030094258.486428-1-iskren.chernev@gmail.com> References: <20221030094258.486428-1-iskren.chernev@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748105309715261399?= X-GMAIL-MSGID: =?utf-8?q?1748105309715261399?= Add initial support for OnePlus Nord N100, based on SM4250. Currently working: - boots - usb - built-in flash storage (UFS) - SD card reader Signed-off-by: Iskren Chernev Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 241 ++++++++++++++++++ 2 files changed, 242 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..eb2a58b8af5f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts new file mode 100644 index 000000000000..a3f1c7c41fd7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2021, Iskren Chernev + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "OnePlus Nord N100"; + compatible = "oneplus,billie2", "qcom,sm4250"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>; + qcom,board-id = <0x1000b 0x00>; + + aliases { + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1600 * 720 * 4)>; + width = <720>; + height = <1600>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; +}; + +&reserved_memory { + bootloader_log_mem: memory@5fff7000 { + reg = <0x0 0x5fff7000 0x0 0x8000>; + no-map; + }; + + ramoops@cbe00000 { + compatible = "ramoops"; + reg = <0x0 0xcbe00000 0x0 0x400000>; + record-size = <0x40000>; + pmsg-size = <0x200000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + }; + + param_mem: memory@cc200000 { + reg = <0x0 0xcc200000 0x0 0x100000>; + no-map; + }; + + mtp_mem: memory@cc300000 { + reg = <0x00 0xcc300000 0x00 0xb00000>; + no-map; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s8a: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_l11a>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +};