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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y5-20020a170906914500b00993d5cdf483si4043666ejw.807.2023.07.11.22.51.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 22:51:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ve+GPkw+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2CB843857BB2 for ; Wed, 12 Jul 2023 05:51:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2CB843857BB2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689141103; bh=wzdbIwW17Ffth/4PWvzW/hqK3Q9ETBFwa8h1tJo2FNk=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ve+GPkw+CnikkW0GvalkzvcXJP3azFglZYTlS+o+DhKkYv9YJgod/MXyavyGf3aIS WhPMN1DIfJTNVV39S9zQ5ygeRZbpQV5GwRp50GES7MccVwYkPHf52RESylgGRvosDo 1eANqdQCAWjdy+BrgNWbW6Ou9TdV0TMY/vR6ahSo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id EE92D3858D20 for ; Wed, 12 Jul 2023 05:50:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EE92D3858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="367427508" X-IronPort-AV: E=Sophos;i="6.01,198,1684825200"; d="scan'208";a="367427508" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2023 22:50:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="671693753" X-IronPort-AV: E=Sophos;i="6.01,198,1684825200"; d="scan'208";a="671693753" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 11 Jul 2023 22:50:55 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 8FB551007826; Wed, 12 Jul 2023 13:50:54 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM Date: Wed, 12 Jul 2023 13:50:53 +0800 Message-Id: <20230712055053.4016796-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712054609.3958442-1-pan2.li@intel.com> References: <20230712054609.3958442-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771192525704265527 X-GMAIL-MSGID: 1771192822742913258 From: Pan Li When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We will also prepare more test cases in another PATCH. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (regnum_definition_p): New function. (insn_asm_p): Ditto. (riscv_vxrm_mode_after): New function for fixed-point. (global_vxrm_state_unknown_p): Ditto. (riscv_frm_mode_after): New function for floating-point. (global_frm_state_unknown_p): Ditto. (riscv_mode_after): Leverage new functions. (riscv_entity_mode_after): Removed. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 96 +++++++++++++++++++++++++++++++++------ 1 file changed, 82 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38d8eb2fcf5..553fbb4435a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7742,19 +7742,91 @@ global_state_unknown_p (rtx_insn *insn, unsigned int regno) return false; } +static bool +regnum_definition_p (rtx_insn *insn, unsigned int regno) +{ + df_ref ref; + struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); + + /* Return true if there is a definition of regno. */ + for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref)) + if (DF_REF_REGNO (ref) == regno) + return true; + + return false; +} + +static bool +insn_asm_p (rtx_insn *insn) +{ + extract_insn (insn); + + return recog_data.is_asm; +} + +static bool +global_vxrm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of VXRM. */ + if (regnum_definition_p (insn, VXRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the VXRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + /* Return true for all assembly since users may hardcode a assembly + like this: asm volatile ("csrwi vxrm, 0"). */ + if (insn_asm_p (insn)) + return true; + + return false; +} + +static bool +global_frm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of FRM. */ + if (regnum_definition_p (insn, FRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the FRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + return false; +} + static int -riscv_entity_mode_after (int regnum, rtx_insn *insn, int mode, - int (*get_attr_mode) (rtx_insn *), int default_mode) +riscv_vxrm_mode_after (rtx_insn *insn, int mode) { - if (global_state_unknown_p (insn, regnum)) - return default_mode; - else if (recog_memoized (insn) < 0) + if (global_vxrm_state_unknown_p (insn)) + return VXRM_MODE_NONE; + + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn))) + return get_attr_vxrm_mode (insn); + else return mode; +} - rtx reg = gen_rtx_REG (SImode, regnum); - bool mentioned_p = reg_mentioned_p (reg, PATTERN (insn)); +static int +riscv_frm_mode_after (rtx_insn *insn, int mode) +{ + if (global_frm_state_unknown_p (insn)) + return FRM_MODE_NONE; - return mentioned_p ? get_attr_mode (insn): mode; + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, FRM_REGNUM), PATTERN (insn))) + return get_attr_frm_mode (insn); + else + return mode; } /* Return the mode that an insn results in. */ @@ -7765,13 +7837,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn) switch (entity) { case RISCV_VXRM: - return riscv_entity_mode_after (VXRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_vxrm_mode, - VXRM_MODE_NONE); + return riscv_vxrm_mode_after (insn, mode); case RISCV_FRM: - return riscv_entity_mode_after (FRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_frm_mode, - FRM_MODE_DYN); + return riscv_frm_mode_after (insn, mode); default: gcc_unreachable (); }