From patchwork Wed Jul 12 05:46:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 118829 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp928758vqm; Tue, 11 Jul 2023 22:47:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlG2F+ni9vHLGzGosKsUuvZwtdgapNoatrgpK8F7KSpR+E2hFpXHBQbRa0eogkc6T4MJ7wN8 X-Received: by 2002:a17:906:d7:b0:992:ab3a:f0d4 with SMTP id 23-20020a17090600d700b00992ab3af0d4mr15841093eji.17.1689140821283; Tue, 11 Jul 2023 22:47:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689140821; cv=none; d=google.com; s=arc-20160816; b=AUeULfDiQHxx8HX18zhyx71H+4XIJvPGWdnfydR4lhNH6vguVg2LAcpyTbWisv8Xo1 z4CKS1w4d6LvNl9k0lCidiUWGY7ROb2d33WAMUyib502Fw6DaRWiI9xojkCzW30Emtr5 wz2tDgcZ4V/1N0g8wUrhsIFuxhpanR0ehr5jT0o5dgJhgeJQ0qpLboJJ/p1C49pLKt7F KaDZSLGZDaMoC/VT6OulZl5DEcLK13sQowdVmeYDxuTTDhXvpN5+h/oQYAJYBbuAPZS7 toziv3YVHjONptGjAbDOmSAWBW3EN/CwGEmM7A+dkBEQ/pvh8Lsld7vePB9heCbRp7SK Wjjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=BlYxyYb47e73PAEDODPqhQl/LC/0kqmdoyKDEXnOpms=; fh=Nw/M2boavwJLWTbobiAULTtRLIIxYVZeHWeEMcryaHM=; b=FmTdQPjeO0hGmb858kKj5/aVtLMIUTWqI/ZsJawX5YD5Mykx3YhPI270cEsL223ySN 8nQbGN56HZFTFX3+kt6luCjzkxcKeMwkKpuTxQYP28CtC5eVs+S3XEaKsi4O1eavhgp3 sbfNXN0A872HOqDb4/YB2/wX2HsvxtWqoWXxZqgyfR6LSUGq4MGheNnc+J0hK/2vMSQt V4hs08YsqSsGDIq3JmncTL1BEvgr9TvC8n0n2GTLGTcYcrtMW84XnjJzAVXgJ4SGvF2G mN28444f85o4QoviDj+8gVX4PLDmago/BFB0EMQ2C8U9KUdE2gaXyzkNstwN5qX8Y/vu xjTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=b9zLWjn3; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l9-20020a1709062a8900b009936735754dsi3848909eje.897.2023.07.11.22.47.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 22:47:01 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=b9zLWjn3; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 014C13858C31 for ; Wed, 12 Jul 2023 05:47:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 014C13858C31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689140820; bh=BlYxyYb47e73PAEDODPqhQl/LC/0kqmdoyKDEXnOpms=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=b9zLWjn3IRQdKXfKzh7vwVN02scCU8lEh9Fx2zief7TPf6p3ydeyGP0jjJC3gdRnp 8ZauWyyd3O/tzNllCLgy+Vis/YielFRALJ77RuXlwA62/xIRaj3HLAGKcHszEd/Ea8 wj6qPJn1x76z4BmE8D5rEY/szTbET5YsjEYtzMVc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 7A3B63858D20 for ; Wed, 12 Jul 2023 05:46:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A3B63858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="395603651" X-IronPort-AV: E=Sophos;i="6.01,198,1684825200"; d="scan'208";a="395603651" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2023 22:46:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="865990689" X-IronPort-AV: E=Sophos;i="6.01,198,1684825200"; d="scan'208";a="865990689" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 11 Jul 2023 22:46:12 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id A5E8B1007826; Wed, 12 Jul 2023 13:46:11 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Refactor riscv mode after for VXRM and FRM Date: Wed, 12 Jul 2023 13:46:09 +0800 Message-Id: <20230712054609.3958442-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771192525704265527 X-GMAIL-MSGID: 1771192525704265527 From: Pan Li When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We will also prepare more test cases in another PATCH. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (regnum_definition_p): New function. (insn_asm_p): Ditto. (riscv_vxrm_mode_after): New function for fixed-point. (global_vxrm_state_unknown_p): Ditto. (riscv_frm_mode_after): New function for floating-point. (global_frm_state_unknown_p): Ditto. (riscv_mode_after): Leverage new functions. (riscv_entity_mode_after): Removed. --- gcc/config/riscv/riscv.cc | 96 +++++++++++++++++++++++++++++++++------ 1 file changed, 82 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38d8eb2fcf5..dbaf100fd8e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7742,19 +7742,91 @@ global_state_unknown_p (rtx_insn *insn, unsigned int regno) return false; } +static bool +regnum_definition_p (rtx_insn *insn, unsigned int regno) +{ + df_ref ref; + struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); + + /* Return true if there is a definition of regno. */ + for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref)) + if (DF_REF_REGNO (ref) == regno) + return true; + + return false; +} + +static bool +insn_asm_p (rtx_insn *insn) +{ + extract_insn (insn); + + return recog_data.is_asm; +} + +static bool +global_vxrm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of VXRM. */ + if (regnum_definition_p (insn, VXRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the VXRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + /* Return true for all assembly since users may hardcode a assembly + like this: asm volatile ("csrwi vxrm, 0"). */ + if (insn_asm_p (insn)) + return true; + + return false; +} + +static bool +global_frm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of FRM. */ + if (regnum_definition_p (insn, FRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the VXRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + return false; +} + static int -riscv_entity_mode_after (int regnum, rtx_insn *insn, int mode, - int (*get_attr_mode) (rtx_insn *), int default_mode) +riscv_vxrm_mode_after (rtx_insn *insn, int mode) { - if (global_state_unknown_p (insn, regnum)) - return default_mode; - else if (recog_memoized (insn) < 0) + if (global_vxrm_state_unknown_p (insn)) + return VXRM_MODE_NONE; + + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn))) + return get_attr_vxrm_mode (insn); + else return mode; +} - rtx reg = gen_rtx_REG (SImode, regnum); - bool mentioned_p = reg_mentioned_p (reg, PATTERN (insn)); +static int +riscv_frm_mode_after (rtx_insn *insn, int mode) +{ + if (global_frm_state_unknown_p (insn)) + return FRM_MODE_NONE; - return mentioned_p ? get_attr_mode (insn): mode; + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, FRM_REGNUM), PATTERN (insn))) + return get_attr_frm_mode (insn); + else + return mode; } /* Return the mode that an insn results in. */ @@ -7765,13 +7837,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn) switch (entity) { case RISCV_VXRM: - return riscv_entity_mode_after (VXRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_vxrm_mode, - VXRM_MODE_NONE); + return riscv_vxrm_mode_after (insn, mode); case RISCV_FRM: - return riscv_entity_mode_after (FRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_frm_mode, - FRM_MODE_DYN); + return riscv_frm_mode_after (insn, mode); default: gcc_unreachable (); }