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Set the I(nput) bit in __io_ar() to restore the ordering, align inline comments. [1] https://github.com/riscv/riscv-platform-specs Signed-off-by: Andrea Parri --- arch/riscv/include/asm/mmio.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index aff6c33ab0c08..4c58ee7f95ecf 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -101,9 +101,9 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * Relaxed I/O memory access primitives. These follow the Device memory * ordering rules but do not guarantee any ordering relative to Normal memory * accesses. These are defined to order the indicated access (either a read or - * write) with all other I/O memory accesses. Since the platform specification - * defines that all I/O regions are strongly ordered on channel 2, no explicit - * fences are required to enforce this ordering. + * write) with all other I/O memory accesses to the same peripheral. Since the + * platform specification defines that all I/O regions are strongly ordered on + * channel 0, no explicit fences are required to enforce this ordering. */ /* FIXME: These are now the same as asm-generic */ #define __io_rbr() do {} while (0) @@ -125,14 +125,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #endif /* - * I/O memory access primitives. Reads are ordered relative to any - * following Normal memory access. Writes are ordered relative to any prior - * Normal memory access. The memory barriers here are necessary as RISC-V + * I/O memory access primitives. Reads are ordered relative to any following + * Normal memory read and delay() loop. Writes are ordered relative to any + * prior Normal memory write. The memory barriers here are necessary as RISC-V * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory") -#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory") +#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) +#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) #define __io_aw() mmiowb_set_pending() #define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) From patchwork Tue Jul 11 13:33:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Parri X-Patchwork-Id: 118557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp515666vqm; Tue, 11 Jul 2023 07:20:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlE8HIeLcBPI8khhZ9SOW78t+6ILIa53mSMgDGq577aACGu8De+pmZ5DsvhkdgGyKyWPweU+ X-Received: by 2002:a05:6402:b09:b0:51e:1095:5ae5 with SMTP id bm9-20020a0564020b0900b0051e10955ae5mr16433750edb.8.1689085205372; Tue, 11 Jul 2023 07:20:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689085205; cv=none; d=google.com; s=arc-20160816; b=xQN0MPynHNWWUFYnzvEFfK7DZlZpmb8Qgn30uRoWgPbWkE6WwM6zABg1JC7pPGQkfJ t54qDFDeYi5r3xPS5Q172YsavXPXojvkJH3NWjLLMGzv/hT0wXPZgC0ag4oUpGYkZnZP 4ZcLv2V7kVMjPuNrET0jhDN5j60USle1k12nJvmXMFQfp2srFPIx9Velt4si8Ch3sAa9 UtSssc8mSJ5gXRwGQcjhQwKD9fqh5vvK9MuH+X0M5TayA2MeMmDrKKBkWmhqfkE95VDh nTj8wyyAZCz5UaB5SUk7o3BCcSUmwq9DNDSa7NjkyI7OetxP9jI9qSSYEOW53y6ELVjX 3Nog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hjSbzIFEjI+X1OOQ6m2DfrSrdZF0QXWrCZ+NzN3e1QQ=; fh=YYtMg3dyTLwSwThzJ+b5yIx4WLaHuVbs8jP2ERXLYYI=; b=ilzMCfoyucizqIn+Rab1NzBhR2J1FJwXSbjmL2GOX4PY0s072EPKBPa0fIlbqxuOnN aQDvXoVgyFVBPSiaRTGWHA3QgGuVqpsZb2m1MwIm5K8Vgtxf4zuxacpzFgag4DZcTWuB VYDiZ9yLwgNDbztyi/IggejQ3m7Lo4R3+tYuW39/REh7O/5mFflw1Q1HKZXafqYxOfIs Hn2FlpVhtNzhW7PZgp56CVNp3GhL2mdVeK3Pn5lfluAMfSjEY53WD0tJvoKaU+kd0RTI 78eymdwWu4ozpkLZuUjmBayI/Ksz7JCR3XO6rh8LXHELcRTD+rnZu3fQ89Hr14EoAI2d rYsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="E3/CeuSO"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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No functional change intended. Signed-off-by: Andrea Parri --- arch/riscv/include/asm/mmio.h | 68 ++++------------------------------- 1 file changed, 6 insertions(+), 62 deletions(-) diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h index 4c58ee7f95ecf..116b898fe969d 100644 --- a/arch/riscv/include/asm/mmio.h +++ b/arch/riscv/include/asm/mmio.h @@ -80,72 +80,16 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) #endif /* - * Unordered I/O memory access primitives. These are even more relaxed than - * the relaxed versions, as they don't even order accesses between successive - * operations to the I/O regions. - */ -#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) -#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) -#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) - -#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) -#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) -#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) - -#ifdef CONFIG_64BIT -#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) -#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) -#endif - -/* - * Relaxed I/O memory access primitives. These follow the Device memory - * ordering rules but do not guarantee any ordering relative to Normal memory - * accesses. These are defined to order the indicated access (either a read or - * write) with all other I/O memory accesses to the same peripheral. Since the - * platform specification defines that all I/O regions are strongly ordered on - * channel 0, no explicit fences are required to enforce this ordering. - */ -/* FIXME: These are now the same as asm-generic */ -#define __io_rbr() do {} while (0) -#define __io_rar() do {} while (0) -#define __io_rbw() do {} while (0) -#define __io_raw() do {} while (0) - -#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) -#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) -#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) - -#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) -#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) -#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) - -#ifdef CONFIG_64BIT -#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) -#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) -#endif - -/* - * I/O memory access primitives. Reads are ordered relative to any following - * Normal memory read and delay() loop. Writes are ordered relative to any - * prior Normal memory write. The memory barriers here are necessary as RISC-V - * doesn't define any ordering between the memory space and the I/O space. + * I/O barriers + * + * See Documentation/memory-barriers.txt, "Kernel I/O barrier effects". + * + * Assume that each I/O region is strongly ordered on channel 0, following the + * RISC-V Platform Specification, "OS-A Common Requirements". */ #define __io_br() do {} while (0) #define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); }) #define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); }) #define __io_aw() mmiowb_set_pending() -#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) -#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) -#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) - -#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) -#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) -#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) - -#ifdef CONFIG_64BIT -#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) -#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); }) -#endif - #endif /* _ASM_RISCV_MMIO_H */