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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:26 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:00 +0200 Subject: [PATCH 01/53] dt-bindings: interconnect: qcom,icc: Introduce fixed BCM voter indices MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-1-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1189; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9/TmGzQ1xk3CQ8ToyRcpOQBYP1VhR10l+JU+aSmEvI0=; b=N1JxOuvEYm4h/wsNdORtSNFT8AF68EXhuMFZexG+clfwKvtG5+uxA4rn/Z4fouP9EkKmuRWz+ 7R/htFQncM5BE7iN2tU0kXbvvV7s3St2Rs+MKybBnVpLAaPzAPW+821 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127536884491417 X-GMAIL-MSGID: 1771127536884491417 It makes zero (or less) sense to consume BCM voters per interconnect provider. They are shared throughout the entire system and it's enough to keep a single reference to each of them. Storing them in a shared array at fixed indices will let us improve both the representation of the RPMh architecture (every RSC can hold a resource vote on any bus, they're not limited in that regard) and save as much as kilobytes worth of RAM. Signed-off-by: Konrad Dybcio --- include/dt-bindings/interconnect/qcom,icc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,icc.h b/include/dt-bindings/interconnect/qcom,icc.h index cd34f36daaaa..9c13ef8a044e 100644 --- a/include/dt-bindings/interconnect/qcom,icc.h +++ b/include/dt-bindings/interconnect/qcom,icc.h @@ -23,4 +23,12 @@ #define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ QCOM_ICC_TAG_SLEEP) +#define ICC_BCM_VOTER_APPS 0 +#define ICC_BCM_VOTER_DISP 1 +#define ICC_BCM_VOTER_CAM0 2 +#define ICC_BCM_VOTER_CAM1 3 +#define ICC_BCM_VOTER_CAM2 4 + +#define ICC_BCM_VOTER_MAX 64 + #endif From patchwork Tue Jul 11 12:18:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118459 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp439838vqm; Tue, 11 Jul 2023 05:30:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlH7/1vYy8JvHvQAa4YNOyatr166hZ2nEGXatSatBQirfwIdWXEVD0a4hP8LACyQ72zesCzI X-Received: by 2002:a05:6a00:3a21:b0:682:7d8a:f887 with SMTP id fj33-20020a056a003a2100b006827d8af887mr14239259pfb.30.1689078602603; Tue, 11 Jul 2023 05:30:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078602; cv=none; d=google.com; s=arc-20160816; b=LCeEatxQN82iWxLf3mfN5LpXr1v7z/Wi6HJKD0JXJ00OBnVnwwzg9xPPYJitq1quU+ jZPaI0lOt4C4MK9UXGcdjwsPjm0xLa7JKwQNdaj1Jx9/x281wQQ5IpLEcxPxjfwwzEFD Z2LqTPUJGREGmLESOok9e3VXaF5vwZxc1hb4ynV1V9X113p7jyzkPme1EyW4rgueo7CA JO0WdIPgfM7aD+gMyzdbNObennZscPPuPNtz570IW1AGVF4AQU3wTFD+iwvxfq3gA2GA jtPOKCr1skqkihZIYrRyBgO5lHKGklnD+eR4GvnW/IiHH1iHgWWYknLQglnFx9qhd7Dt uE9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=+wKqZuebC0/DNlU3YArXv0CU05fgiLNPi4ZrsgdcBCw=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=xZXulIKSVGDLvutAPlHwFsp3q8hPRUj/Jnt3SM4Iv/sNwPWch3niH0++44jkxPJxMC KJvLes9ZdT6fO3GGMAHgOQ8SwPY8F0HBdHdpvvnYGnt0jaLyOFUpfWsexjGKeUD4ufNh h2hnE7Oe+TY9AEgm3GM/8hzoNNRECv6YN/3/B7tkAYNxDPvpya6WXARWq32ltYxcdzCb Lyj8G4mn1g7p/IaWo+MPcYVrIpWDFWH5rjye+LimRmuXxHfHYhwmjmqSo5PMC+ua5u0G 6nbNX0MDZ6GCF4yes6y+2GiF8/+KtXtJfB4wTdwwS22ShLIzjcl0U6+Wn8dG4kT2c+Qx zfaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WKIt9VI7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:28 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:01 +0200 Subject: [PATCH 02/53] dt-bindings: interconnect: qcom,bcm-voter: Add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-2-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1777; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1YdtkjCpwqfCeGyrzm5y0lnW6+XAD6b/nL964j7XiAc=; b=xos5lY2485rsc/Fk8rtrxCyUPIzjqnRyhiyLpKu+58DpQKwGajPucJDjZBVy9wi9zJJ9gfdh6 VLXTFNZnq0gAaPF4VFj/7ocVEN6NJ6MYG26wIQmS+2QDKR9YXajYKvP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127284913321004 X-GMAIL-MSGID: 1771127284913321004 In order to (at least partially) untangle the global BCM voter lookup (as again, they are shared throughout the entire system and not bound to individual buses/providers), introduce a new required property to assign a unique identifier to each BCM voter. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interconnect/qcom,bcm-voter.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml index eec987640b37..09321c1918bf 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml @@ -38,8 +38,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 + qcom,bcm-voter-idx: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A globally unique predefined discrimnator, identifying each BCM voter. + required: - compatible + - qcom,bcm-voter-idx additionalProperties: false @@ -48,8 +54,11 @@ examples: # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml - | + #include + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node @@ -61,5 +70,6 @@ examples: disp_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; + qcom,bcm-voter-idx = ; }; ... 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:29 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:02 +0200 Subject: [PATCH 03/53] interconnect: qcom: icc-rpmh: Store direct BCM voter references MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-3-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5806; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=op0OvwRNT/rufglepzjHxJNouLHRuZ5bBbm7iZd+W3A=; b=hcbnLTk5GYW1/XfQr0MsnVa4AHorgH8tXJFov6Rx8PUHIkGm+fyj0WYFcLKB912rf5F+bG2kV HPnsL3Qld0lClgPC5l+H31c8ICbLpQz4v/6Qt2Ur+dwKu8pQbc9h0YH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127634198606322 X-GMAIL-MSGID: 1771127634198606322 It makes zero (or less) sense to consume BCM voters per interconnect provider. They are shared throughout the entire system and it's enough to keep a single reference to each of them. Since the list of these voters is common across SoCs and across buses on them, turn to caching a pointer to each voter at a dt-bindings-defined index in a shared array to make accesses O(1) (instead of a clunky loop-based lookup) and vastly save on redefining & referencing the same set over and over again. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.c | 29 ++++++++++++++++++++++++++++- drivers/interconnect/qcom/icc-rpmh.c | 16 +++++++++------- drivers/interconnect/qcom/icc-rpmh.h | 4 ++++ 3 files changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c index d5f2a6b5376b..f8fbddb87e6b 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -19,6 +19,17 @@ static LIST_HEAD(bcm_voters); static DEFINE_MUTEX(bcm_voter_lock); +struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX] = { }; +EXPORT_SYMBOL_GPL(qcom_icc_bcm_voters); + +static const char * const bcm_voter_names[ICC_BCM_VOTER_MAX] = { + [ICC_BCM_VOTER_APPS] = "APPS", + [ICC_BCM_VOTER_DISP] = "DISP", + [ICC_BCM_VOTER_CAM0] = "CAM0", + [ICC_BCM_VOTER_CAM1] = "CAM1", + [ICC_BCM_VOTER_CAM2] = "CAM2", +}; + /** * struct bcm_voter - Bus Clock Manager voter * @dev: reference to the device that communicates with the BCM @@ -37,6 +48,7 @@ struct bcm_voter { struct list_head ws_list; struct list_head voter_node; u32 tcs_wait; + u32 voter_idx; }; static int cmp_vcd(void *priv, const struct list_head *a, const struct list_head *b) @@ -353,12 +365,27 @@ static int qcom_icc_bcm_voter_probe(struct platform_device *pdev) if (of_property_read_u32(np, "qcom,tcs-wait", &voter->tcs_wait)) voter->tcs_wait = QCOM_ICC_TAG_ACTIVE_ONLY; + /* + * This is the best guess we can make.. + * Not registering BCMs correctly would be gamebreaking anyway! + */ + if (of_property_read_u32(np, "qcom,bcm-voter-idx", &voter->voter_idx)) + voter->voter_idx = ICC_BCM_VOTER_APPS; + mutex_init(&voter->lock); INIT_LIST_HEAD(&voter->commit_list); INIT_LIST_HEAD(&voter->ws_list); mutex_lock(&bcm_voter_lock); - list_add_tail(&voter->voter_node, &bcm_voters); + /* Do not attempt to register BCMs with the same ID twice! */ + if (qcom_icc_bcm_voters[voter->voter_idx]) { + mutex_unlock(&bcm_voter_lock); + dev_err(&pdev->dev, "Attempted to overwrite %s BCM voter!\n", + bcm_voter_names[voter->voter_idx]); + return -EINVAL; + } + + qcom_icc_bcm_voters[voter->voter_idx] = voter; mutex_unlock(&bcm_voter_lock); return 0; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index fdb5e58e408b..53298148f24b 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -20,9 +20,9 @@ */ void qcom_icc_pre_aggregate(struct icc_node *node) { - size_t i; - struct qcom_icc_node *qn; struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + int i; qn = node->data; qp = to_qcom_provider(node->provider); @@ -33,7 +33,7 @@ void qcom_icc_pre_aggregate(struct icc_node *node) } for (i = 0; i < qn->num_bcms; i++) - qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]); + qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS], qn->bcms[i]); } EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate); @@ -95,7 +95,7 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) qp = to_qcom_provider(node->provider); - qcom_icc_bcm_voter_commit(qp->voter); + qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]); return 0; } @@ -167,6 +167,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct icc_provider *provider; struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; + struct device_node *bcm_node; struct icc_node *node; size_t num_nodes, i, j; int ret; @@ -200,9 +201,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) qp->bcms = desc->bcms; qp->num_bcms = desc->num_bcms; - qp->voter = of_bcm_voter_get(qp->dev, NULL); - if (IS_ERR(qp->voter)) - return PTR_ERR(qp->voter); + /* Ensure the BCM voter is reachable (unless we don't have any) */ + qp->voter = qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]; + if (qp->num_bcms && !qp->voter) + return -EPROBE_DEFER; for (i = 0; i < qp->num_bcms; i++) qcom_icc_bcm_init(qp->bcms[i], dev); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 7843d8864d6b..5634d302963a 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -88,6 +88,7 @@ struct qcom_icc_node { * communicating with RPMh * @list: used to link to other bcms when compiling lists for commit * @ws_list: used to keep track of bcms that may transition between wake/sleep + * @voter_idx: index of the BCM voter used to convey votes to AOSS * @num_nodes: total number of @num_nodes * @nodes: list of qcom_icc_nodes that this BCM encapsulates */ @@ -104,6 +105,7 @@ struct qcom_icc_bcm { struct bcm_db aux_data; struct list_head list; struct list_head ws_list; + u8 voter_idx; size_t num_nodes; struct qcom_icc_node *nodes[]; }; @@ -138,4 +140,6 @@ void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); int qcom_icc_rpmh_remove(struct platform_device *pdev); +extern struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX]; + #endif From patchwork Tue Jul 11 12:18:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp451647vqm; Tue, 11 Jul 2023 05:50:27 -0700 (PDT) X-Google-Smtp-Source: APBJJlH77C9803ftdkNq5s9ZHs5ymNVUfOgp5jGlj8zAtzwwj7ncabyk+Ke9ydigzPcyjWLzf2Uz X-Received: by 2002:a05:6871:b21:b0:1b7:2261:e5b3 with SMTP id fq33-20020a0568710b2100b001b72261e5b3mr6730833oab.31.1689079827229; Tue, 11 Jul 2023 05:50:27 -0700 (PDT) ARC-Seal: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:30 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:03 +0200 Subject: [PATCH 04/53] interconnect: qcom: icc-rpmh: Retire dead code MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-4-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2754; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6mcS5eZovBnK2nwqFQIK7RBsbNQhwBhsQk+oBWRxNK4=; b=3ESDmMghTA6TIXl1ds/z4EpMEk5yAVv8VC1Tp1dLP/zINjykK+fbVDiJIiARIDeqq+KEQrt8B nrdFX/8/EnIALZGZh9DZJCTIFG3oUiASEHts3K8O46uCivUgJ4qPqU7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128568961205265 X-GMAIL-MSGID: 1771128568961205265 of_bcm_voter_get is no longer necessary. Remove its ugly remnants. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.c | 46 ----------------------------------- drivers/interconnect/qcom/bcm-voter.h | 1 - 2 files changed, 47 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c index f8fbddb87e6b..0ce3874f60d2 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -16,7 +16,6 @@ #include "bcm-voter.h" #include "icc-rpmh.h" -static LIST_HEAD(bcm_voters); static DEFINE_MUTEX(bcm_voter_lock); struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX] = { }; @@ -182,51 +181,6 @@ static void tcs_list_gen(struct bcm_voter *voter, int bucket, } } -/** - * of_bcm_voter_get - gets a bcm voter handle from DT node - * @dev: device pointer for the consumer device - * @name: name for the bcm voter device - * - * This function will match a device_node pointer for the phandle - * specified in the device DT and return a bcm_voter handle on success. - * - * Returns bcm_voter pointer or ERR_PTR() on error. EPROBE_DEFER is returned - * when matching bcm voter is yet to be found. - */ -struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name) -{ - struct bcm_voter *voter = ERR_PTR(-EPROBE_DEFER); - struct bcm_voter *temp; - struct device_node *np, *node; - int idx = 0; - - if (!dev || !dev->of_node) - return ERR_PTR(-ENODEV); - - np = dev->of_node; - - if (name) { - idx = of_property_match_string(np, "qcom,bcm-voter-names", name); - if (idx < 0) - return ERR_PTR(idx); - } - - node = of_parse_phandle(np, "qcom,bcm-voters", idx); - - mutex_lock(&bcm_voter_lock); - list_for_each_entry(temp, &bcm_voters, voter_node) { - if (temp->np == node) { - voter = temp; - break; - } - } - mutex_unlock(&bcm_voter_lock); - - of_node_put(node); - return voter; -} -EXPORT_SYMBOL_GPL(of_bcm_voter_get); - /** * qcom_icc_bcm_voter_add - queues up the bcm nodes that require updates * @voter: voter that the bcms are being added to diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/qcom/bcm-voter.h index 0f64c0bab2c0..30b324fcb2ee 100644 --- a/drivers/interconnect/qcom/bcm-voter.h +++ b/drivers/interconnect/qcom/bcm-voter.h @@ -20,7 +20,6 @@ static struct qcom_icc_bcm _name = { \ .nodes = { __VA_ARGS__ }, \ } -struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name); void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm); int qcom_icc_bcm_voter_commit(struct bcm_voter *voter); From patchwork Tue Jul 11 12:18:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118472 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441093vqm; Tue, 11 Jul 2023 05:31:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlFZngcwV1zWUAaDDmu2xdSY3ghZQilBDd58+GVDNqzg3lmDWuQ1qjUqycodvbC+X9+nLgnh X-Received: by 2002:a17:903:11c9:b0:1a1:d54b:71df with SMTP id q9-20020a17090311c900b001a1d54b71dfmr21753612plh.0.1689078708386; Tue, 11 Jul 2023 05:31:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078708; cv=none; d=google.com; s=arc-20160816; b=M5+qwUJAoEIGXQLWzH1YdzIlEOPHMVC92Z2WC/8Olxmpei91kLyGpDG9Tz4pbdUwO9 ZwLZ/AigFOwayA4Wi2pbotFs6Q4H+8bV4yjLTmNiY2Bcq7tXr4dtsFZpUELzCtkudNLS TbmJFuEfJjE0LvbgL4R2Xv39aX8Ymm2zactPcJzsRYSEm1OUKaTfOQI7ddrWFGjC1699 Va6MjICCgtX98kbR3sbWA2LHnhrenvhSpTWKYo537BR35Qlt3SL4u7p0viFJCJU8fFKE PgZg12P82O/J+ndXN1jTODpXUQu89RmPEdI9GEi6R8egP/28zhPc8nCdLwe7O5eaQaly 1/Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=ccaHxWEA1SHNBLA/pJ32RMxAjEs2vftCpusuOqWZkaE=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=lMLOj4xICnPb9Hev+dqQTpJDdOPUzXWhaB18MZUSU2R+izZDbMn1bh3JXwvvVMMT1F fkjhqUUC8BSOTdjPzK3XjuOgtkhfsDO6Ejdgmm4j+VCnENgnNH8YURdzWebKrHcanTXK xGL53mytxeFda9Boe5LRVNpmXkf2nKItmDuHMgyHcNykz5ZaraUPbaMXMgEWSombRfOj OkMl2fQ5ou71Wm0X1L97WCvMAGWwZYU4T/pY9BFpHoUHTvKC4X/iZgtwuNOhNWHhAna9 Yeti+NaE9l9V4SRgppu5/4EPwchEjt/cBlGFby2Uql1w5vU0O8jJHvjCLfH8tsGHfeRe nuJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AAa407DA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:31 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:04 +0200 Subject: [PATCH 05/53] interconnect: qcom: icc-rpmh: Implement voting on non-APPS RSCs MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-5-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=3399; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qxa5myzMVst/ng/FRMS5QwwZ8ABXjqpOGI10XxQPCBc=; b=YTn8PsYOLKHdJ4Oifs+Jok/jlVwavascvy0uIPmwXcmQnyELG4gnpyZgozP0wLWdDR7INKJYf FKpv39ljyUsDLC8wn1QDYP1tm30T7i3e8mbyhY3odnYIh4XD9fY7ZnA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127395823918494 X-GMAIL-MSGID: 1771127395823918494 Linux can cast votes on resources through different RSCs (e.g. DISP). This can be done for many reasons, from latency to fine-grain on-SoC-power-grid management. With all the necessary bits in place, add the loops and ifs necessary to vote through different RSCs. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpmh.c | 49 ++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 53298148f24b..3cdd9106b0c0 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -22,6 +22,8 @@ void qcom_icc_pre_aggregate(struct icc_node *node) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; + struct qcom_icc_bcm *bcm; + int voter_idx; int i; qn = node->data; @@ -32,8 +34,17 @@ void qcom_icc_pre_aggregate(struct icc_node *node) qn->max_peak[i] = 0; } - for (i = 0; i < qn->num_bcms; i++) - qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS], qn->bcms[i]); + for (i = 0; i < qn->num_bcms; i++) { + bcm = qn->bcms[i]; + + /* Old and incomplete device trees may not specify all voters. */ + if (qcom_icc_bcm_voters[bcm->voter_idx]) + voter_idx = bcm->voter_idx; + else + voter_idx = ICC_BCM_VOTER_APPS; + + qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[voter_idx], bcm); + } } EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate); @@ -87,6 +98,7 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; struct icc_node *node; + int i, ret; if (!src) node = dst; @@ -95,7 +107,11 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) qp = to_qcom_provider(node->provider); - qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]); + for (i = 0; i < ICC_BCM_VOTER_MAX; i++) { + ret = qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[i]); + if (ret) + return ret; + } return 0; } @@ -168,6 +184,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; struct device_node *bcm_node; + u32 val, voter_count = 0; struct icc_node *node; size_t num_nodes, i, j; int ret; @@ -201,10 +218,28 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) qp->bcms = desc->bcms; qp->num_bcms = desc->num_bcms; - /* Ensure the BCM voter is reachable (unless we don't have any) */ - qp->voter = qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]; - if (qp->num_bcms && !qp->voter) - return -EPROBE_DEFER; + for (i = 0; i < ICC_BCM_VOTER_MAX; i++) { + bcm_node = of_parse_phandle(dev->of_node, "qcom,bcm-voters", voter_count); + if (!bcm_node) + break; + + voter_count++; + + ret = of_property_read_u32(bcm_node, "qcom,bcm-voter-idx", &val); + of_node_put(bcm_node); + /* Legacy DTs only ever referenced the APPS BCM voter */ + if (ret == -EINVAL) + val = ICC_BCM_VOTER_APPS; + else if (ret) + return ret; + + if (!qcom_icc_bcm_voters[val]) + return -EPROBE_DEFER; + } + + /* Let's not forget to add qcom,bcm-voters to the provider node! */ + if (qp->num_bcms && !voter_count) + return -EINVAL; for (i = 0; i < qp->num_bcms; i++) qcom_icc_bcm_init(qp->bcms[i], dev); From patchwork Tue Jul 11 12:18:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118462 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440009vqm; Tue, 11 Jul 2023 05:30:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlEyyeNpwAX3a2cuQSe/uo5rW72vzp2sjoeutDh0MQpe+Lrn/Ex6OBeV8UpvMWHDz6TdU5F3 X-Received: by 2002:a05:6358:41a3:b0:134:c682:213f with SMTP id w35-20020a05635841a300b00134c682213fmr13426469rwc.31.1689078618336; Tue, 11 Jul 2023 05:30:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078618; cv=none; d=google.com; s=arc-20160816; b=I8NGj7LP2iXXjrNYDyPhLsYY6T9XlHK3WTtGBVQBcCETT6SelJMuCmCVE/tDcFH5iF H2StP+ZNy1G1fzT6ySLfkgOphlnxvzrn0S+HsJRRHfbFfAYlnrVmhfD6yqMgsNBshBQ7 f9dMkh8SZDyukHlGU9KmzJdcCegGRxT2llrAaGPuUdgwoDQhjl/WcCQ9LpllPvSLPtaM lp/dkg6TodOR72c66VWytTTPHO+CBHnUSs+ZF8F/Suzg+iFwRtWdaLmyRUpZS+mZqAx/ zJZr83eNFjqSySkyF5UUWuaeaittJ6TuXWzhz0KhivasQElrn3YxzFZ9/SceULxEqgvQ HSgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=J9H8WmeBksbeh8NfCbg2+mLM/ZRxw9tuOAbuu8Kzagk=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=jR3M6QlpOZdjumDobo5o5Upf56yPPjg463zfoP1Mxr+bjPLs70fwD1VIcPvoOV3ZXi fkQbosUvg24ZBh+6xzOJowEViVS4oYDFJCqwoY4+nQunJKlLrn+kc5tpYt0dBWdkX9BG sdIt1CZ+lKINid3B5FxKlNa9kuNsDH3MB21PJzcIX8Z3xZZY0099cvGefHzHrWjZb28D c8ij8I+Bkb3wOxahUHvBysgdyErDuSH7U8P1ZO7KkC52J0Wf4G0/8Z7zR7n7OKdUyGeO CIpxURYrx2Hq0bilY+ZqCYb27mdtWd/b3Mcu/hPC6+3KzjUKDI6cvXixGmYZSRo6UQa9 bo0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z2l74bUh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:05 +0200 Subject: [PATCH 06/53] interconnect: qcom: sc7180: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-6-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=42545; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3HncnistFIjHOWYEogNMs1JXDdztHDQYLkYhd8ihntg=; b=BM4JmAz3ZkYFn2ZflIGGgiF4W0dM+uRy8eNZIGYWc+gCdGjBH4rOA0RkzW1x4E/OTx46wF/lY y1vXXAw1vHLD/P+S9Dhe5W/6nVMIbwZ+lntKyrwNBTOIbq9nH4845FU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127301331587481 X-GMAIL-MSGID: 1771127301331587481 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7180.c | 1356 ++++++++++++++++++++++++++++++++---- 1 file changed, 1219 insertions(+), 137 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index ef4e13fb4983..d1b0427f8781 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -15,143 +15,1225 @@ #include "icc-rpmh.h" #include "sc7180.h" -DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, -SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1); -DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC); -DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0); -DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1); -DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4); -DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SC7180_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SC7180_MASTER_QSPI, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_0 = { + .name = "qhm_qup_0", + .id = SC7180_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SC7180_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SC7180_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SC7180_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SC7180_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SC7180_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_1 = { + .name = "qhm_qup_1", + .id = SC7180_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SC7180_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SC7180_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SC7180_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_usb3 = { + .name = "qhm_usb3", + .id = SC7180_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SC7180_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SC7180_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp = { + .name = "qxm_npu_dsp", + .id = SC7180_MASTER_NPU_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SC7180_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SC7180_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SC7180_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_CFG, + SC7180_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps0 = { + .name = "acm_apps0", + .id = SC7180_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SC7180_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SC7180_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + SC7180_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SC7180_MASTER_COMPUTE_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SC7180_MASTER_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SC7180_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SC7180_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SC7180_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SC7180_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SC7180_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SC7180_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SC7180_MASTER_CAMNOC_HF0, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SC7180_MASTER_CAMNOC_HF1, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SC7180_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SC7180_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SC7180_MASTER_ROTATOR, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SC7180_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SC7180_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SC7180_MASTER_NPU_SYS, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg = { + .name = "qhm_npu_cfg", + .id = SC7180_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 8, + .links = { SC7180_SLAVE_NPU_CAL_DP0, + SC7180_SLAVE_NPU_CP, + SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_DPM, + SC7180_SLAVE_ISENSE_CFG, + SC7180_SLAVE_NPU_LLM_CFG, + SC7180_SLAVE_NPU_TCM, + SC7180_SLAVE_SERVICE_NPU_NOC + }, +}; + +static struct qcom_icc_node qup_core_master_1 = { + .name = "qup_core_master_1", + .id = SC7180_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup_core_master_2 = { + .name = "qup_core_master_2", + .id = SC7180_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SC7180_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SC7180_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SC7180_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SC7180_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SC7180_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC, + SC7180_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SC7180_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SC7180_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SC7180_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SC7180_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SC7180_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc = { + .name = "qns_cdsp_gemnoc", + .id = SC7180_SLAVE_CDSP_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SC7180_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SC7180_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SC7180_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SC7180_SLAVE_AHB2PHY_CENTER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SC7180_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SC7180_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .id = SC7180_SLAVE_BOOT_ROM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SC7180_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { + .name = "qhs_camera_nrt_throttle_cfg", + .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SC7180_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SC7180_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SC7180_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SC7180_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SC7180_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SC7180_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SC7180_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_rt_throttle_cfg = { + .name = "qhs_display_rt_throttle_cfg", + .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg = { + .name = "qhs_display_throttle_cfg", + .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SC7180_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SC7180_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SC7180_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SC7180_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SC7180_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SC7180_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SC7180_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SC7180_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { + .name = "qhs_npu_dma_throttle_cfg", + .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { + .name = "qhs_npu_dsp_throttle_cfg", + .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SC7180_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SC7180_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SC7180_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SC7180_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .id = SC7180_SLAVE_QM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .id = SC7180_SLAVE_QM_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SC7180_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SC7180_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SC7180_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SC7180_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SC7180_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SC7180_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SC7180_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_1 = { + .name = "qhs_tlmm_1", + .id = SC7180_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_2 = { + .name = "qhs_tlmm_2", + .id = SC7180_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_3 = { + .name = "qhs_tlmm_3", + .id = SC7180_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SC7180_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SC7180_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SC7180_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg = { + .name = "qhs_venus_throttle_cfg", + .id = SC7180_SLAVE_VENUS_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SC7180_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SC7180_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gemnoc = { + .name = "qhs_gemnoc", + .id = SC7180_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SC7180_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SC7180_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SC7180_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SC7180_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SC7180_SLAVE_EBI1, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SC7180_SLAVE_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SC7180_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SC7180_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SC7180_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SC7180_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SC7180_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SC7180_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SC7180_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SC7180_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SC7180_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SC7180_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup_core_slave_1 = { + .name = "qup_core_slave_1", + .id = SC7180_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup_core_slave_2 = { + .name = "qup_core_slave_2", + .id = SC7180_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SC7180_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SC7180_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SC7180_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SC7180_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SC7180_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SC7180_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SC7180_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SC7180_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SC7180_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); From patchwork Tue Jul 11 12:18:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118458 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp439814vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:34 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:06 +0200 Subject: [PATCH 07/53] interconnect: qcom: sdm670: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-7-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=34748; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=V+MGY6LePTTXD4nJ5soCKBGeCOExkcBtc/T6Gwor5mI=; b=2xqpXi14JeM5h01URD74UzsoKGBByAcM1I9rKvXkXVQMG3GyPUsPuXSZozncT/6FLtFx0c1dY RDwPssB6d1QDAen4IUdD5vriLaMYnzT0JLY2HwxsOKYvpdvZlpf8cPH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127283246551186 X-GMAIL-MSGID: 1771127283246551186 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm670.c | 1145 ++++++++++++++++++++++++++++++++---- 1 file changed, 1029 insertions(+), 116 deletions(-) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index bda955035518..2c2cbe1b5197 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -14,122 +14,1035 @@ #include "icc-rpmh.h" #include "sdm670.h" -DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SDM670_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SDM670_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SDM670_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SDM670_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SDM670_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDM670_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SDM670_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SDM670_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDM670_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SDM670_MASTER_BLSP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDM670_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDM670_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDM670_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDM670_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SDM670_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SDM670_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SDM670_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SDM670_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 38, + .links = { SDM670_SLAVE_TLMM_SOUTH, + SDM670_SLAVE_CAMERA_CFG, + SDM670_SLAVE_SDCC_4, + SDM670_SLAVE_SDCC_2, + SDM670_SLAVE_CNOC_MNOC_CFG, + SDM670_SLAVE_UFS_MEM_CFG, + SDM670_SLAVE_GLM, + SDM670_SLAVE_PDM, + SDM670_SLAVE_A2NOC_CFG, + SDM670_SLAVE_QDSS_CFG, + SDM670_SLAVE_DISPLAY_CFG, + SDM670_SLAVE_TCSR, + SDM670_SLAVE_DCC_CFG, + SDM670_SLAVE_CNOC_DDRSS, + SDM670_SLAVE_SNOC_CFG, + SDM670_SLAVE_SOUTH_PHY_CFG, + SDM670_SLAVE_GRAPHICS_3D_CFG, + SDM670_SLAVE_VENUS_CFG, + SDM670_SLAVE_TSIF, + SDM670_SLAVE_CDSP_CFG, + SDM670_SLAVE_AOP, + SDM670_SLAVE_BLSP_2, + SDM670_SLAVE_SERVICE_CNOC, + SDM670_SLAVE_USB3, + SDM670_SLAVE_IPA_CFG, + SDM670_SLAVE_RBCPR_CX_CFG, + SDM670_SLAVE_A1NOC_CFG, + SDM670_SLAVE_AOSS, + SDM670_SLAVE_PRNG, + SDM670_SLAVE_VSENSE_CTRL_CFG, + SDM670_SLAVE_EMMC_CFG, + SDM670_SLAVE_BLSP_1, + SDM670_SLAVE_SPDM_WRAPPER, + SDM670_SLAVE_CRYPTO_0_CFG, + SDM670_SLAVE_PIMEM_CFG, + SDM670_SLAVE_TLMM_NORTH, + SDM670_SLAVE_CLK_CTL, + SDM670_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc = { + .name = "qhm_cnoc", + .id = SDM670_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM670_SLAVE_MEM_NOC_CFG, + SDM670_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 = { + .name = "acm_l3", + .id = SDM670_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDM670_SLAVE_SERVICE_GNOC, + SDM670_SLAVE_GNOC_SNOC, + SDM670_SLAVE_GNOC_MEM_NOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg = { + .name = "pm_gnoc_cfg", + .id = SDM670_MASTER_GNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDM670_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDM670_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg = { + .name = "qhm_memnoc_cfg", + .id = SDM670_MASTER_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM670_SLAVE_SERVICE_MEM_NOC, + SDM670_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_apps = { + .name = "qnm_apps", + .id = SDM670_MASTER_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SDM670_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SDM670_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDM670_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDM670_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SDM670_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SDM670_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SDM670_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SDM670_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SDM670_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SDM670_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SDM670_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SDM670_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SDM670_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SDM670_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SDM670_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDM670_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SDM670_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SDM670_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv = { + .name = "qnm_gladiator_sodv", + .id = SDM670_MASTER_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDM670_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SDM670_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDM670_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SDM670_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SDM670_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SDM670_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SDM670_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SDM670_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SDM670_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SDM670_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDM670_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDM670_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SDM670_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDM670_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg = { + .name = "qhs_compute_dsp_cfg", + .id = SDM670_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SDM670_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDM670_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SDM670_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDM670_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SDM670_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SDM670_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SDM670_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SDM670_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDM670_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDM670_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SDM670_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDM670_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south = { + .name = "qhs_phy_refgen_south", + .id = SDM670_SLAVE_SOUTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SDM670_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDM670_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDM670_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SDM670_SLAVE_BLSP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SDM670_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SDM670_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDM670_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDM670_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SDM670_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDM670_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SDM670_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SDM670_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SDM670_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SDM670_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SDM670_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SDM670_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SDM670_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SDM670_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SDM670_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SDM670_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SDM670_SLAVE_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv = { + .name = "qns_gladiator_sodv", + .id = SDM670_SLAVE_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc = { + .name = "qns_gnoc_memnoc", + .id = SDM670_SLAVE_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc = { + .name = "srvc_gnoc", + .id = SDM670_SLAVE_SERVICE_GNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDM670_SLAVE_EBI_CH0, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apps_io = { + .name = "qns_apps_io", + .id = SDM670_SLAVE_MEM_NOC_GNOC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDM670_SLAVE_LLCC, + .channels = 2, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDM670_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc = { + .name = "srvc_memnoc", + .id = SDM670_SLAVE_SERVICE_MEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SDM670_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SDM670_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SDM670_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDM670_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SDM670_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc = { + .name = "qns_memnoc_gc", + .id = SDM670_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf = { + .name = "qns_memnoc_sf", + .id = SDM670_SLAVE_SNOC_MEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDM670_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SDM670_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDM670_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDM670_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDM670_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); From patchwork Tue Jul 11 12:18:07 2023 Content-Type: text/plain; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:36 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:07 +0200 Subject: [PATCH 08/53] interconnect: qcom: sdm845: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-8-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=43630; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KNfiEgG3TyzMX9xEccJ89zpUneCkvrGmifaqFWTB5ZU=; b=O8I/wugUASx/V7NKMfFLfXKCCu/uhyHiC1vZLkjvDjANzR0ZDXqW8lhpkEsHjpLEgPD4ZU8xJ L4ozSoWtzQJAYhIkizhYFUcmQbbB7n+wNFzAPH1j891XgRU0KERvgVm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127663574058179 X-GMAIL-MSGID: 1771127663574058179 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm845.c | 1376 ++++++++++++++++++++++++++++++++---- 1 file changed, 1246 insertions(+), 130 deletions(-) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 954e7bd13fc4..5caf6e5aeeca 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -15,136 +15,1252 @@ #include "icc-rpmh.h" #include "sdm845.h" -DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CF G, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_ CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENS E_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG); -DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC); -DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); -DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); -DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); -DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0); -DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); -DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SDM845_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SDM845_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SDM845_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SDM845_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDM845_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SDM845_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SDM845_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie_0 = { + .name = "xm_pcie_0", + .id = SDM845_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SDM845_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDM845_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SDM845_MASTER_BLSP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDM845_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDM845_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDM845_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SDM845_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDM845_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SDM845_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SDM845_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SDM845_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SDM845_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qhm_tic = { + .name = "qhm_tic", + .id = SDM845_MASTER_TIC, + .channels = 1, + .buswidth = 4, + .num_links = 43, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SDM845_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SDM845_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 43, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc = { + .name = "qhm_cnoc", + .id = SDM845_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM845_SLAVE_LLCC_CFG, + SDM845_SLAVE_MEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 = { + .name = "acm_l3", + .id = SDM845_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDM845_SLAVE_GNOC_SNOC, + SDM845_SLAVE_GNOC_MEM_NOC, + SDM845_SLAVE_SERVICE_GNOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg = { + .name = "pm_gnoc_cfg", + .id = SDM845_MASTER_GNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDM845_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDM845_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg = { + .name = "qhm_memnoc_cfg", + .id = SDM845_MASTER_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + SDM845_SLAVE_SERVICE_MEM_NOC + }, +}; + +static struct qcom_icc_node qnm_apps = { + .name = "qnm_apps", + .id = SDM845_MASTER_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SDM845_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SDM845_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDM845_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDM845_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SDM845_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SDM845_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SDM845_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SDM845_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SDM845_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SDM845_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SDM845_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SDM845_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SDM845_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SDM845_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SDM845_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDM845_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SDM845_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SDM845_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 9, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv = { + .name = "qnm_gladiator_sodv", + .id = SDM845_MASTER_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 8, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDM845_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_pcie_anoc = { + .name = "qnm_pcie_anoc", + .id = SDM845_MASTER_ANOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 5, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SDM845_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDM845_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SDM845_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SDM845_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { 0 }, +}; + +static struct qcom_icc_node qns_pcie_a1noc_snoc = { + .name = "qns_pcie_a1noc_snoc", + .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SDM845_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_snoc = { + .name = "qns_pcie_snoc", + .id = SDM845_SLAVE_ANOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SDM845_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SDM845_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SDM845_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SDM845_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDM845_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDM845_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SDM845_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDM845_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg = { + .name = "qhs_compute_dsp_cfg", + .id = SDM845_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SDM845_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDM845_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SDM845_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDM845_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SDM845_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SDM845_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SDM845_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDM845_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDM845_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SDM845_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SDM845_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_gen3_cfg = { + .name = "qhs_pcie_gen3_cfg", + .id = SDM845_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDM845_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south = { + .name = "qhs_phy_refgen_south", + .id = SDM845_SLAVE_SOUTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SDM845_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDM845_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDM845_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SDM845_SLAVE_BLSP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SDM845_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SDM845_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDM845_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDM845_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SDM845_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SDM845_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDM845_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SDM845_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SDM845_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SDM845_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SDM845_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SDM845_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SDM845_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SDM845_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SDM845_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SDM845_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SDM845_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SDM845_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SDM845_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SDM845_SLAVE_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv = { + .name = "qns_gladiator_sodv", + .id = SDM845_SLAVE_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc = { + .name = "qns_gnoc_memnoc", + .id = SDM845_SLAVE_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc = { + .name = "srvc_gnoc", + .id = SDM845_SLAVE_SERVICE_GNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDM845_SLAVE_EBI1, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apps_io = { + .name = "qns_apps_io", + .id = SDM845_SLAVE_MEM_NOC_GNOC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDM845_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDM845_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc = { + .name = "srvc_memnoc", + .id = SDM845_SLAVE_SERVICE_MEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SDM845_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SDM845_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SDM845_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDM845_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SDM845_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc = { + .name = "qns_memnoc_gc", + .id = SDM845_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf = { + .name = "qns_memnoc_sf", + .id = SDM845_SLAVE_SNOC_MEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDM845_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pcie = { + .name = "qxs_pcie", + .id = SDM845_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pcie_gen3 = { + .name = "qxs_pcie_gen3", + .id = SDM845_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SDM845_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDM845_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDM845_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDM845_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; From patchwork Tue Jul 11 12:18:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118448 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp434598vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:37 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:08 +0200 Subject: [PATCH 09/53] interconnect: qcom: sdx55: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-9-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=22083; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DfvVOVIJtBrOMDPH5uxDCesHNBsdiS2Js6MQ8bXhn3w=; b=eT0LvUJhmLKsKNSJml7cLtTJ25fwA5ZUjjQXGVbYrJ9bR2dWLhT4vlK4FMuFijkpTq2D50mOh hv2kBcQRx9QCjUMYaVQBlkk/HC4/kOEGkW10lPE0xHV+5LMWnLS4WY1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126689231020776 X-GMAIL-MSGID: 1771126689231020776 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx55.c | 681 ++++++++++++++++++++++++++++++++++---- 1 file changed, 623 insertions(+), 58 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 130a828c3873..2b5e8873eaa5 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -18,64 +18,629 @@ #include "icc-rpmh.h" #include "sdx55.h" -DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0); -DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4); -DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8); +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX55_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDX55_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDX55_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr = { + .name = "xm_apps_rdwr", + .id = SDX55_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX55_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 = { + .name = "qhm_blsp1", + .id = SDX55_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX55_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 28, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX55_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 5, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDX55_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 = { + .name = "qhm_spmi_fetcher1", + .id = SDX55_MASTER_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX55_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 30, + .links = { SDX55_SLAVE_PCIE_0, + SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_USB3, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_ipa = { + .name = "qnm_ipa", + .id = SDX55_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 27, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDX55_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 29, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie = { + .name = "qnm_memnoc_pcie", + .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX55_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node xm_emac = { + .name = "xm_emac", + .id = SDX55_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv = { + .name = "xm_ipa2pcie_slv", + .id = SDX55_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .id = SDX55_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDX55_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 28, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX55_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX55_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX55_SLAVE_EBI_CH0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX55_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDX55_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDX55_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDX55_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDX55_SLAVE_APPSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX55_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_blsp1 = { + .name = "qhs_blsp1", + .id = SDX55_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX55_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDX55_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDX55_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg = { + .name = "qhs_ecc_cfg", + .id = SDX55_SLAVE_ECC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac_cfg = { + .name = "qhs_emac_cfg", + .id = SDX55_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX55_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX55_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX55_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_parf = { + .name = "qhs_pcie_parf", + .id = SDX55_SLAVE_PCIE_PARF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX55_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX55_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX55_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX55_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX55_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDX55_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher = { + .name = "qhs_spmi_fetcher", + .id = SDX55_SLAVE_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX55_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX55_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX55_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX55_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX55_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_aggre_noc = { + .name = "qns_aggre_noc", + .id = SDX55_SLAVE_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc = { + .name = "qns_snoc_memnoc", + .id = SDX55_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX55_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDX55_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .id = SDX55_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX55_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX55_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); From patchwork Tue Jul 11 12:18:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118473 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441241vqm; Tue, 11 Jul 2023 05:32:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlFmE4+drnj207GugAIULe3kiz1CqLspPedX88Aorl/yOccrzsPZjFgSZ4TvANuY4KeW8DIN X-Received: by 2002:a17:902:d312:b0:1b8:b46d:91b7 with SMTP id b18-20020a170902d31200b001b8b46d91b7mr12576819plc.45.1689078721600; Tue, 11 Jul 2023 05:32:01 -0700 (PDT) ARC-Seal: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:39 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:09 +0200 Subject: [PATCH 10/53] interconnect: qcom: sdx65: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-10-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=20861; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Atb806ycN2p4ZV3kQEetNQMYYysNjcCZbT7AH3nl6w0=; b=h3fQTqSs52o/JOpIqVi3C5ad1i5Fhw2YHzPt9XKqy0iG4IfGtHdU4Bt3LSr8CtD4Uka0SKTn5 GYMw65afihsCsW9mJSeiqEPKxu3TN8C2hBy4r2sMh/6r5fK+5RAL8Ui X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127409568178478 X-GMAIL-MSGID: 1771127409568178478 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx65.c | 643 ++++++++++++++++++++++++++++++++++---- 1 file changed, 588 insertions(+), 55 deletions(-) diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index b16d31d53e9b..bebed036fe7a 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -14,61 +14,594 @@ #include "icc-rpmh.h" #include "sdx65.h" -DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0); -DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); -DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); -DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX65_MASTER_LLCC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDX65_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDX65_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr = { + .name = "xm_apps_rdwr", + .id = SDX65_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX65_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 = { + .name = "qhm_blsp1", + .id = SDX65_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX65_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX65_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 4, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDX65_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 = { + .name = "qhm_spmi_fetcher1", + .id = SDX65_MASTER_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX65_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 29, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_ipa = { + .name = "qnm_ipa", + .id = SDX65_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDX65_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 27, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie = { + .name = "qnm_memnoc_pcie", + .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX65_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv = { + .name = "xm_ipa2pcie_slv", + .id = SDX65_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .id = SDX65_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDX65_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX65_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 4, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX65_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX65_SLAVE_EBI1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX65_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDX65_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDX65_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDX65_SLAVE_APPSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX65_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_blsp1 = { + .name = "qhs_blsp1", + .id = SDX65_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX65_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDX65_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDX65_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg = { + .name = "qhs_ecc_cfg", + .id = SDX65_SLAVE_ECC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX65_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX65_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX65_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_parf = { + .name = "qhs_pcie_parf", + .id = SDX65_SLAVE_PCIE_PARF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX65_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX65_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX65_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX65_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX65_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDX65_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher = { + .name = "qhs_spmi_fetcher", + .id = SDX65_SLAVE_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX65_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX65_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX65_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX65_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX65_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_aggre_noc = { + .name = "qns_aggre_noc", + .id = SDX65_SLAVE_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc = { + .name = "qns_snoc_memnoc", + .id = SDX65_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX65_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDX65_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .id = SDX65_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX65_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX65_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); From patchwork Tue Jul 11 12:18:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118469 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441057vqm; Tue, 11 Jul 2023 05:31:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlEjMsp9rb+8dpden3cGZ7FzB1Vt8BHJGMWlQbxQxy7lSUt7tnmOJmTiOxMoMRRRJhkFvdnT X-Received: by 2002:a17:902:bb89:b0:1b0:f727:bc41 with SMTP id m9-20020a170902bb8900b001b0f727bc41mr10654947pls.42.1689078704892; Tue, 11 Jul 2023 05:31:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078704; cv=none; d=google.com; s=arc-20160816; b=bTozswNwKiPBKCJ4YnYb4/hytvIiL2jLWBHX+xlH04QG0mue/6WiardGDS8DGMtEq0 XLywseJ5Zi9i26AeKb9hxx8TdpoA8t6ocY0H7RNooy+X5GVfn8vrxsTqYqCFcIbLNkVf 5OCCH4qhIVhQ2aljkuu0yQ9Ub+1pD9ykmKsTrBih9+JnKSFo6VtLV+a3Kwu7IpIwwKV/ IpGVya8Z804zPOwdgSrhkbaN+YjRGSiLFoYCwviCJNDh8+C0wssu5MnPhdNFB7IHmjQP yeDiHOWo4hlxGbyALUYz+q9QC+d8KTGdK1QGhQrJ2FLi3nhQlCvDWGT7u/Hx9feTkhWc Z8uw== ARC-Message-Signature: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:40 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:10 +0200 Subject: [PATCH 11/53] interconnect: qcom: sm6350: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-11-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=39658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Vn2Dl/Zh9To6jL368CWOwQ/9G+yXzmEWxN811xRUl7w=; b=jTY8FGQBDJ6+bvx3jOIgPc97Y9WS7ggW4CD1BvtS0I8w0tjtiXJhYoG02YfJRyoBasAbPSjIk wj26hmOA5EMAoSWzmGloh/1ysJN/Vn2S4McKWsOLHlLKBXf5aaL/i89 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127392255592219 X-GMAIL-MSGID: 1771127392255592219 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm6350.c | 1273 ++++++++++++++++++++++++++++++++---- 1 file changed, 1146 insertions(+), 127 deletions(-) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index a3d46e59444e..7421eb4cd520 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -14,133 +14,1152 @@ #include "icc-rpmh.h" #include "sm6350.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0); -DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1); -DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_S LAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6 350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); -DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM6350_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup_0 = { + .name = "qhm_qup_0", + .id = SM6350_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SM6350_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM6350_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM6350_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM6350_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup_1 = { + .name = "qhm_qup_1", + .id = SM6350_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM6350_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM6350_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM6350_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM6350_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM6350_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_icp_uncomp = { + .name = "qxm_camnoc_icp_uncomp", + .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SM6350_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM6350_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM6350_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM6350_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp = { + .name = "qxm_npu_dsp", + .id = SM6350_MASTER_NPU_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM6350_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM6350_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM6350_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC_CFG, + SM6350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_apps = { + .name = "acm_apps", + .id = SM6350_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SM6350_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM6350_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG, + SM6350_SLAVE_SERVICE_GEM_NOC, + SM6350_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM6350_MASTER_COMPUTE_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM6350_MASTER_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM6350_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM6350_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM6350_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SM6350_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM6350_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM6350_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM6350_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM6350_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf = { + .name = "qxm_camnoc_hf", + .id = SM6350_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_icp = { + .name = "qxm_camnoc_icp", + .id = SM6350_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SM6350_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM6350_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SM6350_MASTER_NPU_SYS, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg = { + .name = "qhm_npu_cfg", + .id = SM6350_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 8, + .links = { SM6350_SLAVE_SERVICE_NPU_NOC, + SM6350_SLAVE_ISENSE_CFG, + SM6350_SLAVE_NPU_LLM_CFG, + SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM6350_SLAVE_NPU_CP, + SM6350_SLAVE_NPU_TCM, + SM6350_SLAVE_NPU_CAL_DP0, + SM6350_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM6350_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM6350_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM6350_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM6350_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM6350_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC, + SM6350_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM6350_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM6350_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM6350_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM6350_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM6350_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SM6350_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM6350_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM6350_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc = { + .name = "qns_cdsp_gemnoc", + .id = SM6350_SLAVE_CDSP_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM6350_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM6350_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM6350_SLAVE_AHB2PHY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SM6350_SLAVE_AHB2PHY_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM6350_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .id = SM6350_SLAVE_BOOT_ROM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM6350_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { + .name = "qhs_camera_nrt_thrott_cfg", + .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM6350_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM6350_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM6350_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM6350_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM6350_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM6350_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM6350_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg = { + .name = "qhs_display_throttle_cfg", + .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SM6350_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SM6350_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM6350_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM6350_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM6350_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM6350_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SM6350_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM6350_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM6350_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM6350_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM6350_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM6350_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .id = SM6350_SLAVE_QM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .id = SM6350_SLAVE_QM_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM6350_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM6350_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM6350_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SM6350_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM6350_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM6350_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM6350_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM6350_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM6350_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg = { + .name = "qhs_venus_throttle_cfg", + .id = SM6350_SLAVE_VENUS_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM6350_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM6350_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gemnoc = { + .name = "qhs_gemnoc", + .id = SM6350_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM6350_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { + .name = "qhs_mcdma_ms_mpu_cfg", + .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM6350_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM6350_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SM6350_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM6350_SLAVE_EBI_CH0, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM6350_SLAVE_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM6350_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM6350_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SM6350_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SM6350_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SM6350_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SM6350_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SM6350_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SM6350_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SM6350_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SM6350_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM6350_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM6350_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM6350_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM6350_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM6350_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM6350_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM6350_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM6350_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM6350_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:11 +0200 Subject: [PATCH 12/53] interconnect: qcom: sm8150: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-12-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=43197; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KfeJu81yzM9UtZk6tkFn5rt1KeKxy7YZJdapT6RtiNw=; b=T8eC75GAZGawcHThG7JAbyPR4AmdmaoW8EFm/joEvmxnDDGfl888D7MR5q96nD7rk7l8HkAu1 ciO7wLacAWOB6/b+0WKlSa2N3GcscOr0fn9I/hrc1p+Cydc2QUslnxb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127585303394511 X-GMAIL-MSGID: 1771127585303394511 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8150.c | 1401 ++++++++++++++++++++++++++++++++---- 1 file changed, 1263 insertions(+), 138 deletions(-) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index c5ab29322164..29f16899cf5d 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -15,144 +15,1269 @@ #include "icc-rpmh.h" #include "sm8150.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150 _SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_ CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4); -DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32); -DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM8150_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8150_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emac = { + .name = "xm_emac", + .id = SM8150_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8150_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8150_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8150_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM8150_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8150_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8150_MASTER_QSPI, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8150_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8150_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_sensorss_ahb = { + .name = "qhm_sensorss_ahb", + .id = SM8150_MASTER_SENSORS_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SM8150_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SM8150_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8150_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8150_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8150_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8150_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8150_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8150_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8150_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SM8150_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM8150_MASTER_NPU, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SM8150_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM8150_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 50, + .links = { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8150_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_CNOC_A2NOC, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM8150_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8150_SLAVE_GEM_NOC_CFG, + SM8150_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps = { + .name = "acm_apps", + .id = SM8150_MASTER_AMPSS_M0, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_gpu_tcu = { + .name = "acm_gpu_tcu", + .id = SM8150_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SM8150_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM8150_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8150_SLAVE_SERVICE_GEM_NOC, + SM8150_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8150_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8150_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8150_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8150_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8150_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8150_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_ecc = { + .name = "qxm_ecc", + .id = SM8150_MASTER_ECC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8150_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM8150_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SM8150_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SM8150_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SM8150_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8150_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8150_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8150_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SM8150_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SM8150_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SM8150_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM8150_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8150_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8150_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 9, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_PCIE_0, + SM8150_SLAVE_PCIE_1, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM8150_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8150_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8150_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8150_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8150_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8150_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8150_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SM8150_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc = { + .name = "qns_cdsp_mem_noc", + .id = SM8150_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM8150_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM8150_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy_south = { + .name = "qhs_ahb2phy_south", + .id = SM8150_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SM8150_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8150_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8150_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8150_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp = { + .name = "qhs_compute_dsp", + .id = SM8150_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8150_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8150_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8150_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8150_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM8150_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8150_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac_cfg = { + .name = "qhs_emac_cfg", + .id = SM8150_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SM8150_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8150_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8150_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8150_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM8150_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM8150_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8150_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8150_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_north = { + .name = "qhs_phy_refgen_north", + .id = SM8150_SLAVE_NORTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8150_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM8150_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8150_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8150_SLAVE_QSPI, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_east = { + .name = "qhs_qupv3_east", + .id = SM8150_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SM8150_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SM8150_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8150_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8150_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM8150_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SM8150_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SM8150_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ssc_cfg = { + .name = "qhs_ssc_cfg", + .id = SM8150_SLAVE_SSC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8150_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_east = { + .name = "qhs_tlmm_east", + .id = SM8150_SLAVE_TLMM_EAST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SM8150_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SM8150_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_west = { + .name = "qhs_tlmm_west", + .id = SM8150_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SM8150_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8150_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8150_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8150_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8150_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8150_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8150_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SM8150_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8150_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8150_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SM8150_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ecc = { + .name = "qns_ecc", + .id = SM8150_SLAVE_ECC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM8150_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8150_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SM8150_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8150_SLAVE_EBI_CH0, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SM8150_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8150_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8150_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8150_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM8150_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8150_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8150_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8150_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8150_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8150_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8150_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8150_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8150_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8150_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; From patchwork Tue Jul 11 12:18:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118471 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441062vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:43 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:12 +0200 Subject: [PATCH 13/53] interconnect: qcom: sm8250: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-13-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=45391; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hGYe0N70rDnwja5IvQO5Zqf0PStSfBajeNCnSM/xFtE=; b=RZw7sBl2WvUUvAH8S24zwPS3RmO8L4FVLPaEZqvEbSsDrREvWN0KTwXs54wHBbGHaXFc1/ZX6 rMGuTbnII1cAkfn8XXAOTfUZK2Z1vZr6/OuM0XXdoMUycC2DDGKRVGe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127392860935527 X-GMAIL-MSGID: 1771127392860935527 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8250.c | 1478 ++++++++++++++++++++++++++++++++---- 1 file changed, 1330 insertions(+), 148 deletions(-) static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index d3d0196902cd..d4123799c2c6 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -15,154 +15,1336 @@ #include "icc-rpmh.h" #include "sm8250.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1); -DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_ PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM 8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1); -DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC); -DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4); -DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM8250_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8250_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8250_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8250_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SM8250_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_modem = { + .name = "xm_pcie3_modem", + .id = SM8250_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8250_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8250_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8250_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8250_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM8250_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8250_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8250_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SM8250_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8250_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8250_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8250_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8250_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8250_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8250_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SM8250_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM8250_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM8250_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 49, + .links = { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8250_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 50, + .links = { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_CNOC_A2NOC, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM8250_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8250_SLAVE_GEM_NOC_CFG, + SM8250_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SM8250_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SM8250_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SM8250_MASTER_AMPSS_M0, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM8250_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SM8250_SLAVE_SERVICE_GEM_NOC_2, + SM8250_SLAVE_SERVICE_GEM_NOC_1, + SM8250_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8250_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8250_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8250_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8250_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8250_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8250_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8250_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8250_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM8250_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SM8250_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SM8250_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SM8250_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM8250_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SM8250_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM8250_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8250_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8250_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8250_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SM8250_MASTER_NPU_SYS, + .channels = 4, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys_cdp_w = { + .name = "amm_npu_sys_cdp_w", + .id = SM8250_MASTER_NPU_CDP, + .channels = 2, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_cfg = { + .name = "qhm_cfg", + .id = SM8250_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 9, + .links = { SM8250_SLAVE_SERVICE_NPU_NOC, + SM8250_SLAVE_ISENSE_CFG, + SM8250_SLAVE_NPU_LLM_CFG, + SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM8250_SLAVE_NPU_CP, + SM8250_SLAVE_NPU_TCM, + SM8250_SLAVE_NPU_CAL_DP0, + SM8250_SLAVE_NPU_CAL_DP1, + SM8250_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM8250_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8250_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8250_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM8250_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM8250_SLAVE_PIMEM, + SM8250_SLAVE_OCIMEM, + SM8250_SLAVE_APPSS, + SM8250_SNOC_CNOC_SLV, + SM8250_SLAVE_TCU, + SM8250_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SM8250_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SM8250_SLAVE_PCIE_2, + SM8250_SLAVE_PCIE_0, + SM8250_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8250_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8250_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8250_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_modem_mem_noc = { + .name = "qns_pcie_modem_mem_noc", + .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8250_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8250_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8250_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc = { + .name = "qns_cdsp_mem_noc", + .id = SM8250_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM8250_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM8250_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM8250_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SM8250_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8250_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8250_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8250_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp = { + .name = "qhs_compute_dsp", + .id = SM8250_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8250_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8250_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8250_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8250_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SM8250_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM8250_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM8250_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8250_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8250_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8250_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8250_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SM8250_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SM8250_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM8250_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM8250_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8250_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8250_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_modem_cfg = { + .name = "qhs_pcie_modem_cfg", + .id = SM8250_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM8250_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8250_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM8250_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8250_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8250_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM8250_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM8250_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SM8250_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8250_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8250_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM8250_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8250_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm0 = { + .name = "qhs_tlmm0", + .id = SM8250_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm1 = { + .name = "qhs_tlmm1", + .id = SM8250_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm2 = { + .name = "qhs_tlmm2", + .id = SM8250_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SM8250_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8250_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8250_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8250_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8250_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8250_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8250_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SM8250_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8250_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8250_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SM8250_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM8250_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8250_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8250_SLAVE_EBI_CH0, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8250_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM8250_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8250_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SM8250_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp1 = { + .name = "qhs_cal_dp1", + .id = SM8250_SLAVE_NPU_CAL_DP1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SM8250_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SM8250_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SM8250_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SM8250_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SM8250_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SM8250_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SM8250_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8250_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM8250_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8250_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8250_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8250_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8250_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8250_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8250_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8250_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_modem = { + .name = "xs_pcie_modem", + .id = SM8250_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8250_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8250_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:45 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:13 +0200 Subject: [PATCH 14/53] interconnect: qcom: sm8350: Retire DEFINE_QNODE MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-14-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=46347; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=MBUJBtasIyeZJQqHT2qf34XR17jseRqW+X62JXRRHOs=; b=v8UyoAvE9jr47XwqXZz+UnNUTdHabx8f9JPCwg05MvNvnfgRc0p06D2TS4s7ziu0Fh/g91nma 4+sIDjgvk/DCRjc1ueXF5qIIfdbqnnoxxwu4S6E9YoPkl6vzOzSSgpA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126708081010996 X-GMAIL-MSGID: 1771126708081010996 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 1488 ++++++++++++++++++++++++++++++++---- 1 file changed, 1338 insertions(+), 150 deletions(-) DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 5398e7c8d826..859549b176c8 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -14,156 +14,1344 @@ #include "icc-rpmh.h" #include "sm8350.h" -DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_C FG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1); -DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM835 0_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); -DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC); -DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1); -DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC); -DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP); -DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP); -DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC); -DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4); -DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4); -DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4); -DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4); -DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4); -DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8); -DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8); -DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC); -DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC); -DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8); -DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4); -DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4); -DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC); -DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4); -DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP); -DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP); +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8350_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8350_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8350_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8350_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg = { + .name = "qnm_a1noc_cfg", + .id = SM8350_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8350_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8350_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8350_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8350_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8350_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg = { + .name = "qnm_a2noc_cfg", + .id = SM8350_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8350_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8350_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8350_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8350_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8350_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8350_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SM8350_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SM8350_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 56, + .links = { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_PCIE_0, + SM8350_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8350_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 56, + .links = { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .id = SM8350_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8350_SLAVE_LLCC_CFG, + SM8350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SM8350_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SM8350_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SM8350_MASTER_APPSS_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8350_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SM8350_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 5, + .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + SM8350_SLAVE_MCDMA_MS_MPU_CFG, + SM8350_SLAVE_SERVICE_GEM_NOC_1, + SM8350_SLAVE_SERVICE_GEM_NOC_2, + SM8350_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8350_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8350_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8350_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8350_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8350_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = SM8350_MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 6, + .links = { SM8350_SLAVE_LPASS_CORE_CFG, + SM8350_SLAVE_LPASS_LPI_CFG, + SM8350_SLAVE_LPASS_MPU_CFG, + SM8350_SLAVE_LPASS_TOP_CFG, + SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + SM8350_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8350_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SM8350_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SM8350_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SM8350_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .id = SM8350_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM8350_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SM8350_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM8350_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8350_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8350_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8350_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = SM8350_MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = SM8350_MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8350_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8350_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = SM8350_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8350_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8350_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_disp = { + .name = "qnm_mnoc_hf_disp", + .id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_disp = { + .name = "qnm_mnoc_sf_disp", + .id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node llcc_mc_disp = { + .name = "llcc_mc_disp", + .id = SM8350_MASTER_LLCC_DISP, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_EBI1_DISP }, +}; + +static struct qcom_icc_node qxm_mdp0_disp = { + .name = "qxm_mdp0_disp", + .id = SM8350_MASTER_MDP0_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_mdp1_disp = { + .name = "qxm_mdp1_disp", + .id = SM8350_MASTER_MDP1_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_rot_disp = { + .name = "qxm_rot_disp", + .id = SM8350_MASTER_ROTATOR_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8350_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8350_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8350_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8350_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM8350_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SM8350_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8350_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8350_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8350_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8350_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_cfg = { + .name = "qhs_compute_cfg", + .id = SM8350_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8350_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8350_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8350_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8350_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SM8350_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM8350_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8350_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8350_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .id = SM8350_SLAVE_HWKM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8350_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8350_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SM8350_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SM8350_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SM8350_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SM8350_SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8350_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8350_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM8350_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8350_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pka_wrapper_cfg = { + .name = "qhs_pka_wrapper_cfg", + .id = SM8350_SLAVE_PKA_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg = { + .name = "qhs_pmu_wrapper_cfg", + .id = SM8350_SLAVE_PMU_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8350_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8350_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM8350_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM8350_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SM8350_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8350_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8350_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SM8350_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SM8350_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8350_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SM8350_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8350_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8350_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8350_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8350_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8350_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8350_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a1_noc_cfg = { + .name = "qns_a1_noc_cfg", + .id = SM8350_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2_noc_cfg = { + .name = "qns_a2_noc_cfg", + .id = SM8350_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SM8350_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .id = SM8350_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SM8350_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .id = SM8350_SLAVE_BOOT_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8350_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8350_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8350_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8350_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8350_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8350_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8350_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8350_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SM8350_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { + .name = "qhs_modem_ms_mpu_cfg", + .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SM8350_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8350_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SM8350_SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SM8350_SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SM8350_SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SM8350_SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8350_SLAVE_EBI1, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8350_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM8350_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8350_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SM8350_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SM8350_SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8350_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8350_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8350_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc_disp = { + .name = "qns_llcc_disp", + .id = SM8350_SLAVE_LLCC_DISP, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_LLCC_DISP }, +}; + +static struct qcom_icc_node ebi_disp = { + .name = "ebi_disp", + .id = SM8350_SLAVE_EBI1_DISP, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf_disp = { + .name = "qns_mem_noc_hf_disp", + .id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_mem_noc_sf_disp = { + .name = "qns_mem_noc_sf_disp", + .id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP }, +}; 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Kill it with heavy fire. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpmh.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 5634d302963a..e0b40e313f08 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -122,16 +122,6 @@ struct qcom_icc_desc { size_t num_bcms; }; -#define DEFINE_QNODE(_name, _id, _channels, _buswidth, ...) \ - static struct qcom_icc_node _name = { \ - .id = _id, \ - .name = #_name, \ - .channels = _channels, \ - .buswidth = _buswidth, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links = { __VA_ARGS__ }, \ - } - int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); int qcom_icc_set(struct icc_node *src, struct icc_node *dst); From patchwork Tue Jul 11 12:18:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118450 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp434869vqm; Tue, 11 Jul 2023 05:21:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlHfB968fNlpNK+K6E+nQC/jJ0aQ1h/X+dluMIpU0VexuMNupx+wZOLt1BTDCHBl2vwn4o0C X-Received: by 2002:a17:903:244e:b0:1b5:edd:e3c7 with SMTP id l14-20020a170903244e00b001b50edde3c7mr15146280pls.16.1689078065747; Tue, 11 Jul 2023 05:21:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078065; cv=none; d=google.com; s=arc-20160816; b=W3ftuWh0xsF+buhU8yt33QReXRTcuyQMfhZhhCPsoJHCpoNSFl4SEAsedhpv142fxZ fyvVxMVOauGN3AdAohbQqyvEWYndS1TOA00cx+8W7a12gbXNiKD4PsTk1DgwXaXtOaFl 9igFt3Lpxs/0HpoqHCbCpJivX4YoBNu3NfQS2uGrZ+H9G8ic2r374Ict7HlGF8+fb6yd Ey06RDKHZDn9LI+2Sxiz6tEyy+BF7pobdnekcklyiVcMcZMMwqKFK4T3B6nF6Z9kVNrc PosmTAX6dw+kktaIBB/6Ct+16kA4L7mk5AA3XnpElRO/N4US4egvhtm63n+1o105gWvt /kkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=JV2NOHdhXQJvyF0fc5slrvpV1+3GiCLz+u7Y70t3daI=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=c8dYXuQpyCoGvDuqmiAu5DqRMR7+vBGmmeRM65VHuSJG5vwNcZvQaQ9WytRA6Leqvk WW5whPg/UjzaYJipMBJiFFvylhPrWiEzyZZc+pLtRxGCjbGw76ce26yjVdPaeyKvsEOt TjTjKU1x3VgBxwFbAMJULF0vRX7Z1VIM1IAoAA2vZoz/LIPkxmZ+Mo21NJ2FqHDTpg50 O7BiHT2zfWKJ/bL7caSygAXRUK1xryLY+f/1uWmeBl2nKi1JDThlR4kuqWslLNysLp4M THD9SeP+FwHndPr060Rycfe4byE0S4vTmZOq3YqShBDAUeXJ9re8vZdV4g7iCrE1qs8y 1aOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RF7r80co; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:15 +0200 Subject: [PATCH 16/53] interconnect: qcom: sc7180: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-16-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8531; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=z5wK9eZaguqOGRFKwow1eBaPyqCaSpkZDfuYMwlOGz0=; b=lkxrf35BwbC2UuSnZtJLbD7icxmUVnr1eFa3xKWoGtYaeSGTrASIhgtVs6IhS77YPHhrUs2Fc SoppQwAXXkxCIZzArfY9UH+aAKHJtmGnPz5Svdxl7lBSSWYA/U/o9JM X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126722032593806 X-GMAIL-MSGID: 1771126722032593806 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7180.c | 279 +++++++++++++++++++++++++++++++++---- 1 file changed, 255 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index d1b0427f8781..3629dee4448b 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1235,30 +1235,261 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 48, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 8, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qhm_mnoc_cfg, + &qxm_mdp0, + &qxm_rot, + &qxm_venus0, + &qxm_venus_arm9 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qup_core_master_1, &qup_core_master_2 }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_apps0 }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 8, + .nodes = { &qhm_qspi, + &xm_sdc2, + &xm_emmc, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_qspi, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qxm_pimem, &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, From patchwork Tue Jul 11 12:18:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118454 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp439631vqm; Tue, 11 Jul 2023 05:29:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlFzVRNP0imdFyAVb5THdxYhBu0QJ5GMNL1dqMxjKFhF7dn9McD4A9t2IdRDb4gSXILjN7CT X-Received: by 2002:a05:6870:4292:b0:1b0:657f:5047 with SMTP id y18-20020a056870429200b001b0657f5047mr16918709oah.46.1689078585593; Tue, 11 Jul 2023 05:29:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078585; cv=none; d=google.com; s=arc-20160816; b=UHsdolXhP0fHig7s4KJi2/rniAllsja0VrkVwZIa82ilPJrop83baMi5poGdrQZ67r tikiw0yGrYFPLilsUSeYK/U64O0C5Zbu9r5UTU2m4xHuopUa9kTywD0lF0/fvC0WQ/Iq wMjLaNwbdOcyZ39IVUrnVdZOYVt9I7ueUjHvfT6/9AELBj7xTpahA7JJq2+1Yqkzq8Ib HAaXVX/6kAuHaJOmfkQ1NvSmka87ajsgGdr0b7+VLDHlnukzCM2Zm8d8v0ZJ/u0oV4tD WSeLHNqMCOnvVx0dyEasCpxT/T/z5orUOPVIynNb29JWwLFAtLd+DaqLKdszMOoXdItm M+PA== ARC-Message-Signature: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:49 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:16 +0200 Subject: [PATCH 17/53] interconnect: qcom: sdm670: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-17-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8074; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=8HeC5O9fAYtInntL0QiwX8CnifnzRAUfXIiKtq/eVkU=; b=R15de6emMH6T9UWZlbP6B9fTaKRaPR57Wh7xfaJn8rdLlWXHZ+fKMxLOhd1dJt8jJEERDH5bZ kyZukWSgye7AYuhvFzz+y7gZlwGtSJCKb+S+5WtZesmHdmpTRH8scb4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127266879758961 X-GMAIL-MSGID: 1771127266879758961 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm670.c | 263 +++++++++++++++++++++++++++++++++---- 1 file changed, 239 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index 2c2cbe1b5197..c13ccdd5841d 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1044,30 +1044,245 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 41, + .nodes = { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qxm_pimem, &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn13 = { + .name = "SN13", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, From patchwork Tue Jul 11 12:18:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118486 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442897vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:50 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:17 +0200 Subject: [PATCH 18/53] interconnect: qcom: sdm845: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-18-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=9245; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ssXuHafj1ZDCbbonhxge+YDkgDx8WaBw7/dlRD6KWU0=; b=kyUwAelmuHa0aGRAJw+drBSeWz4L0zOcjTagal7f6G16iGADNeYhg/vTHLQ0bD9pQBn42fBF1 apI5brH4xFtDwJ4xHyKuHhp78DkVP2p3IFDFWBVpIEsQbRhXmG29uYY X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127569054975496 X-GMAIL-MSGID: 1771127569054975496 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm845.c | 305 +++++++++++++++++++++++++++++++++---- 1 file changed, 277 insertions(+), 28 deletions(-) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 5caf6e5aeeca..26fade7a0ce5 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1262,34 +1262,283 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3); -DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 47, + .nodes = { &qhm_spdm, + &qhm_tic, + &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pcie_gen3 }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_pcie_anoc }, +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn9, From patchwork Tue Jul 11 12:18:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118485 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442856vqm; Tue, 11 Jul 2023 05:34:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlFv2AhS4YI56hN40Rj04qEA/kSr5fod0czjcxs9/Owv7hWgjyCeineCV37HrjsNZA0g5ufl X-Received: by 2002:a05:6a20:60b:b0:122:92d0:452a with SMTP id 11-20020a056a20060b00b0012292d0452amr15983159pzl.37.1689078869171; Tue, 11 Jul 2023 05:34:29 -0700 (PDT) ARC-Seal: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:18 +0200 Subject: [PATCH 19/53] interconnect: qcom: sdx55: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-19-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5432; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R92aM77XVZAqKQuJtDwodh3d1IHCkhMpDQVlwb6kTv0=; b=ASDIVUzeQZ9QMHjM49gGjQWUBVfYt6YMoSX818QYw/+a/Q3qoJ8RNZ/VHzK4anO+KxSqsbUHf f4DOgaD4pyaAUjtd9IwCjIMLH32BgKxrDiIBpbODkXdiH8kIQKg0fnh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127564471086955 X-GMAIL-MSGID: 1771127564471086955 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx55.c | 180 +++++++++++++++++++++++++++++++++----- 1 file changed, 159 insertions(+), 21 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 2b5e8873eaa5..968b7b953912 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -642,27 +642,165 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, - &qns_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_pn0 = { + .name = "PN0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qhm_snoc_cfg }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qns_memnoc_snoc, &qns_sys_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_pn1 = { + .name = "PN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 = { + .name = "PN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_pn3 = { + .name = "PN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_pn5 = { + .name = "PN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, +}; static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, From patchwork Tue Jul 11 12:18:19 2023 Content-Type: text/plain; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:53 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:19 +0200 Subject: [PATCH 20/53] interconnect: qcom: sdx65: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-20-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6218; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Fdsj7Q8qluuHDSxo4HSyUvvKfsGRHI1pvdy6XHDDsKo=; b=9lSQq6+ZIpxll0H/JERMHh/63NXuDH5sC5z5byZrPdLmDqG6Y8+4slb8XxQ7q3ZYznonHtN9K qAJ9iEaVbg2AqKcaNU5XSSrczELv5nOez3VrH5wqLB4XEs8xCQ1p/a1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127268303019830 X-GMAIL-MSGID: 1771127268303019830 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx65.c | 205 ++++++++++++++++++++++++++++++++++---- 1 file changed, 185 insertions(+), 20 deletions(-) diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index bebed036fe7a..881a39c172e3 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -603,26 +603,191 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_pn0 = { + .name = "PN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 26, + .nodes = { &qhm_snoc_cfg, + &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &srvc_snoc + }, +}; + +static struct qcom_icc_bcm bcm_pn1 = { + .name = "PN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 = { + .name = "PN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_pn3 = { + .name = "PN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_pn4 = { + .name = "PN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 4, + .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, +}; static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, From patchwork Tue Jul 11 12:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118483 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442821vqm; Tue, 11 Jul 2023 05:34:27 -0700 (PDT) X-Google-Smtp-Source: APBJJlEpisxIgZyNal+26cLaxuLUgIksejz7RwAcmtuz7TEBJ/ZwiuEFvlR+ysDFnbwV/k0RAsHd X-Received: by 2002:a17:902:e743:b0:1b8:1c4f:4f8e with SMTP id p3-20020a170902e74300b001b81c4f4f8emr16792764plf.53.1689078866744; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:20 +0200 Subject: [PATCH 21/53] interconnect: qcom: sm6350: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-21-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8416; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SrAfEu7z7LDi+swPnqPTMHcA8pMC5/hLxqI6ZqZhaf0=; b=7WlneqnlYUMwfgEWnegCIMJfixgMc1PsRYVSsNGX2DEtr9WcXugI3RsfzMQZKXEXxhT053I17 5WznrJl7egfC0ejss8NmYrjEn1JX6/Cc84u1ixD848BDyOfR/6GCl1m X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127561474050759 X-GMAIL-MSGID: 1771127561474050759 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm6350.c | 276 +++++++++++++++++++++++++++++++++---- 1 file changed, 251 insertions(+), 25 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index 7421eb4cd520..845d888f7634 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1161,31 +1161,257 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 41, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_thrott_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 6, + .nodes = { &xm_emmc, + &xm_sdc2, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_icp_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf, + &qxm_mdp0 + }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 4, + .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 4, + .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, From patchwork Tue Jul 11 12:18:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118467 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440439vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:21 +0200 Subject: [PATCH 22/53] interconnect: qcom: sm8150: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-22-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=9494; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OR/aMRqrXjITcvDE45wlMNy7hvzhmiKeqYcGWttjB1Q=; b=uF+SFPLd6m6ntYCetsIlLhvgefSm5PCEEzcmxuit4atD5Re3IYmwtv545+LYKXsoSuT1jd13g uwfQDDEOZJwAjvrpTHYPMY4jF6Go5mE6iXfc2A93+DlTv7+0QvGxAAx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127338150049873 X-GMAIL-MSGID: 1771127338150049873 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8150.c | 311 +++++++++++++++++++++++++++++++++---- 1 file changed, 283 insertions(+), 28 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 29f16899cf5d..91f68d91f12a 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1279,34 +1279,289 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { .buswidth = 8, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &acm_gpu_tcu, &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 4, + .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_co1 = { + .name = "CO1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 53, + .nodes = { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy_south, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emac_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_phy_refgen_north, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qupv3_east, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_ssc_cfg, + &qhs_tcsr, + &qhs_tlmm_east, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tlmm_west, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qxm_pimem, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, From patchwork Tue Jul 11 12:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118451 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp435138vqm; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:57 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:22 +0200 Subject: [PATCH 23/53] interconnect: qcom: sm8250: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-23-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8980; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=t1pXtAGd50MXkyw2HwnChg2QcAcq+w7wwZSL8zvgYig=; b=FydPpyU0pYwqg60zuq5IyJ2PVzg0/iI6p7cPUx2AhRjBtXFm4HCWdX8PH8cssELO0FQQeKi8R aLRJXDCAkZ/Cn+szJAWmIJVylzJysAFfMd4IfaZZo3XfSrzDEpCb9q9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126753672561550 X-GMAIL-MSGID: 1771126753672561550 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8250.c | 294 +++++++++++++++++++++++++++++++++---- 1 file changed, 267 insertions(+), 27 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index d4123799c2c6..8cb032ac34bf 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -1394,33 +1394,273 @@ static struct qcom_icc_node qup2_core_slave = { .buswidth = 4, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 52, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie_modem_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm0, + &qhs_tlmm1, + &qhs_tlmm2, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_pcie_modem }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn12, From patchwork Tue Jul 11 12:18:23 2023 Content-Type: text/plain; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:23 +0200 Subject: [PATCH 24/53] interconnect: qcom: sm8350: Retire DEFINE_QBCM MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-24-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=10048; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=7vRh6286jkOOStnKJOqywJgMBVBvPJLc59I7qoEIBjs=; b=BeU5lcKnloq3Tv9ibVtuGRjb29VlklFHbqYkVVLJgLUjBiQjoE6LpKiS6N8OucmxAwKV9Lg/e Fwc2wFonCPDD4VJb5ohkQgkVq0jbagT1ipLwUVJQQBrCbsmrI7XpM/H X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127444109248325 X-GMAIL-MSGID: 1771127444109248325 The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 340 +++++++++++++++++++++++++++++++++---- 1 file changed, 308 insertions(+), 32 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 859549b176c8..c48f96ff8575 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1353,38 +1353,314 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { .links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP }, }; -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp); -DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp); -DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp); -DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp); -DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); -DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); -DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 47, + .nodes = { &xm_qdss_dap, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 5, + .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 3, + .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_mm4 = { + .name = "MM4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm5 = { + .name = "MM5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 6, + .nodes = { &qnm_camnoc_icp, + &qnm_camnoc_sf, + &qnm_video0, + &qnm_video1, + &qnm_video_cvp, + &qxm_rot + }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 2, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &xm_pcie3_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .voter_idx = ICC_BCM_VOTER_APPS, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_acv_disp = { + .name = "ACV", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mc0_disp = { + .name = "MC0", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mm0_disp = { + .name = "MM0", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm1_disp = { + .name = "MM1", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 2, + .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp }, +}; + +static struct qcom_icc_bcm bcm_mm4_disp = { + .name = "MM4", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm5_disp = { + .name = "MM5", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qxm_rot_disp }, +}; + +static struct qcom_icc_bcm bcm_sh0_disp = { + .name = "SH0", + .keepalive = false, + .voter_idx = 0, + .num_nodes = 1, + .nodes = { &qns_llcc_disp }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; From patchwork Tue Jul 11 12:18:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118476 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441668vqm; Tue, 11 Jul 2023 05:32:40 -0700 (PDT) X-Google-Smtp-Source: APBJJlFfR0myHzDs3slk3WfDLpiy6QAekO3pIxDC8KEh4FeRVpPrq37/eluO3OGT3RODe/GMNMEv X-Received: by 2002:a17:903:449:b0:1b9:e481:ef3f with SMTP id iw9-20020a170903044900b001b9e481ef3fmr2902001plb.9.1689078760494; Tue, 11 Jul 2023 05:32:40 -0700 (PDT) ARC-Seal: i=1; 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Kill it with heavy fire. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/qcom/bcm-voter.h index 30b324fcb2ee..62cdee94b5ba 100644 --- a/drivers/interconnect/qcom/bcm-voter.h +++ b/drivers/interconnect/qcom/bcm-voter.h @@ -12,14 +12,6 @@ #include "icc-rpmh.h" -#define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \ -static struct qcom_icc_bcm _name = { \ - .name = _bcmname, \ - .keepalive = _keepalive, \ - .num_nodes = ARRAY_SIZE(((struct qcom_icc_node *[]){ __VA_ARGS__ })), \ - .nodes = { __VA_ARGS__ }, \ -} - void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm); int qcom_icc_bcm_voter_commit(struct bcm_voter *voter); From patchwork Tue Jul 11 12:18:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118470 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441072vqm; Tue, 11 Jul 2023 05:31:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlFWbOPqasS62TelHdm2ZelBIau+bDC/RrLQ+azqdU4t688g7qwJAgDgp4jybh+Id6e4jXxO X-Received: by 2002:a05:6a00:391c:b0:682:9162:720f with SMTP id fh28-20020a056a00391c00b006829162720fmr14660562pfb.6.1689078706750; Tue, 11 Jul 2023 05:31:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078706; cv=none; d=google.com; s=arc-20160816; b=Tbg6GBypk4OVjWXq2CsXd7TQdJmq8pNHY4gCw5/spbUdGsJwWVissopKFcjzb7idKf FJsow5HT/GfzF82TemTuxcy44AfYkzov6XS0u4JxpgxYje+4dkrDBxxAryFtGs/fucW/ GiQpg9uPw3OUAqybHQq8SBqQnTAR9iPCr74QUUXkK13TXqvi0BRWIr2msPmVBGTOVf3Y QVXa6xfb6bTxhyCpxDYX6XMuVwfWiAYyk0h3j0wbXPACAfsBEOPLlCicfaoXuW04aU7T 42C663DGxbwPjBQZY4T74F7m2Y/8o1uAyS94c7/j7Q03PwkBRknfBNxma0ZSJc7mu7vK 8Lwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=yjEw0XoxZw/g1nfL12bHFSyvJYF4vER1wXRrobCe4VQ=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=dtTV7PRxYxuNGeYnkQ6AoqFGL7BZ8mmaUkTHCjCEclSMJePr54RnsRVizSwHGVCJ5d zWecUoMmyDavespix4OyVcmZqD417yWDNNJx3Bu3jrhnZxPY8CxrILXCmCkn/HgjjHr3 E/PoyLLma/AiCUo6+WyUR0d1nmSUdK41G6JJa2pVVbpq3pBXiqIVGX1NXMwvTD2a5CaS s/fu+e+JX8vvuzsNt9Vz87CrYkPcbglo1do9+DDuXrEllufTnhXddOUWBrOGyCizzjx/ RJdwHMQv8ABpT9zK9+K+kdMGmEJ07xlGHrdgwVV5I1xC3jieKe97nkToKMwAJHm6SYM+ 1POQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SO8G7gtb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:01 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:25 +0200 Subject: [PATCH 26/53] interconnect: qcom: qdu1000: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-26-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2723; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9xNumb4mlVPJURVONYP61q5QOzs9rfLdvbN1jnXwzpk=; b=IUepLalcILF7YN5hx4w8ucTFotgb8EVQk+WRRg8BB2vlIGoZ5lTxmAmV/VZbcNjfozWT0W6Bq V1lkz8druzNCYbmJ0YerskqCPBdQR+cpC3t0UpsAEdKCdRw2G5z5+Mu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127394350441252 X-GMAIL-MSGID: 1771127394350441252 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/qdu1000.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index a4cf559de2b0..f9c54e9ad9d1 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -768,18 +768,21 @@ static struct qcom_icc_node xs_sys_tcu_cfg = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_crypto }, }; static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 44, .nodes = { &qhm_qpic, &qhm_qspi, &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave, @@ -808,24 +811,28 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qup0_core_slave, &qup1_core_slave }, }; static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 11, .nodes = { &alm_sys_tcu, &chm_apps, &qnm_ecpri_dma, &qnm_fec_2_gemnoc, @@ -838,12 +845,14 @@ static struct qcom_icc_bcm bcm_sh1 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 6, .nodes = { &qhm_gic, &qxm_pimem, &xm_gic, &xm_qdss_etr0, @@ -853,6 +862,7 @@ static struct qcom_icc_bcm bcm_sn1 = { static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 5, .nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi, &xm_ecpri_dma, &qns_anoc_snoc_gsi, @@ -862,6 +872,7 @@ static struct qcom_icc_bcm bcm_sn2 = { static struct qcom_icc_bcm bcm_sn7 = { .name = "SN7", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_pcie_gemnoc, &xs_pcie }, }; From patchwork Tue Jul 11 12:18:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118484 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442853vqm; Tue, 11 Jul 2023 05:34:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlEBXZY5uHAiAPY8YlKqba+/4Yk//OqnJYlq4ghM+YS9e4SJKS3Y31Xi4Yod9UoKmoxOjCtu X-Received: by 2002:a17:902:b494:b0:1b6:771a:3516 with SMTP id y20-20020a170902b49400b001b6771a3516mr12055065plr.22.1689078869042; Tue, 11 Jul 2023 05:34:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078869; cv=none; d=google.com; s=arc-20160816; b=QQGaCCdImft20m3NiJ750HW/8CBjpUt5DAVX+y1wJM9RptjGoFk2HLo08Ehfleq5gz CJfEpKN+8jMRDj10QWMn3vqDk7hCB4lgCVmwyPJBGrGhs/QQScphx2ZhunwxNk9XzNee zwd/hxjvq5i1Yc+Y1PqUvW5mURz8na0e1RNhA6JzhhhRHdQTJx/KnBf9UwyAAKSitP/a 21U0q7RLEXr730rk4f4H3sifiwOKAq3nvrSbnnbAs0iE/lOFtQHpM+Wx4ERXW5wuqTf6 NHjgDP/pJJszTpEprEUvVO9eI3gXRO1RDtZeKtz+SAq+ttE31DTT67EeH1CXwZ6Vn5Yb ivfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=InZYjJK59SO/+Ay8B5RTmrMRVJCA6dyKOvQqkkaczAs=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=SUVm/sdMVg7CuuSXx5OVCIP1yZHkFDV8SX2Ksp6CDSQiJSmlGteJx0/nSz3mWlmRFI gm73PA+XotztnrYk7nOO8D6udgCF8AKpqQ2EAJvOphLNqMUdljfohbqP7AUWGCRGKrXO Z4Y6GqLR8Nw+sxv1PKmyGM4D2RuSHHzkNiRKa6JHpiWVxnBo9TEpUD6LswnGo5gUh39Q almtcHZCsqp0NCgTBxKQ4sLNHNdoNhXehhnaTQKGNahVGaZZcvqvY/inIUg6XfKQm8sM LNFDUKAXqkeYphjqlh+uWaCl3p1Bv3ECeM+DFS0Ir2NZz+HGptWq4JYhN+Uz/6XR9pWS rjmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ot38pV7C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:26 +0200 Subject: [PATCH 27/53] interconnect: qcom: sa8775p: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-27-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6180; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hOvbaOTw9Rft7PbhGwWzFvl3fJ55nEvjw1n3n0o+bvA=; b=bgBgJk9B9qnxSbwV2qtOwPqT0zxWHu4caPLE/qW7xFxyp0JDmlS4/+qKJ/fj7t1TS2QpTfbW1 k9/9xeqbpMyBVZ8bZBghyIsifPl/3HndxIGab11sgNllsV5rphubazj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127564230775164 X-GMAIL-MSGID: 1771127564230775164 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sa8775p.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index f56538669de0..0c8ef127f8a8 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .voter_idx = ICC_BCM_VOTER_APPS, .enable_mask = 0x8, .num_nodes = 1, .nodes = { &ebi }, @@ -1880,6 +1881,7 @@ static struct qcom_icc_bcm bcm_acv = { static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, }; @@ -1887,12 +1889,14 @@ static struct qcom_icc_bcm bcm_ce0 = { static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, }; static struct qcom_icc_bcm bcm_cn1 = { .name = "CN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 76, .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, @@ -1936,6 +1940,7 @@ static struct qcom_icc_bcm bcm_cn1 = { static struct qcom_icc_bcm bcm_cn2 = { .name = "CN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_qup3 }, @@ -1943,18 +1948,21 @@ static struct qcom_icc_bcm bcm_cn2 = { static struct qcom_icc_bcm bcm_cn3 = { .name = "CN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &xs_pcie_0, &xs_pcie_1 }, }; static struct qcom_icc_bcm bcm_gna0 = { .name = "GNA0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_dsp0 }, }; static struct qcom_icc_bcm bcm_gnb0 = { .name = "GNB0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_dsp1 }, }; @@ -1962,6 +1970,7 @@ static struct qcom_icc_bcm bcm_gnb0 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; @@ -1969,6 +1978,7 @@ static struct qcom_icc_bcm bcm_mc0 = { static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 5, .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, &qnm_mdp0_1, &qnm_mdp1_0, @@ -1977,6 +1987,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 7, .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, @@ -1986,30 +1997,35 @@ static struct qcom_icc_bcm bcm_mm1 = { static struct qcom_icc_bcm bcm_nsa0 = { .name = "NSA0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_hcp, &qns_nsp_gemnoc }, }; static struct qcom_icc_bcm bcm_nsa1 = { .name = "NSA1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_nsp }, }; static struct qcom_icc_bcm bcm_nsb0 = { .name = "NSB0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp }, }; static struct qcom_icc_bcm bcm_nsb1 = { .name = "NSB1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_nspb }, }; static struct qcom_icc_bcm bcm_pci0 = { .name = "PCI0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_pcie_mem_noc }, }; @@ -2017,6 +2033,7 @@ static struct qcom_icc_bcm bcm_pci0 = { static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; @@ -2024,6 +2041,7 @@ static struct qcom_icc_bcm bcm_qup0 = { static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; @@ -2031,6 +2049,7 @@ static struct qcom_icc_bcm bcm_qup1 = { static struct qcom_icc_bcm bcm_qup2 = { .name = "QUP2", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qup2_core_slave, &qup3_core_slave }, }; @@ -2038,12 +2057,14 @@ static struct qcom_icc_bcm bcm_qup2 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh2 = { .name = "SH2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &chm_apps }, }; @@ -2051,42 +2072,49 @@ static struct qcom_icc_bcm bcm_sh2 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxs_pimem }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, }; static struct qcom_icc_bcm bcm_sn9 = { .name = "SN9", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_sysnoc, &qnm_lpass_noc }, }; static struct qcom_icc_bcm bcm_sn10 = { .name = "SN10", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &xs_qdss_stm }, }; From patchwork Tue Jul 11 12:18:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118481 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442527vqm; Tue, 11 Jul 2023 05:33:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlHphlrl65Eqcy/QsO8BkMD+C13VESqb/qZE2Q4DDG08i7D8uqcT7XvNYhXpBskGUIsOFqqd X-Received: by 2002:a05:6a21:328a:b0:132:7d91:aadb with SMTP id yt10-20020a056a21328a00b001327d91aadbmr1024623pzb.6.1689078836593; Tue, 11 Jul 2023 05:33:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078836; cv=none; d=google.com; s=arc-20160816; b=0fOf009f0eoxedNF3rC3SbedTgN+BZsCQD3xgXGWsHNqpTKk2ZNEASF/7KSDAbKAhi gdJb0hYo2qssXQUQyieLnxXST6JF+nL+IUyfONwolytEErZjImrinXV2das8V6YkuAxp cFoKtPOfXsaWUST6xWwFF2lxRb9Slskh1oCZP2y/17UgrbCxSLjbeOm/tm8qyGoQWLv3 6sKMsDZ6iZRXutdHrJ9jCEErwNPr9zJlIGnNXgmhP/0EnH8qpDY0cAJPTZgm24Ykt6QG Jw6vViSZkggpuKkL8mcMq6ZzeqKBZ9cZYbWTXb5q/dkuVMpY3dhqnZQ4YpB2z0Pz7+uV VP3Q== ARC-Message-Signature: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:03 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:27 +0200 Subject: [PATCH 28/53] interconnect: qcom: sc7280: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-28-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5586; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nax1GmT400+SDmWYx677ggaJz8Q417oAUImc//sqRBI=; b=QZfN5DzZ+sQyvhBt7DAVOOwH1qwd9tG7nKc4auZp5i3QPCjza8KgAr17dKeTznGx/lQwfE2k4 gz3cbp2Cj8GB79VtLFoHEG9heBFxwEzRP59H5YWT+IFj7RrJXX/vZaj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127529818047832 X-GMAIL-MSGID: 1771127529818047832 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7280.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 971f538bc98a..bb8b31612501 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1284,12 +1284,14 @@ static struct qcom_icc_node srvc_snoc = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_crypto }, }; @@ -1297,12 +1299,14 @@ static struct qcom_icc_bcm bcm_ce0 = { static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, }; static struct qcom_icc_bcm bcm_cn1 = { .name = "CN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 47, .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1331,6 +1335,7 @@ static struct qcom_icc_bcm bcm_cn1 = { static struct qcom_icc_bcm bcm_cn2 = { .name = "CN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 6, .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc1, @@ -1339,12 +1344,14 @@ static struct qcom_icc_bcm bcm_cn2 = { static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_nsp_gemnoc }, }; static struct qcom_icc_bcm bcm_co3 = { .name = "CO3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_nsp }, }; @@ -1352,6 +1359,7 @@ static struct qcom_icc_bcm bcm_co3 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; @@ -1359,24 +1367,28 @@ static struct qcom_icc_bcm bcm_mc0 = { static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf }, }; static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qxm_camnoc_hf, &qxm_mdp0 }, }; static struct qcom_icc_bcm bcm_mm4 = { .name = "MM4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_sf }, }; static struct qcom_icc_bcm bcm_mm5 = { .name = "MM5", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qnm_video0, &qxm_camnoc_icp, &qxm_camnoc_sf }, @@ -1385,6 +1397,7 @@ static struct qcom_icc_bcm bcm_mm5 = { static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; @@ -1392,6 +1405,7 @@ static struct qcom_icc_bcm bcm_qup0 = { static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; @@ -1399,24 +1413,28 @@ static struct qcom_icc_bcm bcm_qup1 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh2 = { .name = "SH2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, }; static struct qcom_icc_bcm bcm_sh3 = { .name = "SH3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_cmpnoc }, }; static struct qcom_icc_bcm bcm_sh4 = { .name = "SH4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &chm_apps }, }; @@ -1424,54 +1442,63 @@ static struct qcom_icc_bcm bcm_sh4 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxs_pimem }, }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &xs_qdss_stm }, }; static struct qcom_icc_bcm bcm_sn5 = { .name = "SN5", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &xm_pcie3_0 }, }; static struct qcom_icc_bcm bcm_sn6 = { .name = "SN6", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &xm_pcie3_1 }, }; static struct qcom_icc_bcm bcm_sn7 = { .name = "SN7", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_bcm bcm_sn8 = { .name = "SN8", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_bcm bcm_sn14 = { .name = "SN14", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_pcie_mem_noc }, }; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:04 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:28 +0200 Subject: [PATCH 29/53] interconnect: qcom: sc8180x: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-29-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=4909; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BvLWDzRk2sKY58qxMKk4+8yHkv9gScgVxizsgjWb+5A=; b=S4SWkBHlhYTPcaujc0sQmaZQyunPxhvKNOiG/aVsNj2bmQlmh2bfEHjGvop/VE8BQNX0Mqv9z syT8aKM70g1Ch4Hy4W1nWDuHW8XsS3yXKDu+KTMKwZD5fD7NOJZJLA8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127467876815739 X-GMAIL-MSGID: 1771127467876815739 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc8180x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index c76e3a6a98cd..a811cbf2cd15 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1344,6 +1344,7 @@ static struct qcom_icc_node slv_qup_core_2 = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_ebi } }; @@ -1351,6 +1352,7 @@ static struct qcom_icc_bcm bcm_acv = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_ebi } }; @@ -1358,24 +1360,28 @@ static struct qcom_icc_bcm bcm_mc0 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_qns_llcc } }; static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_qns_mem_noc_hf } }; static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_qns_cdsp_mem_noc } }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &mas_qxm_crypto } }; @@ -1383,6 +1389,7 @@ static struct qcom_icc_bcm bcm_ce0 = { static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 57, .nodes = { &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, @@ -1445,6 +1452,7 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 7, .nodes = { &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, @@ -1457,6 +1465,7 @@ static struct qcom_icc_bcm bcm_mm1 = { static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &mas_qup_core_0, &mas_qup_core_1, @@ -1465,12 +1474,14 @@ static struct qcom_icc_bcm bcm_qup0 = { static struct qcom_icc_bcm bcm_sh2 = { .name = "SH2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_qns_gem_noc_snoc } }; static struct qcom_icc_bcm bcm_mm2 = { .name = "MM2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 6, .nodes = { &mas_qxm_camnoc_sf, &mas_qxm_rot, @@ -1483,45 +1494,53 @@ static struct qcom_icc_bcm bcm_mm2 = { static struct qcom_icc_bcm bcm_sh3 = { .name = "SH3", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &mas_acm_apps } }; static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &slv_qns_gemnoc_sf } }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &slv_qxs_imem } }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &slv_qns_gemnoc_gc } }; static struct qcom_icc_bcm bcm_co2 = { .name = "CO2", + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &mas_qnm_npu } }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &slv_srvc_aggre1_noc, &slv_qns_cnoc } }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .voter_idx = ICC_BCM_VOTER_APPS, .nodes = { &slv_qxs_pimem } }; static struct qcom_icc_bcm bcm_sn8 = { .name = "SN8", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &slv_xs_pcie_0, &slv_xs_pcie_1, @@ -1531,18 +1550,21 @@ static struct qcom_icc_bcm bcm_sn8 = { static struct qcom_icc_bcm bcm_sn9 = { .name = "SN9", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &mas_qnm_aggre1_noc } }; static struct qcom_icc_bcm bcm_sn11 = { .name = "SN11", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &mas_qnm_aggre2_noc } }; static struct qcom_icc_bcm bcm_sn14 = { .name = "SN14", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &slv_qns_pcie_mem_noc } }; @@ -1550,6 +1572,7 @@ static struct qcom_icc_bcm bcm_sn14 = { static struct qcom_icc_bcm bcm_sn15 = { .name = "SN15", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &mas_qnm_gemnoc } }; From patchwork Tue Jul 11 12:18:29 2023 Content-Type: text/plain; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:06 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:29 +0200 Subject: [PATCH 30/53] interconnect: qcom: sc8280xp: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-30-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6261; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1S7DwAbbmJRlgdB0jUv8vg/oE5s08GOdcA66t7/JhZc=; b=vqcyWjtV/JprX614HAMpkTlFUQLjDMQQv8R0aAu5IsNbPK8j8+eSx7TI5kYXRFXHwdUaPAWMc Gdjwnz/iYQiATKZK2DH//eiLoYEHkOvpvT8Aw55TgVtLqg5AooIMaOQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128973099387191 X-GMAIL-MSGID: 1771128973099387191 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc8280xp.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index e56df893ec3e..2f595b78e2bc 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -1711,12 +1711,14 @@ static struct qcom_icc_node srvc_snoc = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_crypto }, }; @@ -1724,6 +1726,7 @@ static struct qcom_icc_bcm bcm_ce0 = { static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 9, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, @@ -1739,6 +1742,7 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_cn1 = { .name = "CN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 67, .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1812,6 +1816,7 @@ static struct qcom_icc_bcm bcm_cn1 = { static struct qcom_icc_bcm bcm_cn2 = { .name = "CN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qhs_qspi, &qhs_qup0, @@ -1822,6 +1827,7 @@ static struct qcom_icc_bcm bcm_cn2 = { static struct qcom_icc_bcm bcm_cn3 = { .name = "CN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qxs_imem, &xs_smss, @@ -1832,6 +1838,7 @@ static struct qcom_icc_bcm bcm_cn3 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; @@ -1839,6 +1846,7 @@ static struct qcom_icc_bcm bcm_mc0 = { static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 5, .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, @@ -1850,6 +1858,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 8, .nodes = { &qnm_rot_0, &qnm_rot_1, @@ -1864,6 +1873,7 @@ static struct qcom_icc_bcm bcm_mm1 = { static struct qcom_icc_bcm bcm_nsa0 = { .name = "NSA0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_nsp_gemnoc, &qxs_nsp_xfr @@ -1872,12 +1882,14 @@ static struct qcom_icc_bcm bcm_nsa0 = { static struct qcom_icc_bcm bcm_nsa1 = { .name = "NSA1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_nsp }, }; static struct qcom_icc_bcm bcm_nsb0 = { .name = "NSB0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_nspb_gemnoc, &qxs_nspb_xfr @@ -1886,12 +1898,14 @@ static struct qcom_icc_bcm bcm_nsb0 = { static struct qcom_icc_bcm bcm_nsb1 = { .name = "NSB1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_nspb }, }; static struct qcom_icc_bcm bcm_pci0 = { .name = "PCI0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_pcie_gem_noc }, }; @@ -1899,6 +1913,7 @@ static struct qcom_icc_bcm bcm_pci0 = { static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; @@ -1906,6 +1921,7 @@ static struct qcom_icc_bcm bcm_qup0 = { static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; @@ -1913,6 +1929,7 @@ static struct qcom_icc_bcm bcm_qup1 = { static struct qcom_icc_bcm bcm_qup2 = { .name = "QUP2", .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup2_core_slave }, }; @@ -1920,12 +1937,14 @@ static struct qcom_icc_bcm bcm_qup2 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh2 = { .name = "SH2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &chm_apps }, }; @@ -1933,24 +1952,28 @@ static struct qcom_icc_bcm bcm_sh2 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_gc }, }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxs_pimem }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc @@ -1959,6 +1982,7 @@ static struct qcom_icc_bcm bcm_sn3 = { static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc @@ -1967,6 +1991,7 @@ static struct qcom_icc_bcm bcm_sn4 = { static struct qcom_icc_bcm bcm_sn5 = { .name = "SN5", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_aggre_usb_snoc, &qnm_aggre_usb_noc @@ -1975,6 +2000,7 @@ static struct qcom_icc_bcm bcm_sn5 = { static struct qcom_icc_bcm bcm_sn9 = { .name = "SN9", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qns_sysnoc, &qnm_lpass_noc @@ -1983,6 +2009,7 @@ static struct qcom_icc_bcm bcm_sn9 = { static struct qcom_icc_bcm bcm_sn10 = { .name = "SN10", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &xs_qdss_stm }, }; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:07 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:30 +0200 Subject: [PATCH 31/53] interconnect: qcom: sm8450: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-31-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=I0m5AL+30JxxsGRzPqVcr4YQAJm2OVM5Cn2T0SByiyw=; b=WvhVcfnpVCw2fiB0NJVs0AmEGvXFtkSXcpGBzJbdk2JMg7zxPWG3lUNV9rCQc50aIayKpYc40 5xw4Gnu63tTCAUQIB5T6KtLbd7AU/VloMGOHlznCeW79Pic5gSqvTfE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127317237894959 X-GMAIL-MSGID: 1771127317237894959 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8450.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index e64c214b4020..989ae24f2be9 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1338,12 +1338,14 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .enable_mask = 0x8, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_crypto }, }; @@ -1352,6 +1354,7 @@ static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .enable_mask = 0x1, .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 55, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1386,6 +1389,7 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, }; @@ -1393,6 +1397,7 @@ static struct qcom_icc_bcm bcm_co0 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; @@ -1400,6 +1405,7 @@ static struct qcom_icc_bcm bcm_mc0 = { static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf }, }; @@ -1407,6 +1413,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 12, .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_mdp, @@ -1420,6 +1427,7 @@ static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; @@ -1428,6 +1436,7 @@ static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; @@ -1436,6 +1445,7 @@ static struct qcom_icc_bcm bcm_qup2 = { .name = "QUP2", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup2_core_slave }, }; @@ -1443,6 +1453,7 @@ static struct qcom_icc_bcm bcm_qup2 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; @@ -1450,6 +1461,7 @@ static struct qcom_icc_bcm bcm_sh0 = { static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 7, .nodes = { &alm_gpu_tcu, &alm_sys_tcu, &qnm_nsp_gemnoc, &qnm_pcie, @@ -1460,6 +1472,7 @@ static struct qcom_icc_bcm bcm_sh1 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; @@ -1467,6 +1480,7 @@ static struct qcom_icc_bcm bcm_sn0 = { static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qhm_gic, &qxm_pimem, &xm_gic, &qns_gemnoc_gc }, @@ -1474,24 +1488,28 @@ static struct qcom_icc_bcm bcm_sn1 = { static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_lpass_noc }, }; static struct qcom_icc_bcm bcm_sn7 = { .name = "SN7", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_pcie_mem_noc }, }; @@ -1499,18 +1517,21 @@ static struct qcom_icc_bcm bcm_sn7 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_disp }, }; @@ -1518,6 +1539,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { static struct qcom_icc_bcm bcm_mm1_disp = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qnm_mdp_disp, &qnm_rot_disp, &qns_mem_noc_sf_disp }, @@ -1525,6 +1547,7 @@ static struct qcom_icc_bcm bcm_mm1_disp = { static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; @@ -1532,6 +1555,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_pcie_disp }, }; From patchwork Tue Jul 11 12:18:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118461 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440005vqm; Tue, 11 Jul 2023 05:30:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlG9SniqDlQztAeswWk7oCpvUZgHJylQnFaaTFzq3Ng8AgXZCpOIv5w4atGU2booE1gDh07I X-Received: by 2002:a05:6a21:3393:b0:132:965d:5323 with SMTP id yy19-20020a056a21339300b00132965d5323mr246761pzb.33.1689078617757; Tue, 11 Jul 2023 05:30:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078617; cv=none; d=google.com; s=arc-20160816; b=UHP+QVVsdJloXk0pPh0SMIS4C0y19pIEAFKhbl8pNONZbdSECdXbboh9KVCzvNr4Mj pRxlfcRTHwHP75InwzNogzlwCmr/xDFcmDqPy8DI55V+0ULgnhJrDagQRz8IQhtzDxsH txNv/NWBO+5W5fIZVkS1aZEOkIzWVLyYvGtWRGsqMHzspaHE8u3O1vTK+tk6Bv/zsOq7 l3+7JAjalI1D1MdwPMaxiW5gpnQRo/sGG+TqDc61pJ7aGpL/8/IrzNnywf+XLJgBhMdu +FMULEiZyKksagIVOTcKv9RXu2zLsEV11wLHmf20qo2BNmvpjtPENxlTo495HphLntgj 3t/g== ARC-Message-Signature: i=1; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:09 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:31 +0200 Subject: [PATCH 32/53] interconnect: qcom: sm8550: Explicitly assign voter_idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-32-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=10160; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R7Ecrvuc6qvo53FMgbNdmnfTrkm2nzBuT8JYA7NSeZg=; b=7JcPwfgfhW2pBVGCghP4NdB7PkYfC0k2m2pMPnzv11dSYaWGj0cVZJdQGSwPcJDvlV21poK3s 7cAfSr0Sh7zBiFLhY9Hx0cToOoP5VqlOZlfwm995wuMmRQ9SbjC+T4q X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127300550433519 X-GMAIL-MSGID: 1771127300550433519 To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 0864ed285375..40740cf5e41d 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1474,12 +1474,14 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = { static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .enable_mask = 0x8, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qxm_crypto }, }; @@ -1488,6 +1490,7 @@ static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .enable_mask = 0x1, .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 54, .nodes = { &qsm_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_apss, @@ -1520,6 +1523,7 @@ static struct qcom_icc_bcm bcm_cn0 = { static struct qcom_icc_bcm bcm_cn1 = { .name = "CN1", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qhs_display_cfg }, }; @@ -1527,12 +1531,14 @@ static struct qcom_icc_bcm bcm_cn1 = { static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, }; static struct qcom_icc_bcm bcm_lp0 = { .name = "LP0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, }; @@ -1540,12 +1546,14 @@ static struct qcom_icc_bcm bcm_lp0 = { static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf }, }; @@ -1553,6 +1561,7 @@ static struct qcom_icc_bcm bcm_mm0 = { static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 8, .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_vapss_hcp, @@ -1564,6 +1573,7 @@ static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; @@ -1572,6 +1582,7 @@ static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup1_core_slave }, }; @@ -1580,6 +1591,7 @@ static struct qcom_icc_bcm bcm_qup2 = { .name = "QUP2", .keepalive = true, .vote_scale = 1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qup2_core_slave }, }; @@ -1587,6 +1599,7 @@ static struct qcom_icc_bcm bcm_qup2 = { static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc }, }; @@ -1594,6 +1607,7 @@ static struct qcom_icc_bcm bcm_sh0 = { static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 13, .nodes = { &alm_gpu_tcu, &alm_sys_tcu, &chm_apps, &qnm_gpu, @@ -1607,6 +1621,7 @@ static struct qcom_icc_bcm bcm_sh1 = { static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; @@ -1614,6 +1629,7 @@ static struct qcom_icc_bcm bcm_sn0 = { static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qhm_gic, &xm_gic, &qns_gemnoc_gc }, @@ -1621,18 +1637,21 @@ static struct qcom_icc_bcm bcm_sn1 = { static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre1_noc }, }; static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qnm_aggre2_noc }, }; static struct qcom_icc_bcm bcm_sn7 = { .name = "SN7", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_pcie_mem_noc }, }; @@ -1640,24 +1659,28 @@ static struct qcom_icc_bcm bcm_sn7 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_disp }, }; static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; @@ -1665,6 +1688,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 2, .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, }; @@ -1672,18 +1696,21 @@ static struct qcom_icc_bcm bcm_sh1_disp = { static struct qcom_icc_bcm bcm_acv_cam_ife_0 = { .name = "ACV", .enable_mask = 0x0, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_0 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_0 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_0 }, }; @@ -1691,6 +1718,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, @@ -1698,6 +1726,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_0 }, }; @@ -1705,6 +1734,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, &qnm_pcie_cam_ife_0 }, @@ -1713,18 +1743,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { static struct qcom_icc_bcm bcm_acv_cam_ife_1 = { .name = "ACV", .enable_mask = 0x0, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_1 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_1 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_1 }, }; @@ -1732,6 +1765,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, @@ -1739,6 +1773,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_1 }, }; @@ -1746,6 +1781,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, &qnm_pcie_cam_ife_1 }, @@ -1754,18 +1790,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { static struct qcom_icc_bcm bcm_acv_cam_ife_2 = { .name = "ACV", .enable_mask = 0x0, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_2 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = { .name = "MC0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &ebi_cam_ife_2 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = { .name = "MM0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_2 }, }; @@ -1773,6 +1812,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { .name = "MM1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, @@ -1780,6 +1820,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = { .name = "SH0", + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_2 }, }; @@ -1787,6 +1828,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = { .name = "SH1", .enable_mask = 0x1, + .voter_idx = ICC_BCM_VOTER_APPS, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, &qnm_pcie_cam_ife_2 }, From patchwork Tue Jul 11 12:18:32 2023 Content-Type: text/plain; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:10 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:32 +0200 Subject: [PATCH 33/53] arm64: dts: qcom: qdu1000: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-33-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1029; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FFJMPSVIi/rnzhslrYEk6oNnRd5UMA/I/qlOvdMR/JA=; b=1yoDTc6kd8ZvHVFgmFdyi2Or4zbatDVvuAKn9V2a+ZPcKRh3aahwUN+dQ9O/e0E7q3U+zQUKY A6JH7xgCmDPA/3U9dZqnoHUGhGOMqWgfPbfvh9DBdnTZkFkZgICqPHi X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127300291900206 X-GMAIL-MSGID: 1771127300291900206 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d271e91..6e4e049b1c29 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1366,6 +1367,7 @@ apps_rsc: rsc@17a00000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118452 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp435539vqm; Tue, 11 Jul 2023 05:22:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlH+Bg5V2F67lv/R9EfhmzLD5ODN7WxvdUBNlBlK5sfoqeUDrGpJUm0LBUGmy9JmMB6YzV8h X-Received: by 2002:a05:6a00:bde:b0:666:c1ae:3b87 with SMTP id x30-20020a056a000bde00b00666c1ae3b87mr20720071pfu.12.1689078136350; Tue, 11 Jul 2023 05:22:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078136; cv=none; d=google.com; s=arc-20160816; b=dkO48YB9IdLkeKSeBsW9Sl/dkaoMWSKjQmJNWldQFbbAeDCjXD4dnVnp1UcI37kYzT nmyIygRc+SyPTGeVGZBcgxKpZRMhuJbOpqBG8PlhnLvAOPuCVqIlegcN7A8Y5RfRz4Ux mVM2PuCajXg7mN7RUdaaQHGDPu5etC71lgFQpbrvfX5gkpuAIuHhbqyjSXiVopQ5ZkMC yFT7OOhmG4uUS0YgtlKTZGuhKq42LWjYA08z6wd6ihPRWiFAa9bJM/vGFXxVQ2sQNGdR c52ySnzwkYChilesFjOnbyOl2UlS+MZgn7zfdYC34k652rhSneVI+9vu1O0lOx0ykRtM uggA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=pfbv/J9UlljbpfQkbJ1RQZoYi8S5NISMbRChDv8nMFA=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=JaXjV9tvscQDc7jacQ8BLpWhL42BWSGnCKGCkDSMIA1BREPRrOsjQb597nnQ56ui5t 0X2AV9hlaHslQ0iA/JpZxOps2JE+M0R+5gkuCkAYlGmJUkjXmIpcCEFdFcHZmOgMKocs 0AFbzMYgLUIroeAOH35cYuzAxxjLagDl6nhQhK7X/gyHETAEC/701qv+JbTD/RtlwcHV d4fP+Ny9aiszXdE38zWFww1hRo0YRkEUOUTyO8DuG5z3y6yXWLjdsoxpXzKL42bk+6Wb BWr9UqTkyjDWoB0bsaM9wJXAsr66ydfqbRRwt5jKWGfGUTURtaUbxGXt1jTXrhj1dVj/ ZFPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5HgpV8U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:11 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:33 +0200 Subject: [PATCH 34/53] arm64: dts: qcom: sa8775p: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-34-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=670; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=J+YzV1ysLrALsNig4GY1Hu1u/TnFl+lfs1ry3Cimg4c=; b=RnXcZb42j9gisrdfBq2D0dwqm5OBc1WiW3QgOhaAD3dwMseB7SUn+nM5Ps3f99EzJaYT0vBQ1 tCFypJ1rmhqAkCv6CuZsCvsUEQh2WU6TvIVwHQcQJq3Dp5uIp1YLfiD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126795883753658 X-GMAIL-MSGID: 1771126795883753658 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 59eedfc9c2cb..e38cb436ed1f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2243,6 +2243,7 @@ apps_rsc: rsc@18200000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118474 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441301vqm; Tue, 11 Jul 2023 05:32:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlEiTMvzr0XPBKJ8dFk+GPfUDlxxoMRrlf+u51W4lArrfO/FHW63lxcAVL+ZuVFy1KMzF2J8 X-Received: by 2002:a17:902:d4d1:b0:1b8:83a3:7db6 with SMTP id o17-20020a170902d4d100b001b883a37db6mr18143190plg.44.1689078726146; Tue, 11 Jul 2023 05:32:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078726; cv=none; d=google.com; s=arc-20160816; b=hHcvMNR/La15u+lgU+mn15mMippNQRRZzwygVf0cpIVyWyiHIPrzB+JjK4hb0pTSw0 IqDJAvIndwQl69b/LocMqBeU2mEhIMsSPyJt/KOs5MqxqR48dPxsuM6qiVppSSis+3m4 k+NZv1EGspPWdyhLZnQAWSPO+yplYGAjlNdAW9atDGX3MRyQuXK//HIvSmjT9aKDM9aH jd5Igoirhf+wXoeU/V1ulGs+onPoXtNqg4/aSXvvvmLXulBwIZmQZXYWUuH+pMPsqAUG GwASj5aZbcYLeMWD4ekyga8lbBNNV8LFMJRF0vgFDPBR2z/SEKPoTZtk1D4+FtAgTbLq hvXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fUYkKYV4ujMuk/ZAzUO3GhIfjlSDACYKMYMpvbHOS0o=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=czn6zsk+paITZQOwzEEkUDuk7nsALdi4Bm5MVkLvgt6zCfB6DTmw7Z9jakh2e6/ceB UAN1CQnXknkUYeBgSykNmtlLT/UnnOpkQxcdyAFzAMpeCR+RNFpdp5OG161tOOYjhMOT kSYWoN+zPLRW9Isj4G9UuLxdQJwqUU3LJIgb3gZ5dXnBjrSxjor+nJ60oUgJGKeueqdp e4I0fQcXMrHrWGvlAAGRzddbDFEYmTBNymfiBbfnvQb+y5bCHqxaW4yR0HN7TQnVZQkn jHFjiyTkHny2m+muB+AfrqRm3CCecCp98ZYmuAHigjImpOAAIzuHliyRRC+42sOn8BiK tFHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OgunhkVO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:14 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:35 +0200 Subject: [PATCH 36/53] arm64: dts: qcom: sc7280: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-36-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1025; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nytm9EolJCU+y++LKFvuDAt/1VSGVvY9ubKWLH3kdjQ=; b=MXIbUp80VLgVzHgAsczbdl+x2lP+g4cVPrIPNIvPVACY8QAdMnLDpC+0PiIwuQ9UpX4LYTGEF j+ER9dzS1+7CkKnv6yiBlm4fqAn81IIWTPxCW61QjC8EHSbst3oJToZ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127509842817445 X-GMAIL-MSGID: 1771127509842817445 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 925428a5f6ae..a45d9e12eb97 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -5294,6 +5295,7 @@ apps_rsc: rsc@18200000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhpd: power-controller { From patchwork Tue Jul 11 12:18:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118466 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440412vqm; Tue, 11 Jul 2023 05:30:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlFzDRwPTEFHFJDq7uYQp0XmsoOconWdjbTruSTNmp6mheU5TYDLwmrdmqi5t37+ESs8+MrH X-Received: by 2002:a17:902:a60f:b0:1b9:cca6:551b with SMTP id u15-20020a170902a60f00b001b9cca6551bmr7541309plq.7.1689078651950; Tue, 11 Jul 2023 05:30:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078651; cv=none; d=google.com; s=arc-20160816; b=LB5Lveb41lp4W1QH9pKMeFBUaUWrZPgwf2FeJclpvEXZVc3LjA7ecVRrnAwoYO5tUl M7QL/C3EzkoqsppK661EJWepBPuIAUNhDXkd+Dm3XNxvIs9P3K8J1X3e/4S2KVdqiNL0 WBreP4I9gJRwv0fFC4ARb02YZeUn57ZBY1XZJ8NJO9zur6G4wO//0IYP7dQkEUQ4/YPm cfk5dcq+J09hTtY6Cetg7G/CEKuydmAM4aKbjZNhXrSowEDhSjsTemw9TNMImvKm5uPW a7VJRgXT+m/dYPXHhhcOXiWPAruyu6t2R02nfomsAgm/WTOE2cWNvGPzdh17cR++8gsB 1djg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=RreYIt3ZnMFF0R9LfEKzWTch1LksZzSPzwy9Jv7pG2k=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=LBu79X0VWIBFI6OT48Zd+hr7tb9RGMmb5bWLWPVhJBZXoeVE/ezPvJUDek3l94PQ0P UpVh7HseHRjIAgc7qPm1u/+XpIhhhrTo/hoZ3R5W5fUF+lxQisjr3QskQA0NJCh5m2dZ PCxSEuu71e7iqDi98ULSXXgtUXIrpzZlsyhoWu2j4ALb+LjCZqSpwCXsXVNsFAjGWtom gK+42abZ/JDdL9YCUHOdnHp5T71R5yHr7xZ9CX14+1onXOUtju1sN7zGj3o3i/39CfAU GBeHWzTDDjbapydCx4dohpFPPGb558DI5wHUux8oPxfG9Ubpy9ywI7IWI7r5WXLrpCqT Ypjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UwgYDVcL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:15 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:36 +0200 Subject: [PATCH 37/53] arm64: dts: qcom: sc8180x: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-37-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1043; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QsxBAhmF4V+7cAeh292jLOJ0EyFZPEAL/VdNYG6uwy0=; b=EcINMFAuqr9POkjtP9ouV28bSDwaunALS/IJtAXkha5ZPq8MnvKlayBi1+JHun4UsH1AaxL5q VCJU1VpxMvoBWzhtrdtBzwPXQ4C90YZjC7B812kmR/BQepghhNjS74J X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127336553282799 X-GMAIL-MSGID: 1771127336553282799 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 11dcad9c6e94..b12d6d573678 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -3500,6 +3501,7 @@ apps_rsc: rsc@18200000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118465 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440304vqm; Tue, 11 Jul 2023 05:30:42 -0700 (PDT) X-Google-Smtp-Source: APBJJlGz7of/zBSYITOPo+j4CBD1+6b5hr3lcHsDjBjNZHole6jV6sJ+/JwWZ+ig5aU+TrYxnR2g X-Received: by 2002:a05:6e02:601:b0:345:8373:bf68 with SMTP id t1-20020a056e02060100b003458373bf68mr13620883ils.25.1689078641844; Tue, 11 Jul 2023 05:30:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078641; cv=none; d=google.com; s=arc-20160816; b=GygJmv1T2HfgfinfYtLGrIY9XMBs/cEiDjqwV6QKaMFZ6fMT0DPdIx8akPiYlmJX4b AhAGviL6y3gCSkqaCBfnTUwzGJdz+6UYgkhc3QqYMcYiHrudK+uVoHr7yvRijcb9sWTv JhBks+NIZdpx8+OMNPY2ZHJYs29ZCzY4Z6BjhvsmfNAju77cmm1tZb1DdxxCzcucPPn8 lr9JOoCTE99nkTBlPzGkHXjChpz8oeH3BjYn+9J2vzdbG4IkpWiztiN4gGjBAcbwnleX V4n9U3fABkaqxsPNN/qMsfh6eWxL79TJ0+y/lXhRervSDE4SBOtkhKnNpEn20BrS/5ZN G/8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=9mLuew5zgjzaN+tG4LFNS3rreDraB5w4e3ZMY58XgsY=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=ds23MiYOUpE4FmEDEpt75X31BKDL7rYKcHgFwDZglKpegLMcSvkSGZHNKJ7XzTfFm/ 29D2egjQQEM6NU6PDk8PELExJvanIFWSg8qmdMDk8NYz+WEs27UFkR7QYdjperfwAC0B 3Gdq04HRwmnatfEP6T9YgQNHtQm9Z0BlyJZuIRcZhFsk/PiVy/bbw2jgPqCykjdwxKCv Cw86qV17esciWzo23xBoclWndyAbEyj0AdunU5qsVJHjMJNRG75eXmYA+Lay/gZe3B6J QXLw792OMcWbxPpGDT8YdcS0QZ9wBPypuzXLqqSxmpyPhD+Fr4GTkzK9a7B5uslykACm 4gjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vvxaGnbe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:16 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:37 +0200 Subject: [PATCH 38/53] arm64: dts: qcom: sc8280xp: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-38-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1056; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hBBGgOqK76JiEy1Y4zr3la6Mn+bAAjoLLiY2eeUBjv0=; b=JKLU4Q8Oos+cK0u7H0/xlo8WQFeN27LnL/bSuf2rwkYhgICdcFnbjGEyukSjuv1FZhS/9OfPN H61d300OZhTBmJtnuW1aUe/Gejqhqj2u6mQF5et6yp7IJjx8G6/JlGE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127325808961478 X-GMAIL-MSGID: 1771127325808961478 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0756b7c141ff..67fe019b3c89 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -4303,6 +4304,7 @@ apps_rsc: rsc@18200000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118457 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp439816vqm; Tue, 11 Jul 2023 05:30:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlEK3eLuGrKU5RJDq0GYzHdrvEwHrKVeMQPvbAiQpwSzaeDVPj/OKXAo19rt8pT0x596hDMn X-Received: by 2002:a05:6a20:9494:b0:12e:b362:a3fa with SMTP id hs20-20020a056a20949400b0012eb362a3famr11678425pzb.21.1689078600945; Tue, 11 Jul 2023 05:30:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078600; cv=none; d=google.com; s=arc-20160816; b=Aq/Re56PRKmDKbbCRYHY1BT57/jDDUm/vH3EIvQiTTkWkgddP7skYWiEEUXzlD5kn/ Pq7MofEkdQqt4KcYyZVqy9FxDi1ZtI4d5IJdfupA+Ui2Dn/XNf4U+KHrD0JYGs2OBTFS 295twDWnZuJnenfGiow0J99sbQDth8OUVzHVjiPwdYqth7hhUMdM8T6XWsLo/4pU4P72 7hPjsVCkmYxgLWa4rBDBKTMr/ixk54XdyMw3OJHOkgrhovV9yJFz1XHDqhgfXMCbxFgP KEFzaAow/RbYGW6mD+7p0IodDhxo8xvPB5ik3qnQrKIVh3hAN/daaF4buG6nsXL41Nlb q0+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=t7SX5vYNZ+wh+FjSCpRImtxC2bIIfmNAdRBfKIkKVN4=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=gvRwPJoYRrW9Aaw2H08Wvb4Ir5pW9JcQp077p5m36bjAtmkgA9FAKzUiiyM0snkgtg 7A3bTne0KSRZFDZWfW6HJgD24zmcXkwfYewd/8f/D2ZiMDDJ4qO3lm2pBbdpGLQ0Ak2D kzc0hTbjo3XgMKZHMr3E++gHmTLlsOSdXvJwfv0n+hDTM2ZrYPf4Cv67k9Wa90/rG2PB EGTFTe6l2d1GJ+dM/ME/h94zYswh5qT36oF9pW83cNH4f31KJ7ty2UroXeMxmp02ocYL BZpqsGUz48V90h5CDGN+YPD2dVBeGnBrDZmK6a7ZiJORg0Z/CktmS+gJKEBsDsU1Zfir gQRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l8E9UNCs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:17 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:38 +0200 Subject: [PATCH 39/53] arm64: dts: qcom: sdm670: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-39-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RqHxnyd+iOCRwffNFe4siVguI4dHOX8Md4wGpVAKjsQ=; b=0n0uMxCZbiXY2lhF4JTtMPW5JgVP+Mrojo/yroWgbTCvcMU7OiW/Y/lZB03SHvLVohu61Lg9L XMw6pk6FW5xCFkJ5DdmkDzEt6hTEfZaiOBNO7wrancWerQ9KPhUv5y4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127282941613065 X-GMAIL-MSGID: 1771127282941613065 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a1c207c0266d..377e6ba57807 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1286,6 +1287,7 @@ apps_rsc: rsc@179c0000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp441778vqm; Tue, 11 Jul 2023 05:32:51 -0700 (PDT) X-Google-Smtp-Source: APBJJlH59A0IgAMYmgPSmSmocwpa7orIWkUhjkbQKvgG++ITiRXcCqub/5Lvxcusa4TuoiJYUnZS X-Received: by 2002:a05:6a20:7fa2:b0:130:f6bc:d6b8 with SMTP id d34-20020a056a207fa200b00130f6bcd6b8mr10750056pzj.16.1689078771337; Tue, 11 Jul 2023 05:32:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078771; cv=none; d=google.com; s=arc-20160816; b=j77exWrYBFhyGrRF/R9U9NkLoCe83kVNS0429vJZPQeFNb79KdyR+AQWRdmXSXvEkN W3V5J99QmZLD7Lm44FthhDVub+CzTY4UXexvNb6Jp/Bzu51SEkH038GlYvPyZSLUanVm P/Whvf9yKNyPpLb5ta7B6+XE6iX0rPGMP2y9zKPB9qaHxJNZB7vwVsYMMg7vQISkedky bN1mTEiX3GyPSFmceqzSK2EiaSXdcl7CBgHSIM8ANucbU1L+XBD2XwK4o3R6LkD+Xrw8 PF6ozUJVBuQ6e4bqWFaRV/TqUmkw80nawjAQnwA1VrRYU/AmHZQ3EqbCNrXFtXXjDcPH br/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=V7PIgAp3e9OzKKcu+9DEgLawk9vSlyfAdloqW5xIZPE=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=l8ZKUQLyForSxWJcmHNm/x3MFrEDPzMXFIRAWHr62EDUueMNgg9qIeR4FIUPVFNsHH d3MIxHloyX44aSCBB+0dIpajvAKXCq+d19NiZ3Jq7HErkKkAE5xi397bMjWaCj5cry1f aaJ7+EPXtRzrQNw1k74ZBLxelVCU9in4HglNsxZ8RaSOPDZGldwWmmpODzb0vhkJVTQp hBNE6vhGmMkYJ1z6mInsvrs6KyHD29xv0Ff/S8KJdwGSPGnDBEhcGzQX1M5KjoZHG4b2 Fsm236eMD4TefPDaF/C76fmBiohYm2mH7sZQ8+jjWmPazE27q0p4EFmCyz77WHbgE2/k KFqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rb2eqLzM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:19 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:39 +0200 Subject: [PATCH 40/53] arm64: dts: qcom: sdm845: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-40-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1017; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FtWJXYwgz7AFS7yftzfhIEpRiM9nqdnApDQ7r1Yxt6E=; b=NFHseIjlf47+cZ7Y6inhcqRB3z2xw6piO4cnR2TvPF9RTvIX0K9ceVjHDtw1I7mK95oxWRDkf 121F9bjlnUEDmKoJMmA69oNbSbvnO6A6uOwcOntrUzTwqLmTS4wZsxc X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127461767165070 X-GMAIL-MSGID: 1771127461767165070 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 02a6ea0b8b2c..afe0712ad808 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -5142,6 +5143,7 @@ apps_rsc: rsc@179c0000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118456 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp439787vqm; Tue, 11 Jul 2023 05:29:59 -0700 (PDT) X-Google-Smtp-Source: APBJJlGQExvaPAgEXEnjFEQN++xjr4MbbYnEXRe0UakBlXfV2RMIbkwnK7+0/jSUW+ltaVWXLb2R X-Received: by 2002:a05:6a20:8413:b0:130:46ea:29cb with SMTP id c19-20020a056a20841300b0013046ea29cbmr14886220pzd.25.1689078598643; Tue, 11 Jul 2023 05:29:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078598; cv=none; d=google.com; s=arc-20160816; b=jD2Pe4R+PP2KkA+XuGt+ktIvHXIivOsBP9ONFGudnoX/YXbcAH7UjGWRADAHBtEZvY qMNqOriDJqkwJZOlXzyyRgiOCWTkNkYK+oYiDKg4kkvI3YPxMOiiWQvE0+cNc2sTkIB3 2kQ36nbHRg9OyOTJzS6Ho2ab91FO+xH5co6FeRX4DDrHpOnfJSLYW/uDKtpVGfYBZPrZ 6t2dPgcIXZ8M5YKI+ovy+fh7qrSnuamjUFArmoqqjuNXW2aIcR3aYZmRIQ/NsgnEbrcB 9JGXiCX2AmY/N33zJBmYFG1hGfrn1dE7oyJMtOOhg0DzSTwxWCWpLH2n7avi4Q8T6a5W iQPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=gGY16j5dFZopf3fqhp0nExOr4gAGTapoNrzo7XeioLg=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=g0qgvI6zWLwklGGscT+sz5IsGqny6vYltqzb+g7wAoSaveC9P/ObL95/9inzYq/SzB BAT/1gHzndsoaiJ0DhXT35bi6epKQ6LYEMTRumzcuXdYVt2I63XbH2etmx4T8dXqzulp tmcXy1WgN7e5rH5bx/1M8xMlxFZ/zgZ3RenQBTmzG2Lr/FAU4Dag1kG/mIZWNQwPUC5Y OhBe3cP6AWdmI9fYndfFGWnl5Rpb/nXYNiNEqmg6xvoJXblWQwZCLepw4WKjH7xSnmEX suUNURGplKpHGphWH12ep/h0MArhJ2VdDP+ptKlzUUMe/MBemgNAplPAxUK4ZjlnC+Xb cfXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pDq7+w+S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:20 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:40 +0200 Subject: [PATCH 41/53] arm64: dts: qcom: sdx75: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-41-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=924; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EOUtHrbyChcnQ5Qb2DspxglgtLr61gwWppeXGW3x820=; b=z+vn8kUSfJ9dq9Q3yWFJseduC5gaarOE21ft8/BpJ1DYsiiGJy1Iry2wojZWxxk5c6ozrLP54 XHiO1PMI0YuDmRCGUL6rqp7lsMQT+e9vr33lkPKPEqerL6t1HY7Ma9k X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127280580430711 X-GMAIL-MSGID: 1771127280580430711 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7d39a615f4f7..ecb194aece80 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -635,6 +636,7 @@ apps_rsc: rsc@17a00000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp483103vqm; Tue, 11 Jul 2023 06:34:36 -0700 (PDT) X-Google-Smtp-Source: APBJJlFQAhz7cv5hcrIX/XCuMV//gCCdCWPxWJEc6A9GJuw9a5pdTG1D8B+rC7QDQvqQBaJa/8aB X-Received: by 2002:a05:6a20:7343:b0:12f:7a6b:63d2 with SMTP id v3-20020a056a20734300b0012f7a6b63d2mr14723024pzc.6.1689082476404; Tue, 11 Jul 2023 06:34:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689082476; cv=none; d=google.com; s=arc-20160816; b=xv7MfaAD+IuLIz8ojjNyf9gWtc5/wKUJRCCWHM7XmJq3I+rPm8p6ux3DMci7x3CDMT Byt+YL/AolP09GhQJmoEHM9Xtk83cy6I1+gUQ5kXdgaKx52P0OMYPvsEVgBj8ZsQAAJ1 SqurhpGRMByoOz/UCGKK9WvrXoodFy6ONzYTwZCThw3eHRRpLhnrWFVHCE8ST/qL4uyB SC2bYffRs1YZW1/hsE+qI9Aq/HKVh0GxSlGyDym8FBuBz1QxZhtksb9/sXyU6y9Znx9e Sh2Rj+ZFVOaNWJyVulXCeU1QbYA9ujo7Ee2yTqfS5ZQvFruQPtjGmmXDFyVmIowJg15H 5hnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=G9v4ZXfNPn9qlJhxs+gp/ant1A453p1BhRobLNcBnVk=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=QprQspAgO4Up4yM8TU0xT27Myo+aG/fS8SB2hJdDg+35YatsdMpT78v2aErTIngaOe W3+dcuclYs4mj2r3X5FQo6Gp2onaQuHDESALNWprqWVU5VioRVs6BenizFwR+M4LOAqQ hcM1qv0+nSJ/SBesbW433f3/JQAO9Dl8PgBX4sE+lMqThfIrAvlcd8fE3Lm9WV8OFVQi xY00Kvr/dG2TrVZVPifvOYf34xuf52y2j8w0ULYcfTmAqTFbknekLq3KTmHwMpbzURQf kuRdxh+D5rO6m/irD+ix4p1jE3Lro1f9zRxUjFSbYzzaCiPn4+jNmYcLc9xtrNKStgon DkHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Up4HteXz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:22 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:42 +0200 Subject: [PATCH 43/53] arm64: dts: qcom: sm8150: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-43-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1013; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=x0zGLJs0yoPS/RlnCeGNLi2dqlpoVvi8tNVTarjGkbE=; b=FSfXcsHn89MM1aKOUdCdC6mngIske/lMAzWCWPFQwrEpmxxUCYs9/p7KkltfVx0irKTji+kGL lJuu/TUXpvyD7WNEkqwsIUPvSbBK8HeL20eBfb7txG1n4B36T2oWkBK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771129922796944529 X-GMAIL-MSGID: 1771129922796944529 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0cd580920a92..151cc60de9cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -4332,6 +4333,7 @@ rpmhpd_opp_turbo_l1: opp11 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; }; From patchwork Tue Jul 11 12:18:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118496 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp451659vqm; Tue, 11 Jul 2023 05:50:28 -0700 (PDT) X-Google-Smtp-Source: APBJJlHhgnpXJQRfPoNu5JLZKIMNla7ftfy2JGxfS1jMHc7fD9iEpi85keotXJatP9dLlUfCLgAx X-Received: by 2002:a05:6a20:3213:b0:11f:2714:f6f3 with SMTP id hl19-20020a056a20321300b0011f2714f6f3mr11552214pzc.11.1689079828044; Tue, 11 Jul 2023 05:50:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689079828; cv=none; d=google.com; s=arc-20160816; b=f++HkoFPxOrB+Nm7GPagrEkPfv1hKdFAO/zpytT7sPvwRFUYUnfUpUvj4XmM1g3gb8 Ccx8RWtgYbGnGW+XcaMS9nxuVcogjX0c/m7j2susecGpdZf7OWhUuG2vfCoNy8AXx2Hd z870eVsdZliUoYgDJJnH1Qim0hmfnk8gLgPFSa34WuqSPpNIg3JIPPL6wdaDhCER7yJQ VgMNtxqbll+O7iBgkgMmNyfKkMU1r1oh/qvjlLdRRzpo2d3I5QgNTJdSkLO/9HBHflU0 HNij9mgca+xKnjhq3azmyGbRYIpAetmyZOaS259SnXMFvmS+Q8DFvi9CYdKKUGCqPtvI cQyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=F+HpM+HCeMpSefmXK16C9YcJaoau/C3nDGJIkf8i7cM=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=jwdL3KhKpInntQ2LbDhxeah5CR9O0MR4DdtbBthjG5Glqs8JKe+XzVa2xIjtFflkB3 QYXPojACy2cSlDDtPEoqib+U2l38Z+uMeYmeIw1DRTL4/1KAs8SMl7eTCbDXmLdHOf11 I+2SSwJoA7zuvsc2nFqFF3YzZqgvlAjTvWPDF0fgA5Iud7Xg5AW0BMnlI7q0ubIyt043 hjWqZhqBLZOSZrV1WmAIcDdozYpH/HQAKLKlkwdfr6Q25+dQE5Byp3fI64+CPcYTSP5c TDdgTVW1GhD0wKMiFYweJNHk0KvqacCIvL9Iyfp6XYB9KA8/4ZnYEs1gQ+I75BMH/U81 5+lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ul0ok/tU"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:25 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:44 +0200 Subject: [PATCH 45/53] arm64: dts: qcom: sm8350: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-45-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=921; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zd8n6/BI+I7iSUydn8vszsfz3OyuMkqkyuxPFIRsJhE=; b=E57CxKs72PQD3kiuEmwIYLAntDVsPXBSfYzwul/8gYNvLIixxKL1h9182RVK5JNqZz+6KgOal yDZg5Nh7opvDSGBwll1qr94NW+/GRz5K7PzqECKnGB2muUSSiDiiq8n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128470890721580 X-GMAIL-MSGID: 1771128470890721580 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 557a3d8e889b..fc8779a2fa96 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include #include #include @@ -3397,6 +3398,7 @@ rpmhpd_opp_turbo_l1: opp10 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; }; From patchwork Tue Jul 11 12:18:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118463 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp440129vqm; Tue, 11 Jul 2023 05:30:28 -0700 (PDT) X-Google-Smtp-Source: APBJJlFv3ndczP+6wfnWxhvcjC84dgAAQLBkOEeUtHMoTqGTub7+Uw4E0xrkycCmHFzFxrH2NAl2 X-Received: by 2002:a17:902:ea06:b0:1b9:d38d:efb1 with SMTP id s6-20020a170902ea0600b001b9d38defb1mr11456027plg.8.1689078627929; Tue, 11 Jul 2023 05:30:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078627; cv=none; d=google.com; s=arc-20160816; b=YUHyUH/7arXuBRK9GXWdjky2LX/GHX2kUvSFjEispF9gfB+udO1VDh7HxheqWcRG9S YiFKk6NGUwF9fU8pXgeAlQ+JEoAz8/F54pIFb+8fwls6OmmS+KXY6TQ+qnKrRyoOIcZQ pA2GhzLcZzhvmdIPX+KLo5yg05AGA8FB543cSqEvHiyWq9V10Pv8j67xqAQy9HXsTUeq ExzZhXi5mq8B8Fxu49Zh8LcVgzIxkyRBUgkyHCUW30eVnKijvgzNYPm6cQHbgUyX4PMc kDBS7iioqRTu4b1uA1v3AmhM2Cn6v7z/iAQUEnR97v86Qn5FvNZ4SJZL09iygzTbhnxy JuuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=B4NULi+Pg3BzaFa9S+uijdnxcMxII5T4dtt9x/IhMZ8=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=vrcWPWyTeFF46vm1mDFhOrwHPp5ZAolM9HUIqBGu7aWyv5lgqGCTtg297bBlcdz78Z lcbf496/k021oKq3TKTQQypm1zxpon2ky5Z6e5apoyR5ughIVz6KhZxETzx2tX81zGn1 a6es2mJrmFdR5a0cZ0XDyhWq8x0na0nYZ6z/s+S+ApUcIpFXxoC0PmSh8ELivlzzXnfX Z0mj1Ypo3WMlzt8JVv8PtzdO26ytHZb/86/7ci3KhjbgNspY+AxVcLoIv2Hun8xLmESW qmsu0UkXWMHPJgWZbiUI2Y+E3YoDN+jATGLxWiyF9P+Dy0S/ldIy/YDgpaQIQt5yxQqW 799A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W51lFjiu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:26 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:45 +0200 Subject: [PATCH 46/53] arm64: dts: qcom: sm8450: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-46-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1005; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SQpHj4TfmA+4UsCzDDjRNhiu3Ox+vTnH5LdKeWnrUM4=; b=5TQbA1R0ncEPLIqSN9iQ3lNCQ1W1zper+KD3P7WyAqNmnUuh156FuhAQ4i0R2vj4WhJnt0hdW 1FI94sDsjs4CxRHVepToXuIcyfT1PtDipM1ijKn6MOvhS5so+AWerUl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127311682497996 X-GMAIL-MSGID: 1771127311682497996 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1668d97ce459..9c9645809af7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -4008,6 +4009,7 @@ apps_rsc: rsc@17a00000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp452282vqm; Tue, 11 Jul 2023 05:51:37 -0700 (PDT) X-Google-Smtp-Source: APBJJlG6thlAQigq63F0fXmh4dbBIcGnq3R7ZMIoel6eOumCYEHUYgoSCOeuNaCV8xXQU5dK35Mc X-Received: by 2002:a05:6358:7e8b:b0:132:f2dc:e961 with SMTP id o11-20020a0563587e8b00b00132f2dce961mr12747784rwn.10.1689079897547; Tue, 11 Jul 2023 05:51:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689079897; cv=none; d=google.com; s=arc-20160816; b=sBduS8SR1QPFDqNgalTzgnhflYxrXepsArddnPUXA+HDN9L9JR3kmxW1pRDMvOFHLV Xtl3n8FrfBY/aGPVurrcyd6cYAT+3TH4YMRwGi+28V77bKA+79xhCAMEo/THZQ/946UN xPAYK1/ie5CzRqe+CxJEZ36moJUBwgk2HP1sUtUfZKge9ezE/IDNVT8xmQYJyR/pZd9X VuUj/EN6jw2ukTFWYPi+Uu6pns55OqMAo3oaffVGefLzneVpfO+RuvFUyGZQuNBgdCY6 i0/JnIfaJI0LgUbCJJwnH83BEv0ygTyVcs//MxOCui5YaUxSavHq3meZSNQELptC1AMi 8wsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=IQLBnYw5pfVzQylFNgskr7H7oEW4uSiPIu84jcjkQCk=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=rAmD8PFSP1q8/K5IDc2+oZU6xY86KxIoobY934EqXf8ki7YeQdUVwRFkwkVOxM/rLy PaaNQyyqKpmsH2xNGL1fSEykuSLURtB/qwUPSzUqvw3ArYXSKTfsKeKE+UgwD2s7A5gn AM9lsgRpyo14UlUcHgoyIzp+FUcAMF8PWAYasdG7hA9N1iVYNLYFGEC/3wuJzSNClnSE c42vQT70G0TWXqwcmfhLEYwxsTme2E8FHyHWRAKIf0qzgQZLYHa3M+powzf2Bq14Dwt7 JRzHqcdt8uhgVoPgrBXEJAu6Ss9ROdMEMCzYzXTSIRgkMGIY6xRfIBrr1slxJv8avz2X zzdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VuL7tBUV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:27 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:46 +0200 Subject: [PATCH 47/53] arm64: dts: qcom: sm8550: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-47-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=2n73VwmB8gd6z5jxJWL0kWv1/JV05PWG3zpj6M//Tvs=; b=6cAucdktEPv499aSOqbmljlM2KKvs2eSJ07hrXrAq/GVNAj6ilgikTUSIcX93dYozWDDDBb7g UwYMsvaySf6AKgM7Tyt09TTWQN7rdv3hVkop9AW3R7L1dPXgX0KPAkN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128642322539697 X-GMAIL-MSGID: 1771128642322539697 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6e8aba256931..d54b0ac6d0a3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -3714,6 +3715,7 @@ apps_rsc: rsc@17a00000 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; rpmhcc: clock-controller { From patchwork Tue Jul 11 12:18:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp453039vqm; Tue, 11 Jul 2023 05:53:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlGZvvT2pWMuri/RuPSRv94XHC7Tp7T35OmP9gtdZLA1mB9sOj5PsagD0+mebdccLriMKNNY X-Received: by 2002:a17:90b:1b4f:b0:261:49b:d65 with SMTP id nv15-20020a17090b1b4f00b00261049b0d65mr17705768pjb.28.1689079994681; Tue, 11 Jul 2023 05:53:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689079994; cv=none; d=google.com; s=arc-20160816; b=L9kbtZncg0gHaShFp2RWRuWph+qv0ab5TgdogiyjZUmYef4eOm0DDMnjpMD3Imq5Xm I1mBYHPTz/A06p+n0794jPR+DIB5RJwOsACnL/fYSE7eEgpNbs7JBbgj6alZ6wMGex2m S+zWZ+zpEQJ6GdGYlFuI8NXaJ7bTGl3iE7tvsAbpZ1e7GumR1XnjWU8K6Xr0eTVgHqnH d3CUl9hSyj8sCFRclvyeipk3LfHv4HUccdOFekv8u6jsSlYGI1v1yUE53hUbjkqzmSiG JX8zoP3R8a/0QuJUHJmwUNGO8q1HtBBuT0noF/vQxumkhVFcPnYydeOudogKy/4Aj6/s G7ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=NaXHvKCxI7KxVS1KmSwJhdeP1kNsqjjvViQ53Us8p1Y=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=FJ0qzndN3EOz0BxjlPCo324oyvpk9+SQu1k3fZD5DjZIC2p8f53tUzFEfLCfTwdddO s35EmWFkCG6Wbm5ku5/3EWDCoHVdTWwi49h2MMw/yZy1nu5+BQW5Gt5sqe/KwyVwBJAP q3nNthTVGMf2UNroJuXG4jfxxjmVduvJ4H17p1Xi/Zgm+O9LRg+KXAK6Re+udhxhlIfy dlfilV0RK0+EWwM/f5+jmYgnxSCgSSspyohEjHU+9bjFFmm/2lNzRjk6Al4qa+lMS44A 88OJ1p1vdSIYo9L6YIxDOEaN/BGwPcxz1+OnIMscOXoG/Bu8OBuPAIsDH3/lgUfmxhEU PV0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f5mqGPJo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:30 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:48 +0200 Subject: [PATCH 49/53] arm64: dts: qcom: sdx65: add qcom,bcm-voter-idx MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-49-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=652; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QPuW3Rel3JulR94tJfYoeAL03RliO6PUnmcXiEkxKJ0=; b=opllT+GF9a/Bed6/37yPX0plczgSYkuJUB3jZRB8+yo4DeCEiTP93/R6hdGMr7/rzPqNVd68W wutnZ86z2tyBySDI8bN7TTvFabHscB2+atTO98lTHMANJcn9Wutslt+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128349242337222 X-GMAIL-MSGID: 1771128349242337222 To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 1a3583029a64..7efdcb2a7a0e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -795,6 +795,7 @@ rpmhpd_opp_turbo_l1: opp10 { apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; + qcom,bcm-voter-idx = ; }; }; From patchwork Tue Jul 11 12:18:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118453 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp437103vqm; Tue, 11 Jul 2023 05:25:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlEwTfCLt9D2Vn1Kjt56zP7eGpX7SIccpCPpUZqFKJSnhETijVB030LhST/4QgfObC2Lz+04 X-Received: by 2002:a05:6871:29b:b0:1b0:7eac:70ab with SMTP id i27-20020a056871029b00b001b07eac70abmr18924110oae.41.1689078311126; Tue, 11 Jul 2023 05:25:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078311; cv=none; d=google.com; s=arc-20160816; b=0s8qq6hteARLtUT373VoREpmpCynC4NFwrH1qGDyCPYTNwTIFGmca6/5GLOp/JegrA G/6k/p2LMxyIinsd4jX835A3ezTGlrZDzzbaqAzKQg5Tco4w8P1Vwm5DxW/y9AY1Ze10 Mmj8pvZioZacD5Yv2oiz03n8x3wAOOzodQ9fWa600WjZfgbYyoe7/605sxKBNUCGIvLx XnofNuE5bFXMbPaFxffJFt/WOnwYtuLI7drX+9Vms1LfpC9RX/eF0ji6j9MxrWxgSl6+ GIN7REN1k/+65FQyOCaGqpzy5drrWX/M6rcA0/0DVft8RWx0zCvLrhpB90z1o1Yc/dSD Nkpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=/asgZ03NiEjGsv4yFwqtkX/wMZgRigqk79OQqEY/FpA=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=VMkXPmBSTDpkR+wEkM0REd6SnVdbx85c/xsqPC1JizzDJfypBhJb/d+CQymeqcmQu5 Tf5ounDUnn6bgdrvRe9R/s/zABdntwDmUNwNykm2iST5Mgmmh3Dcw+gtbbYLk/mMSvzh 7FYZ6qpRn8KZ6oJDa5RFQR2z0kEmXTNM8Mw1JNNn/iOQyZiok2SImm/Pvc0UwIB7Tgas jlZRF14dLxphhZCV2UQiSqXEsAr0LcApVzwM3CRL1NSe75oUIEQYKpua8pLlc3EJEnev M0hO1HX72IRPsz+cXE8p+x0hRmlQtqjKhrkXpoJ7fgp0mo8cj9cuobB+0xaoOxuoaBmd pNTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="hCpfqLd/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:31 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:49 +0200 Subject: [PATCH 50/53] interconnect: qcom: sm8350: Point display paths to the display RSC MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-50-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2325; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4cN3u17a4Tjp9KwmLVHyYCuynLOUrKPYJniM89DUm8c=; b=TCiw8Gn5E+kROybJ7eM9HDAHOFyDwfav4mFNcXKQuvK0+BeKxlWbuCdcJLWAdcb6awXlEbvSA 6TqOK3Ni0LHAsoY4ARc1sb+WTzVrou+euI5hOGVp7EXrDzsuyVwnFNu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771126979142674735 X-GMAIL-MSGID: 1771126979142674735 The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: d26a56674497 ("interconnect: qcom: Add SM8350 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index c48f96ff8575..0466ba5d939a 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1609,7 +1609,7 @@ static struct qcom_icc_bcm bcm_sn14 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &ebi_disp }, }; @@ -1617,7 +1617,7 @@ static struct qcom_icc_bcm bcm_acv_disp = { static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &ebi_disp }, }; @@ -1625,7 +1625,7 @@ static struct qcom_icc_bcm bcm_mc0_disp = { static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_disp }, }; @@ -1633,7 +1633,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { static struct qcom_icc_bcm bcm_mm1_disp = { .name = "MM1", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 2, .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp }, }; @@ -1641,7 +1641,7 @@ static struct qcom_icc_bcm bcm_mm1_disp = { static struct qcom_icc_bcm bcm_mm4_disp = { .name = "MM4", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &qns_mem_noc_sf_disp }, }; @@ -1649,7 +1649,7 @@ static struct qcom_icc_bcm bcm_mm4_disp = { static struct qcom_icc_bcm bcm_mm5_disp = { .name = "MM5", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &qxm_rot_disp }, }; @@ -1657,7 +1657,7 @@ static struct qcom_icc_bcm bcm_mm5_disp = { static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", .keepalive = false, - .voter_idx = 0, + .voter_idx = 1, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; From patchwork Tue Jul 11 12:18:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp449579vqm; Tue, 11 Jul 2023 05:46:37 -0700 (PDT) X-Google-Smtp-Source: APBJJlGG8tRm6ahkOgzETZLkU9PQrRhvICbV1YZ5ompH+CvK1ePsLVnStDoN76B1HmH/6piOvfNk X-Received: by 2002:a17:907:2c66:b0:94e:2db:533e with SMTP id ib6-20020a1709072c6600b0094e02db533emr15323226ejc.49.1689079596875; Tue, 11 Jul 2023 05:46:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689079596; cv=none; d=google.com; s=arc-20160816; b=NLmi9voHmkuTCSWtdpspZmJf1Zr3KfuF42Ma8nPUNNJ5xOF8BpO8NVCv4VoEcjUQo1 Prn7GuslFp9mkCe4IhAbVA4ORYoOwuKF3ArxZpCquybfwAlMOpZ4wyHRNb13PfCpV6xi TFA1spjIgXipRLx3aIDrXKI3omYUomz1Ck9jUMYnd18TgRoBKlh6SX5jrZwgG7oI4IEY CEedoO6iF4NImgGqsP2eSDZRRzxHPZ0hyJe0J4epaBpeVV2WUrjOY3qv213BLj2Obt8W 3ctGrGsxtOnpmr9Pscfqj0sNHmr2m7UiqXurYJU0M+UGOc8199qq7dYLlES3qdzU0SpH BY7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=9qEI9ih7CsEfqqcZVsPdCla2s3zGk1zpIvdrNZp7GUo=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=y92gxcbnXPSvE2W13L5i+zyuA8PA2aaKlMJEXDzu5OOYeoou+OJoMenQSP6UdUa2cN uqvPUTCzjRxz0qBui1qf3q4zD5MZDVZ/HxIPYVWe+Rart2DleL50SSBMNVpqxGweeico TqbYx2FZpuirP3haPlXpn/NJ1ZOe67oWrNPSskFFocZulcdVdQt01jK0u5GskuSP1vl/ CwCTJll7/lVa9Nc0x4c1o2qE9353PZckVYapxcZWEcnlyM3UvZnlsGNYxfN11vCVYlqW ojy29C7O9WDaNC54P8SmNKkiz4zz0e2r9eQ9DpxzAHnL5aIMdv2vUq4gZxKS09LDP809 uYNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q446X4P+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:50 +0200 Subject: [PATCH 51/53] interconnect: qcom: sm8450: Point display paths to the display RSC MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-51-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2103; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GAWOUV4QJe60q6M3sv3YLGxilMGxFFgLlCxXc4BU++I=; b=n6mHwI5Knlo8QwAZ9UuQJZ5TSMk5uicF8dPrneNhYlmJUFzK9gguKI0KQoyfgn83kx8zxL6qu BLXqqqUvr/lAd5PsnBNC3JILtU6yS5lpYZClOMClAFtFiipSLnQ2MVw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128327030370279 X-GMAIL-MSGID: 1771128327030370279 The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: fafc114a468e ("interconnect: qcom: Add SM8450 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8450.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 989ae24f2be9..6f42b1d693b4 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1517,21 +1517,21 @@ static struct qcom_icc_bcm bcm_sn7 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_disp }, }; @@ -1539,7 +1539,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = { static struct qcom_icc_bcm bcm_mm1_disp = { .name = "MM1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 3, .nodes = { &qnm_mdp_disp, &qnm_rot_disp, &qns_mem_noc_sf_disp }, @@ -1547,7 +1547,7 @@ static struct qcom_icc_bcm bcm_mm1_disp = { static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; @@ -1555,7 +1555,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &qnm_pcie_disp }, }; From patchwork Tue Jul 11 12:18:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp451265vqm; Tue, 11 Jul 2023 05:49:51 -0700 (PDT) X-Google-Smtp-Source: APBJJlEQ1sM4QzuDYF3ocA8RWfpynaTEgdfmcGJ3+qY13jf8wCCkH2oVOpPscgbNiAjHuCRiYwVy X-Received: by 2002:a2e:8784:0:b0:2b4:7f2e:a42d with SMTP id n4-20020a2e8784000000b002b47f2ea42dmr13922634lji.41.1689079790887; Tue, 11 Jul 2023 05:49:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689079790; cv=none; d=google.com; s=arc-20160816; b=f5vrO2AMDH1z0Z11S5x+mzmuVc98FOA4QIacH0WcTY7oBpcRDJWs9A2tAWBgJp+P74 p4ztMStXNfwnWznvHI1Jv/kacO+lm5weKadf0qGRHPzUkeNpVO7/BA+dLs/Jd5W2E6qw lHGKtp1Nyd46bGcMsR7TizjwE4bNnllp++BKhEpUy4ra9rGArlCJZYq6TTB4anlhPGOu qliLM9oAMJhyKZtsHxT2wx8D9y6DvFdv3stDukpJAdQ3A8wt7i2nkYFmq89bAjcAoneh 9CId2nY2YXMiS823uIckp5RNwyO9yD6bO+ekMqfh2W81DP6q3efvrTpz83HZDyrkmpX+ hqlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=K8XB0b36gPmdiQ9so1TqDakH13y4NHB3DOms10+ba6o=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=DsGO+ki9LLcNjcZwl0wZmx9pshkE+NqdfVYwKRYwhxBL2gP7JAtP0AV8JqRXFoIm/Q 6bUUgFox2SHFTTNSEuutbIv2z6SFSCfte7KuVGeGnVKKWOj5ogdCuB8Ygk2Bxwx50yt5 Z57XQ2psdjJjiEtRh1GTeGe6r4wF+FWKJW4tTKdN+gcvCjOgUNttVDjgEiE4OD8vYavL S7U3rc0s4T6YnHyLeuUTyyDN/Y0Gf3UdEzKZG6DYHZTUW0mH1lc5AVwQ+7Wlz0rRn/h2 gYoNJ+PPFqAE2+fAUTg2drpgSIOBQp7/k3sDvBZwUwK3xs6qNFrO5O1hEeVXjCGmpTKl TWmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q23OvF0A; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:34 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:51 +0200 Subject: [PATCH 52/53] interconnect: qcom: sm8550: Point display paths to the display RSC MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-52-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1733; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JL7o0mask7WGyT5OOgpXbZTfu4QypRbPSv6ivg1xHjk=; b=g5PEcaastA0+757hGRpamUu4K391F2PnVaPxUU5BCcKmXycbS8JudpIcZ1n14tPUfV/YxXGAr u3V8Yb4LTMMDYFOs18dH266Gk0UlXoW91XeF42ZqHdbF8MAGoK9VKp+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771128530627171611 X-GMAIL-MSGID: 1771128530627171611 The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 40740cf5e41d..41314b214cbe 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1659,28 +1659,28 @@ static struct qcom_icc_bcm bcm_sn7 = { static struct qcom_icc_bcm bcm_acv_disp = { .name = "ACV", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mc0_disp = { .name = "MC0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &ebi_disp }, }; static struct qcom_icc_bcm bcm_mm0_disp = { .name = "MM0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_disp }, }; static struct qcom_icc_bcm bcm_sh0_disp = { .name = "SH0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 1, .nodes = { &qns_llcc_disp }, }; @@ -1688,7 +1688,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = { static struct qcom_icc_bcm bcm_sh1_disp = { .name = "SH1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_DISP, .num_nodes = 2, .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, }; From patchwork Tue Jul 11 12:18:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 118479 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a6b2:0:b0:3e4:2afc:c1 with SMTP id c18csp442155vqm; Tue, 11 Jul 2023 05:33:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlH0/wjRROdXzAWbbHM9/hFyM6d7RrDyQVHQ64qHOoOi9uShPKlcE/5O8rvupHxHgiqharOz X-Received: by 2002:a17:902:c20c:b0:1b8:4ede:4a0b with SMTP id 12-20020a170902c20c00b001b84ede4a0bmr12050911pll.9.1689078801535; Tue, 11 Jul 2023 05:33:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689078801; cv=none; d=google.com; s=arc-20160816; b=QVcsM8KuNIVDHpXDtmT/HFaUArOI2k2LKAyoBK9/QBZ7GoQzegllU6rfjk8RDnmOML dxJl0lrk5WYkSrpF8OBsalC2AHlRjJdZsxttmwanAfVn6Y6SlkeM/tySFAu5mDPCcpbw K71DQP3CGuOf/5RQvNzz129q7/MzJGfhbfjHzOCiwd4wfW3arjDdyxI19XUj31M4nzkk C6OaErid5uXvYhpNoZgLwaFrJHqtm4OySjGgqmiRsCMqAofZq3AmY7mW2791XjoQ9fp3 aQZ9gKS9p3ZK5uqHv/qrLC0lQnxU9E1bqdYq9uC+vcrb5fM5MO3cjrApJz6wJptnUFsu v1hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=hSHC4l0gplSJLLulVhlWKIZdx5+fKnKYFEmJEyGDU+A=; fh=JoAcrgft0uy82XIp94lSiB7rWiE0KfkQABjXnED6+RA=; b=MkZucHCuJ55lYuyCJ1QOHxvPGgbg9lvUOBVFDgz/X4kBR1Lld0Uxib2mElUxdBpSF0 8AhAzBKxiviL0bhfxoJd61+Zbk8xBcCMgSGJvBUvsNGLdDH59sDPsWZya1L8FUbQAVh9 i1z6KBDsU9hE+zl54jhDdov6w7xkm92Ipbyg10jYtO/ywf6xu50hTRdmHH68ekPXS3+y yEruw5WmqIIUe986oceL8UYMhYlOMBq11MxGf9jyYuqZV0cpllrH6oAK408uJJTagS1C Bv+1awB/KWJlZzvza4gzpUjFk9V50zDZhilTMTzrvBBKhN3cFduzNEDgyC2nzKwS2bCR fceA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=foJDSaBi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:35 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:52 +0200 Subject: [PATCH 53/53] interconnect: qcom: sm8550: Point camera paths to the camera RSC MIME-Version: 1.0 Message-Id: <20230708-topic-rpmh_icc_rsc-v1-53-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5762; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=W6na5tQubESsXoW9+LUn1M9R9sjGfLBb8AasT+sD/gg=; b=LJKdtd94KUc+CXD5JNWf2ab3MiRf13typSRJvQgEbZhLudJiAhYDUF0t9U94EeCcSdhQdDg6d QOliq5sd1MMASebL8OKCdJ1d1h0gofCmuRajrDkEZu5wA0dZ9sXu5ii X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771127493645936667 X-GMAIL-MSGID: 1771127493645936667 The _CAM_n paths are expected to go through the respective channels of the CAM RSC. Point them to the correct places. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 41314b214cbe..8970fd6505f5 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1696,21 +1696,21 @@ static struct qcom_icc_bcm bcm_sh1_disp = { static struct qcom_icc_bcm bcm_acv_cam_ife_0 = { .name = "ACV", .enable_mask = 0x0, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 1, .nodes = { &ebi_cam_ife_0 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = { .name = "MC0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 1, .nodes = { &ebi_cam_ife_0 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = { .name = "MM0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_0 }, }; @@ -1718,7 +1718,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { .name = "MM1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, @@ -1726,7 +1726,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = { .name = "SH0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_0 }, }; @@ -1734,7 +1734,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { .name = "SH1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM0, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, &qnm_pcie_cam_ife_0 }, @@ -1743,21 +1743,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = { static struct qcom_icc_bcm bcm_acv_cam_ife_1 = { .name = "ACV", .enable_mask = 0x0, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 1, .nodes = { &ebi_cam_ife_1 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = { .name = "MC0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 1, .nodes = { &ebi_cam_ife_1 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = { .name = "MM0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_1 }, }; @@ -1765,7 +1765,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { .name = "MM1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, @@ -1773,7 +1773,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = { .name = "SH0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_1 }, }; @@ -1781,7 +1781,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { .name = "SH1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM1, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, &qnm_pcie_cam_ife_1 }, @@ -1790,21 +1790,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = { static struct qcom_icc_bcm bcm_acv_cam_ife_2 = { .name = "ACV", .enable_mask = 0x0, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 1, .nodes = { &ebi_cam_ife_2 }, }; static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = { .name = "MC0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 1, .nodes = { &ebi_cam_ife_2 }, }; static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = { .name = "MM0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 1, .nodes = { &qns_mem_noc_hf_cam_ife_2 }, }; @@ -1812,7 +1812,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = { static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { .name = "MM1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 4, .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, @@ -1820,7 +1820,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = { static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = { .name = "SH0", - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 1, .nodes = { &qns_llcc_cam_ife_2 }, }; @@ -1828,7 +1828,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = { static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = { .name = "SH1", .enable_mask = 0x1, - .voter_idx = ICC_BCM_VOTER_APPS, + .voter_idx = ICC_BCM_VOTER_CAM2, .num_nodes = 3, .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, &qnm_pcie_cam_ife_2 },