From patchwork Mon Jul 10 09:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904426vqx; Mon, 10 Jul 2023 02:50:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlF/IwmvsWR4x3Ow8gmIhpYPvblV54YHvKyZxK98g8BtqB3z92rXpTolZ3rIO5eWOnuPxv+H X-Received: by 2002:a81:8410:0:b0:57a:8736:a836 with SMTP id u16-20020a818410000000b0057a8736a836mr2023793ywf.31.1688982630999; Mon, 10 Jul 2023 02:50:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982630; cv=none; d=google.com; s=arc-20160816; b=1GlHzucljOpYSiqfQfNwrR4dhLGZUBpArL0NCK0Gc6ig1Ah0ucyUWfhaZ6i1RZT12i vWNUFDQiXbB/guW0rqXnBMgMcqVbt8rh4hL50FWo76G6rfgCMcx/cSYGxTUw2BFlgvP/ v2ee8mqZeXPru43x0CxrUz2NUIJqGUDrGh7TDO35RliPfbQdkOGdVxnUF9eSuymCzgTk A0ZNRg1HqgjWBcu2QdLRMrr74usyHaVR+CdPF1sD9c65M6xBiqSYvLC3qBB4B5s65iQT M9/1A0RBz4mEzMtbmm3AVVooM53DaStrd/UbjvqpWqNOmw0a56SQb6N5+eAfdGgM/w6m wg5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kEcZFxL1PL+URZAYnjmsniH6517OiRx8Qdyeu/i1/j8=; fh=NmedlpijBMacxlBO1NzbUohgLks7RaHl1/2Vvbaff2U=; b=w89tEW/9GwfpnExO6joEBKLynQE108XusPQOFFCPRdyB9Qyvr2/CxySHyypDnTLwv/ aWV86iCA7vw9c7VvFVbnFaUsrFBm0DSw+1d7W92Dmi79NRlG+qetRGCqDpO7u+jCgIoi P0oPO6PholhmNUIzd5z09GNWo5XIB0sa7khDyaGF1btT+Gt7CSmDWJnzlGGFR/At99Ak pu6dBruZiu15f7xA2e4+WK1/knGRRBqcg5EZ2p99/P2XpOcbrloOvDCGyI6Lv8o1Q5k1 NCTsGYFoDsjX+GABTRMKJrIG5NYrHubtC8Tx+jcJv1QN3eRDPZ1iVKZhmQFxxkEojxt1 h3Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LjiZ0UWz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r38-20020a634426000000b0055af2b13196si8546111pga.501.2023.07.10.02.50.16; Mon, 10 Jul 2023 02:50:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LjiZ0UWz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232762AbjGJJjh (ORCPT + 99 others); Mon, 10 Jul 2023 05:39:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232678AbjGJJjF (ORCPT ); Mon, 10 Jul 2023 05:39:05 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 193D0BD; Mon, 10 Jul 2023 02:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981810; x=1720517810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9j52FthJZNa9Xc0YEIj+5Oie+v4CQc4EqZA27meU8go=; b=LjiZ0UWzfTSHar9LrQIDvRQjUj3uM8R00nuWPGwo9GHiYO0QhLMpb2rJ zVhAkGknL6L8AUO0oWtoBisnHJq59X2+xj9L6dlH1SUCnaA0Lk9Gexi7Z 7ffxWyOAJIXvSzDi4fqsejsYvKr70Q+y7eJXXflPTgxn3XsYthvEyY0xp 13xf5pcfughHOz3nNOdtFQYeFS8iG0ospob6qlznC09jF8KIvitvR192r 2TTLE9Zum2J5UFC/JKO+psSXAEFgNPZ4qFM4H3i0FNgZt8WsKiIcFpYhi pFFaBWPNeRO3xiqnQR34eBoZdpocyM3EtkYF37o0qstk3iWBfHHVeteQA g==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="222123395" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:36:31 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:30 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:28 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , , Palmer Dabbelt Subject: [PATCH v4 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Date: Mon, 10 Jul 2023 10:35:36 +0100 Message-ID: <20230710-uncounted-suffocate-633f57fdecab@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2940; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=9vL9UTnWKFum0JN16SUa6SYVYB7LNXsYDcHCgjUs78g=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL1zluRT2YZmquMAyIc6kHKnm7D/izxmq564XT3Q1W7Kk 63p0RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbiZMXIsHBpUphhktkj17h9USxOi/ oe7tj+nNHlWWrzwuB7DgHXvBj+F2ztKjc4v05c+HC3hVFH8fUnVxyV+BfJrt3aIbHp0N1p7AA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771026651505292365 X-GMAIL-MSGID: 1771026651505292365 From: Palmer Dabbelt Right now we provide a somewhat unhelpful error message on systems with invalid error messages, something along the lines of CPU with hartid=0 is not available ------------[ cut here ]------------ kernel BUG at arch/riscv/kernel/smpboot.c:174! Kernel BUG [#1] Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 6.4.0-rc1-00096-ge0097d2c62d5-dirty #1 Hardware name: Microchip PolarFire-SoC Icicle Kit (DT) epc : of_parse_and_init_cpus+0x16c/0x16e ra : of_parse_and_init_cpus+0x9a/0x16e epc : ffffffff80c04e0a ra : ffffffff80c04d38 sp : ffffffff81603e20 gp : ffffffff8182d658 tp : ffffffff81613f80 t0 : 000000000000006e t1 : 0000000000000064 t2 : 0000000000000000 s0 : ffffffff81603e80 s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000 a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 a5 : 0000000000001fff a6 : 0000000000001fff a7 : ffffffff816148b0 s2 : 0000000000000001 s3 : ffffffff81492a4c s4 : ffffffff81a4b090 s5 : ffffffff81506030 s6 : 0000000000000040 s7 : 0000000000000000 s8 : 00000000bfb6f046 s9 : 0000000000000001 s10: 0000000000000000 s11: 00000000bf389700 t3 : 0000000000000000 t4 : 0000000000000000 t5 : ffffffff824dd188 t6 : ffffffff824dd187 status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 [] of_parse_and_init_cpus+0x16c/0x16e [] setup_smp+0x1e/0x26 [] setup_arch+0x6e/0xb2 [] start_kernel+0x72/0x400 Code: 80e7 4a00 a603 0009 b795 1097 ffe5 80e7 92c0 9002 (9002) 715d ---[ end trace 0000000000000000 ]--- Kernel panic - not syncing: Fatal exception in interrupt Add a warning for the cases where the ISA string isn't valid. It's still above the BUG_ON cut, but hopefully it's at least a bit easier for users. Signed-off-by: Palmer Dabbelt Reviewed-by: Evan Green Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..3af2d214ce21 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -66,11 +66,15 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) { + pr_warn("CPU with hartid=%lu does not support rv32ima", *hart); return -ENODEV; + } - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) { + pr_warn("CPU with hartid=%lu does not support rv64ima", *hart); return -ENODEV; + } return 0; } From patchwork Mon Jul 10 09:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117773 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904797vqx; Mon, 10 Jul 2023 02:51:32 -0700 (PDT) X-Google-Smtp-Source: APBJJlGDSc77ovIiMaX/FlSdtR/fdpc2j0o5cpb+dt9OuBGISr6lQoqJOweUKN1F7VpcSUXtawwj X-Received: by 2002:a9d:65c9:0:b0:6b4:77ed:e981 with SMTP id z9-20020a9d65c9000000b006b477ede981mr11755951oth.6.1688982692099; Mon, 10 Jul 2023 02:51:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982692; cv=none; d=google.com; s=arc-20160816; b=xx5BSvj+pfhvgO4vfhUSAkpxZnFPj5jI766lDuK4GsHjA3hWN5Vay28uiU9tscO4pS DkTjAyIzpyINFfND8d//KwUUGHdUQFvqtSc5ty7dy2pmPN2dDAv+EsLtpFx/tS77UpiW chArPKZKy4Cig9TQ0sq+lgIo3Pn9KPQI559yHEFgQOllntxOwdWlZQ9WR6MDiW7zqUzm 65qKILxWYpD4JkXNaDmeG5iTBps49zsOH1Cus/TZSLwkr+ITPxkEgKGAMAdXv5LrkH/z bRecwANPjSwaSE9hZ69SU2Z/2YtMAdUXsyC3ZEeMk7YuzlxLVqmffHDBFvw41J4jfo9Q 6ZMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=i4BvSXkPJxBG2My9nNlMr+UL5vwTSFvfKXDWWGvTiZQ=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=FSorPDQEaIYLPpIZDfm/oE7aSHpEQ7y7hhQsiPIryr6WYd/siUDiFDx3Bz7JB3Gvuk M5Es2SPzjRBPHS9/qNJPofMBF5OAV3R+eGKQ/TJCxUtBwVO6+inl/AVUKgLnqkGSVTzO MIsOtUJkn/76Ho0spmXevRwMgDRhmvARO9bR1fqbmAJC2u8nwsrHQ+ofTBDznZXIJ3Vw UBzvjsLMU8AFTKvZCCb/baWTA+xFLc9nw/Qg51cZ/sb17D37KpIiLBtudOTnDBidSEQ/ +33cmVSNUX9CJjgFq8vFY0579EbEAta0TXZVvpOXr8f8TXuD1qg/3QxBCtPjNnCin3IC GmGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=GkwOWqQ3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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So when recreating the runtime isa-string we can also just go the other way to get the correct starting point for it. Signed-off-by: Heiko Stuebner Reviewed-by: Andrew Jones Reviewed-by: Evan Green Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley --- Changes in v3: - Fix tabbing of print_mmu() Changes in v2: - Delete the whole else & pull print_mmu() above it, since that's common code now --- arch/riscv/kernel/cpu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3af2d214ce21..f808b67f5a27 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f) */ static const char base_riscv_exts[13] = "imafdqcbkjpvh"; -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { int i; seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); + if (IS_ENABLED(CONFIG_32BIT)) + seq_write(f, "rv32", 4); + else + seq_write(f, "rv64", 4); + for (i = 0; i < sizeof(base_riscv_exts); i++) { if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) /* Print only enabled the base ISA extensions */ @@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v) unsigned long cpu_id = (unsigned long)v - 1; struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); struct device_node *node; - const char *compat, *isa; + const char *compat; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); + print_isa(m); + print_mmu(m); if (acpi_disabled) { node = of_get_cpu_node(cpu_id, NULL); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) seq_printf(m, "uarch\t\t: %s\n", compat); of_node_put(node); - } else { - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) - print_isa(m, isa); - - print_mmu(m); } seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); From patchwork Mon Jul 10 09:35:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117784 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4908113vqx; Mon, 10 Jul 2023 02:59:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlGJO6jc95M95Fm0EtIe3BOV2UKOE2pOiwkjPF064YP7oawGT3N41HgRNUcflcpDwvW2CaZ5 X-Received: by 2002:a50:fc1a:0:b0:51e:22da:186c with SMTP id i26-20020a50fc1a000000b0051e22da186cmr10166657edr.35.1688983195880; Mon, 10 Jul 2023 02:59:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688983195; cv=none; d=google.com; s=arc-20160816; b=inQvvmOhOQfafLZH6VAsBo73n7Z8VnbjuilnTZ9F70o5y3ScH7R5RM46iuwRnU8TZp kVmlhmHBn6CLqW8urgpylKchokqgq8oINhrcalPBm7Am/oHMeIC8J7wXGOd9X6SgaD6o 0/Cs7ZzG1mkSmmjG51ObJzavUrt0SKC1QFtZZMo4eGj+UWvFUQiTAOPKg9ZG7mLpwNXH vkjWxqQGTTX6O6oTVFHVuX3UaHacqD6mUs9VJqZPMTRmEinJOHdmoxc79SRQTLMoWmiG ko5ZUlv8LPEGUzKluhKg1Fske7ZcbUa2/FOPr7J5Donj0s4AP03aTEBU7FUKiMimdoFN sjZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vC1BnLacuWIn4JP44zo+QlFO9OWCrIZRrezYlKwlTx8=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=BsqY7fEE0TfS75mZugf3GTP+fJ/4F7zDDn3GWLvzQdx4VkpupEHjFoT2U4Vb0jYUro NVf7OWZj/ii6VCNUINIoWNeotmG2LWOSMM1DheWQfnsO6zoACEMJdSc5WUa0FSM21oVu PVztcapnqw08aFiKVnneBi2NJTnaAooP3tksRl2hZfPuMMOk13bqpe+ggUUrHjm1LB7c mPNuuLtSVbshNlIiW0+gWxLNmdz0W+HgYEj5bErRhI7FyF+DoqlJmWQLUrB4sfJ8lMO5 A9CtfqOjxV5TEldYOc0dNO5P4hmYWW7B1TyHRhJB5dabCOy1Q/WdtSG4ZmBGpyULrTg/ KndA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=dkU568SU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o5-20020a056402038500b0051e3cb448ddsi7857754edv.390.2023.07.10.02.59.32; Mon, 10 Jul 2023 02:59:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=dkU568SU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232879AbjGJJjz (ORCPT + 99 others); Mon, 10 Jul 2023 05:39:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232836AbjGJJjL (ORCPT ); Mon, 10 Jul 2023 05:39:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC299183; Mon, 10 Jul 2023 02:36:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981815; x=1720517815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1i34KSawlUL8WNjNkmTiVglWiYjIqUpNKEWr7RWMan4=; b=dkU568SU+UcSyHrU6giMnLlJ1v4LoewMAX6SrSQOP45Z3WqxQP/tHPZs v9W6ZuI6dkVpeP9T/2osLaawFKsVqAdlv6hG2Hsqa8DSt62A+5UB6L5Ee sUZjNOvp2DS2wh4tGl8HZdQdiz7Rc2D4UIaQyV7Mfd2TcN9ZXZX3xAHt3 26IaZbkz3v9Hb/JaFFtChMyDTf/GLG8Gk4taMsi0Ll5BuY2WxKgQ/qjFm KA7MZxIOoJx+k9Hsp/rmlFBP8h7VIYleoO63BPYUtQisjzwuQlaN1ayRG i/hI0Tu9OHijMj3AGEoGqNLi4s4go//SUH10a0G2XdRer8ZKKVVefOBxX w==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="234573296" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:36:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:36 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:34 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v4 03/11] RISC-V: drop a needless check in print_isa_ext() Date: Mon, 10 Jul 2023 10:35:38 +0100 Message-ID: <20230710-map-unlocking-9f674ee171bb@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1275; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=1i34KSawlUL8WNjNkmTiVglWiYjIqUpNKEWr7RWMan4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL1xTEVf/3XjKu/FK/trOlIJHnLEzzrSGtosIRW32sVOo THPpKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEQKHBj++wUedIrm8Vv68c578dmTuH bbNJuHllrJPva9c+2/8f2HyxgZzp2WkLmxOl33VdKJsomyh4p4C2M/Lreb6H7JbJfBO6WTnAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771027243625122495 X-GMAIL-MSGID: 1771027243625122495 isa_ext_arr cannot be empty, as some of the extensions within it are always built into the kernel. When this code was first added, back in commit a9b202606c69 ("RISC-V: Improve /proc/cpuinfo output for ISA extensions"), the array was empty and needed a dummy item & thus there could be no extensions present. When the first multi-letter ones did get added, it was Sscofpmf - which didn't have a Kconfig symbol to disable it. Remove this check, as it has been redundant since Sscofpmf was added. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Reword commit message to explain why this can be dropped --- arch/riscv/kernel/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index f808b67f5a27..e721f15fdf17 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -237,10 +237,6 @@ static void print_isa_ext(struct seq_file *f) arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - /* No extension support available */ - if (arr_sz <= 0) - return; - for (i = 0; i <= arr_sz; i++) { edata = &isa_ext_arr[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) From patchwork Mon Jul 10 09:35:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904981vqx; Mon, 10 Jul 2023 02:52:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlG9lL6K6MfUtjbk6ZwShBftIxblFKuaMif7GDKmrrwoqabBDo4Lh4Z3K4idAA3OTI/7AoP+ X-Received: by 2002:a37:9343:0:b0:767:ba4:ba96 with SMTP id v64-20020a379343000000b007670ba4ba96mr10287576qkd.55.1688982723419; Mon, 10 Jul 2023 02:52:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982723; cv=none; d=google.com; s=arc-20160816; b=agQJTwi6rVDRaL0UdlAAJTS3ksF9L3qfnntaUUZEp9GE1304VIrmQAJVfF0BAfqjl2 taL8bP8aEQ7VLr9KgHt57KtsEy1VzWQN0wQtAb9KKWRTXg+++HCnpcmcKTOtbicpjkDg SjznMN/LmnA3XV2fiYG6Lttsfbh2RP2wzbSWFk94Y4LId5f6067SzQfg2YhozHZtCTxm vr5748hp6rtIqqqA+7Wnhq9UlfXpDtr4l9axapoxJYmCX0IhkgWFqgw5FntXCflnLh2z 5ct5gFmenA1r8BHb6AqNiffE8CST6FxC8cwy79SY8E4eMdVouwjcgFWf8S7zhQT3xoDn G/YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AzJ8prs2VMctMk6H8W9us1aijZD6DE52Pn0Fb2GHjo8=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=dRT+kE27tqU59steTvnTr1rnbWVhLnae71qmWPaSv5Eba3ZTqfzCDr9CDdR8u+mirY RVzvGRzrQ+T0IYeJ2mtYr5994pUbtU76dt9lk9/SxKoFuk+pqjIrw3b883O6laIB/VQp zWo9nlVUaBQSMcXyWbI+4bxTW0UJUgryyLUhNDbLnJ5ljfYy7a8KkLgHtQqQg09RvBwD 8W/G/vvLFu5CwrUaQ6S/3+xDg/aacSe4jLQkXbL6AL9HC1flFmuP8RUzFo5uNtn+xvWt IqVll8l9Y5rLlikhb1ktlv+K7D8AFK8R0Z3ah9iHSX6Ijj00NqsbG4zyH1Nz1HT2G2eu 9LVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nWjc+CLT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gf8-20020a17090ac7c800b0023a177c4951si7121162pjb.39.2023.07.10.02.51.50; Mon, 10 Jul 2023 02:52:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nWjc+CLT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231437AbjGJJkq (ORCPT + 99 others); Mon, 10 Jul 2023 05:40:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232462AbjGJJj3 (ORCPT ); Mon, 10 Jul 2023 05:39:29 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD64D271E; Mon, 10 Jul 2023 02:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981825; x=1720517825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bOnzuYCARzPhwIulmb5IXa1ikc7VrTQNP62An2jC5Lg=; b=nWjc+CLT5fx2JiYvJBwJp9UdQo/XduSeN7BbY7fIVXyp3BfZvc9xIq3x TcFhUJRKm9K2d19X6Q9P9zinQ83QFSbNFx82l7G0LTj4x3i9ajv8B/fmN LjYYH8Cdxl6paY2Rte1H6zGP3dadGwv1zaZ4jKGkdRZkjuQ/ekdyq6ThR KklAarQ4El5HhYO7tTNGB9x7UzKxJVzq1CtxomMPxz3iN2lEbyAMXu4So QzLED45zUxr8AZliR7eZm6WgmfJmHTQZoHQMHMbrmk0AAM3xoFWxs7TMX 9+B3TLuhi9jdoOSKmUlEj0DaSSWr8K4JP6OUaVWx3WnmATq3QDJ4vcIiG g==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="223902860" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:37:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:39 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:36 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v4 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Date: Mon, 10 Jul 2023 10:35:39 +0100 Message-ID: <20230710-maternity-duct-f93b20b52db3@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8778; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=bOnzuYCARzPhwIulmb5IXa1ikc7VrTQNP62An2jC5Lg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL1xr2y5/uferppedvs++gF08epO85c9aifFoLtgws0Lg u0hARykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYSUMzwm33nrx1TFiTEJXDYCpv/WN yY037+1g5v4+gMH7XSfRyXVBkZLpYcaC9NF7zeKm+mtEfA5N4dl89LJx17Gnzg6AP2DY/fMgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771026747859284289 X-GMAIL-MSGID: 1771026747859284289 To facilitate using one struct to define extensions, rather than having several, shunt isa_ext_arr to cpufeature.c, where it will be used for probing extension presence also. As that scope of the array as widened, prefix it with riscv & drop the type from the variable name. Since the new array is const, print_isa() needs a wee bit of cleanup to avoid complaints about losing the const qualifier. Reviewed-by: Andrew Jones Reviewed-by: Evan Green Signed-off-by: Conor Dooley --- Changes in v2: - Drop the empty element from the end of the array, it was adding a bug anyway as I was not decrementing the result of ARRAY_SIZE() by one. Likely I meant to drop it originally and forgot, as dropping the decrement was intentional. --- arch/riscv/include/asm/hwcap.h | 3 ++ arch/riscv/kernel/cpu.c | 75 +--------------------------------- arch/riscv/kernel/cpufeature.c | 67 ++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 73 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..7a57e6109aef 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,9 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; +extern const struct riscv_isa_ext_data riscv_isa_ext[]; +extern const size_t riscv_isa_ext_count; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index e721f15fdf17..bf93293d51f3 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,81 +164,10 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted after - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be listed - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be listed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed, they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described above. - */ -static struct riscv_isa_ext_data isa_ext_arr[] = { - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), - __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), - __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; - int i = 0, arr_sz; - - arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - - for (i = 0; i <= arr_sz; i++) { - edata = &isa_ext_arr[i]; + for (int i = 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) continue; seq_printf(f, "_%s", edata->uprop); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..fb476153fffc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,6 +99,73 @@ static bool riscv_isa_extension_check(int id) return true; } +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + * + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. + */ +const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), +}; + +const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); + void __init riscv_fill_hwcap(void) { struct device_node *node; From patchwork Mon Jul 10 09:35:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4908895vqx; Mon, 10 Jul 2023 03:01:06 -0700 (PDT) X-Google-Smtp-Source: APBJJlHgNMWGyvD4of0w33/dDuy7UyHR2/wZUi7QAIcd2j7nbt6FpkyVHf5FUNM2vk3U/iyuTjrE X-Received: by 2002:a05:6a20:7349:b0:117:eaef:4d with SMTP id v9-20020a056a20734900b00117eaef004dmr11647209pzc.36.1688983265692; Mon, 10 Jul 2023 03:01:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688983265; cv=none; d=google.com; s=arc-20160816; b=RVQbS3uzixlmYekISxt5xHQLFzyiWMr/W2Rh63Qlc0Pa97q08gxFYkCo9bmzl28qgJ BKP4P/5eGYty03qHBptcqYPyWtSB/IupygIbZOysjAc5PXk3dF2iNzPl96DOlEbjhcrl 9eP9JHbY5LEZr6vuDYzYVSKLZRDGkfC3WmDJzfxgwKk9Aff4MBiZwccahnR96LMHHy/a WkuSclB1jmrxVnIiYC/aq8B/Y593MB3rkAcN4JPyJ0Vpvv8cgpllyp4BUHTliSoFy2xn 0H3ep7mmPJH2b7scKMB1bE5jFg6MAmP29ZjNTY04xN3R9XtIeSYl9ebC9oDLtobqv5+o Kbkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y1s6QdaU8KsCyhnQtHVwoefCpPTi40J55GNx4a9o2qc=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=SexH9xZlBCu1QPivPdU/QNAECxQVugnYBnL8Z0tQ+AyNTk7RYoATrfI86te4jxX3wT Ux2ymNADOvDfHtSrdiTmdapH7MBV6v20dv1eJR4rpQxAjY+KkbdEe6GDe8M7FK/N8mAz WSXhcImm8jyxghp6kVq46v/R3Sv5gNhxApfAOdmSQQ3UmMYjwHLzkBtclSacnd+BL8KJ n1ByeDEow0fY/lR2TGak1OSwYEMnC8xmPawfSPtGDVD/YUT98rFcHng5XseX+qCcmVlk z6fUecObb+pB7x93Jvki5oK2WKsRjmv83ekYCcoH2gCWb9Cvc5Ya7ru1e+kILpQkmF3S BItw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=gMjrZErU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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While at it, drop the statement-of-the-obvious comments from the struct, rename uprop to something more suitable for its new use & constify the members. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Delete the now unused definition --- arch/riscv/include/asm/hwcap.h | 7 ++----- arch/riscv/kernel/cpu.c | 5 +++-- arch/riscv/kernel/cpufeature.c | 26 +++++++------------------- 3 files changed, 12 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7a57e6109aef..2460ac2fc7ed 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -55,7 +55,6 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA @@ -70,10 +69,8 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; + const unsigned int id; + const char *name; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index bf93293d51f3..aa17eeb0ec9a 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -168,9 +168,10 @@ static void print_isa_ext(struct seq_file *f) { for (int i = 0; i < riscv_isa_ext_count; i++) { const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + if (!__riscv_isa_extension_available(NULL, edata->id)) continue; - seq_printf(f, "_%s", edata->uprop); + + seq_printf(f, "_%s", edata->name); } } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fb476153fffc..6d8cd45af723 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id) return true; } -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } +#define __RISCV_ISA_EXT_DATA(_name, _id) { \ + .name = #_name, \ + .id = _id, \ +} /* * The canonical order of ISA extension names in the ISA string is defined in @@ -366,20 +365,9 @@ void __init riscv_fill_hwcap(void) set_bit(nr, isainfo->isa); } } else { - /* sorted alphabetically */ - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); } #undef SET_ISA_EXT_MAP } From patchwork Mon Jul 10 09:35:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4907023vqx; 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Reviewed-by: Andrew Jones Reviewed-by: Evan Green Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2460ac2fc7ed..a20e4ade1b53 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a') From patchwork Mon Jul 10 09:35:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117789 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4910655vqx; Mon, 10 Jul 2023 03:03:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGWlGS88VZ3kANwmiZaV9wCkCKdQMeRDAtU4MKu1PbOLpv+7D2//As82jLlmWbrBsMt05O7 X-Received: by 2002:a50:ec99:0:b0:51e:527b:4170 with SMTP id e25-20020a50ec99000000b0051e527b4170mr5912833edr.24.1688983414781; Mon, 10 Jul 2023 03:03:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688983414; cv=none; d=google.com; s=arc-20160816; b=klO5a/GB1HK5jyIVQM0UQlghQ/X7b5nF4tmyPJKVkntjNJekvp4fXDO4g9KaY5SLNK +AMo/Gv1764CWJIhEIY+C7aEZ6elj1oXsvyCimnrMqwHp8BKpna5KgX7sdTZoY62F8+S CCJA4FJHV5ZCExA+ZE05plH05fFDN1ickoJ1LzO6CoX88xDZCahMexLJQTH7wlYHMXZE Cn301hto0c70ChJEqWG4w0ZpKvasGMcGPR9Zbc7yLFG+lCY+iHrLGsmU+3o+3Mej/4MG t9zbzV0ayrlDZChZodPXf6q/RxukuYYLrTmOkGpsxp6pFKBo6tjuLP/hgtdV2mddESfP 9iTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kB4O3dYMOlL9Rpgov+KxBEV/XRl8KDGaBQ7YWPcjsms=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=XDT/hg118gnHk/KV2fKLH7c7jq9qQl03ptz6+GA9aAedoKPt05bRQ0YcF9nkaATrDH MLZxY66SgrIDD3NUlB7OxQo2cmCS07oQOLgaXO9qWS9TTyYvxs7YM3UdzRmrXTcMTP5Y rr3A81bnIWA6rUYbXXKlWNedFWlvKZQ4sndsS4kBUxiPY85pjaiqvQT99uKVz2y04ZQy E6INb8JNIGqwC86cXpUQiNM/kKR3xttR/h2hpfwE/pO8qVWH1rs8fLgbhQmJc5AYQciU 61Amj68IJS/0g8woCX6UvbVm2lpPspDZLDrutbCOdp6l7vtO7cIOPuJ+ia153nlm+bVw L3Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=bWiV7VN7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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As a result, what gets spat out in /proc/cpuinfo will become borked, as single letter extensions will be printed as part of the base extensions and while printing from riscv_isa_arr. Take the opportunity to unify the printing of the isa string, using the new member of riscv_isa_ext_data in the process. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop the multi_letter member, in exchange for calling strnlen() in two places. --- arch/riscv/kernel/cpu.c | 37 ++++++++++------------------------ arch/riscv/kernel/cpufeature.c | 13 ++++++++++++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index aa17eeb0ec9a..4f1f12f34b63 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,41 +164,26 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -static void print_isa_ext(struct seq_file *f) -{ - for (int i = 0; i < riscv_isa_ext_count; i++) { - const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->id)) - continue; - - seq_printf(f, "_%s", edata->name); - } -} - -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - static void print_isa(struct seq_file *f) { - int i; - seq_puts(f, "isa\t\t: "); + if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); else seq_write(f, "rv64", 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + continue; + + /* Only multi-letter extensions are split by underscores */ + if (strnlen(riscv_isa_ext[i].name, 2) != 1) + seq_puts(f, "_"); + + seq_printf(f, "%s", riscv_isa_ext[i].name); } - print_isa_ext(f); + seq_puts(f, "\n"); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6d8cd45af723..bf7e8e8852f0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -144,6 +144,19 @@ static bool riscv_isa_extension_check(int id) * New entries to this struct should follow the ordering rules described above. */ const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), + __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), + __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), + __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), + __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b), + __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k), + __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j), + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), From patchwork Mon Jul 10 09:35:43 2023 Content-Type: text/plain; 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Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop unused variables --- arch/riscv/kernel/cpufeature.c | 345 +++++++++++++++++---------------- 1 file changed, 177 insertions(+), 168 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bf7e8e8852f0..41aedeaecb61 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -178,29 +178,172 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); -void __init riscv_fill_hwcap(void) +static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo, + unsigned long *isa2hwcap, const char *isa) +{ + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ + isa += 4; + + while (*isa) { + const char *ext = isa++; + const char *ext_end = isa; + bool ext_long = false, ext_err = false; + + switch (*ext) { + case 's': + /* + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] != '_' && ext[1] == 'u') { + ++isa; + ext_err = true; + break; + } + fallthrough; + case 'S': + case 'x': + case 'X': + case 'z': + case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ + ext_long = true; + for (; *isa && *isa != '_'; ++isa) + if (unlikely(!isalnum(*isa))) + ext_err = true; + + ext_end = isa; + if (unlikely(ext_err)) + break; + + if (!isdigit(ext_end[-1])) + break; + + while (isdigit(*--ext_end)) + ; + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { + ++ext_end; + break; + } + + while (isdigit(*--ext_end)) + ; + + ++ext_end; + break; + default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ + if (unlikely(!isalpha(*ext))) { + ext_err = true; + break; + } + + if (!isdigit(*isa)) + break; + + while (isdigit(*++isa)) + ; + + if (tolower(*isa) != 'p') + break; + + if (!isdigit(*++isa)) { + --isa; + break; + } + + while (isdigit(*++isa)) + ; + + break; + } + + /* + * The parser expects that at the start of an iteration isa points to the + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". + */ + if (*isa == '_') + ++isa; + +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext == sizeof(name) - 1) && \ + !strncasecmp(ext, name, sizeof(name) - 1) && \ + riscv_isa_extension_check(bit)) \ + set_bit(bit, isainfo->isa); \ + } while (false) \ + + if (unlikely(ext_err)) + continue; + if (!ext_long) { + int nr = tolower(*ext) - 'a'; + + if (riscv_isa_extension_check(nr)) { + *this_hwcap |= isa2hwcap[nr]; + set_bit(nr, isainfo->isa); + } + } else { + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); + } +#undef SET_ISA_EXT_MAP + } +} + +static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) { struct device_node *node; const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; - unsigned long isa2hwcap[26] = {0}; + int rc; struct acpi_table_header *rhct; acpi_status status; unsigned int cpu; - isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; - isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - - elf_hwcap = 0; - - bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - if (!acpi_disabled) { status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); if (ACPI_FAILURE(status)) @@ -232,158 +375,7 @@ void __init riscv_fill_hwcap(void) } } - /* - * For all possible cpus, we have already validated in - * the boot process that they at least contain "rv" and - * whichever of "32"/"64" this kernel supports, and so this - * section can be skipped. - */ - isa += 4; - - while (*isa) { - const char *ext = isa++; - const char *ext_end = isa; - bool ext_long = false, ext_err = false; - - switch (*ext) { - case 's': - /* - * Workaround for invalid single-letter 's' & 'u'(QEMU). - * No need to set the bit in riscv_isa as 's' & 'u' are - * not valid ISA extensions. It works until multi-letter - * extension starting with "Su" appears. - */ - if (ext[-1] != '_' && ext[1] == 'u') { - ++isa; - ext_err = true; - break; - } - fallthrough; - case 'S': - case 'x': - case 'X': - case 'z': - case 'Z': - /* - * Before attempting to parse the extension itself, we find its end. - * As multi-letter extensions must be split from other multi-letter - * extensions with an "_", the end of a multi-letter extension will - * either be the null character or the "_" at the start of the next - * multi-letter extension. - * - * Next, as the extensions version is currently ignored, we - * eliminate that portion. This is done by parsing backwards from - * the end of the extension, removing any numbers. This may be a - * major or minor number however, so the process is repeated if a - * minor number was found. - * - * ext_end is intended to represent the first character *after* the - * name portion of an extension, but will be decremented to the last - * character itself while eliminating the extensions version number. - * A simple re-increment solves this problem. - */ - ext_long = true; - for (; *isa && *isa != '_'; ++isa) - if (unlikely(!isalnum(*isa))) - ext_err = true; - - ext_end = isa; - if (unlikely(ext_err)) - break; - - if (!isdigit(ext_end[-1])) - break; - - while (isdigit(*--ext_end)) - ; - - if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { - ++ext_end; - break; - } - - while (isdigit(*--ext_end)) - ; - - ++ext_end; - break; - default: - /* - * Things are a little easier for single-letter extensions, as they - * are parsed forwards. - * - * After checking that our starting position is valid, we need to - * ensure that, when isa was incremented at the start of the loop, - * that it arrived at the start of the next extension. - * - * If we are already on a non-digit, there is nothing to do. Either - * we have a multi-letter extension's _, or the start of an - * extension. - * - * Otherwise we have found the current extension's major version - * number. Parse past it, and a subsequent p/minor version number - * if present. The `p` extension must not appear immediately after - * a number, so there is no fear of missing it. - * - */ - if (unlikely(!isalpha(*ext))) { - ext_err = true; - break; - } - - if (!isdigit(*isa)) - break; - - while (isdigit(*++isa)) - ; - - if (tolower(*isa) != 'p') - break; - - if (!isdigit(*++isa)) { - --isa; - break; - } - - while (isdigit(*++isa)) - ; - - break; - } - - /* - * The parser expects that at the start of an iteration isa points to the - * first character of the next extension. As we stop parsing an extension - * on meeting a non-alphanumeric character, an extra increment is needed - * where the succeeding extension is a multi-letter prefixed with an "_". - */ - if (*isa == '_') - ++isa; - -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext == sizeof(name) - 1) && \ - !strncasecmp(ext, name, sizeof(name) - 1) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - - if (unlikely(ext_err)) - continue; - if (!ext_long) { - int nr = tolower(*ext) - 'a'; - - if (riscv_isa_extension_check(nr)) { - this_hwcap |= isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); - } -#undef SET_ISA_EXT_MAP - } + riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa); /* * Linux requires the following extensions, so we may as well @@ -420,6 +412,23 @@ void __init riscv_fill_hwcap(void) if (!acpi_disabled && rhct) acpi_put_table((struct acpi_table_header *)rhct); +} + +void __init riscv_fill_hwcap(void) +{ + char print_str[NUM_ALPHA_EXTS + 1]; + int i, j; + unsigned long isa2hwcap[26] = {0}; + + isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; + isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; + isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; + isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; + isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; + isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; + + riscv_fill_hwcap_from_isa_string(isa2hwcap); /* We don't support systems with F but without D, so mask those out * here. */ From patchwork Mon Jul 10 09:35:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904868vqx; Mon, 10 Jul 2023 02:51:42 -0700 (PDT) X-Google-Smtp-Source: APBJJlHtna9aRsXA9KOdk2wySLMOx2ruaQcb6Mk/D8W9QB0IEqW8gY44+HUZFjyiPAizzXo9T/yO X-Received: by 2002:a05:6808:b32:b0:3a1:d3f0:32ed with SMTP id t18-20020a0568080b3200b003a1d3f032edmr9272654oij.23.1688982702020; Mon, 10 Jul 2023 02:51:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982701; cv=none; d=google.com; s=arc-20160816; b=LZaj1KJA9g4zVOWfr5+8F1ZLZTQ02mmPSccovrvl/eO1PbAtGPrhmTXtNctWlWHiHB vVAlzZTE7lThp4p596luC4r+4I0jl6qEqNaAxWwIlQMyPTIorIFQQ5IjCLvc1lAAzWYs Xp5VGNa67cAZiusPRE3X2RLslImgiEsCUCccrfqtIG3TBByGO9srj972XGqIV7IHQ6D7 bp8tP1U0vgno9IWtEdCLPXmX48cPb63YaIMhMryI8rHPxTKnQupBNWlpn9u6P3gs13ya XWmEzIhvjPyOY8xLYP36O/xJ4o3hGC8mXvYlol/gngKsNobfi1mVIGgrZBq+zdkCVCVg JhEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TZHDoR/0ErFAtLFovXfKUb8RfvGGS5i9GSxPD1E2B7c=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=ZsiUf2Fgso9RQX37gdpeuIHHtJeuY2VCZJBaBZcvPJhH2WWYApFDubdNt3rswwqUiR SSBIE4ihV/vt7E7QUJQ2eZphHItJjHOIcxteKyn539DjZb4CE4WFP5qXmgzBcmDQikzN gvFIci9ridVeW6WFQZ7EzVYE/QQZ7Oi8Lx5Zz+B3ij/NYNr6wQ6O2GuJLLI/r0ra/lMD 6/Z08I1Fm2Qiz7igJt5K/slOcF5lQd89Y+M4kPkptxepczZkqKZEmYbj3MVlt67HHg7v 3RdQx+mPMM4iNJzrCLRom6G+YK53FAA8cGEF8JiJ/Ln1exhvrJ24c2fxmw8ed8nrt7Ps sFBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=1bNYkbD9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 12-20020a63194c000000b0055bc2612ed4si8748883pgz.39.2023.07.10.02.51.29; Mon, 10 Jul 2023 02:51:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=1bNYkbD9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbjGJJkT (ORCPT + 99 others); Mon, 10 Jul 2023 05:40:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbjGJJjZ (ORCPT ); Mon, 10 Jul 2023 05:39:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4532B2716; Mon, 10 Jul 2023 02:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981824; x=1720517824; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GCIGwsCwU5RS5bMsoRtWcou0pn3VgTFaZMXbVrYz4DA=; b=1bNYkbD97eDME8/YnuqxKSALyRNcC66gyCB4ttI2upgsaGDI3qsb1Iov 3WGqZ5hSMeQrT5n1/0GOivaNjVvt/jS9A21IY9k3+S6f78iFNax/WyLCQ gPUv9/7ComN9d+j2cdQBfZzBz2dr676X4VXV/DZG+uKWr81YDn5DA89Zt R64pAKolhl8h4T43B+OgXCWNk/aaTqzXUWfMkT5FbjVyp0k5zIvy/DoqV VDVNM3LBFScC4tvqrePn8VvLQMMZK0fjpj4E1DD7Ib/VDeBgRfxyTLD77 xPFxRaEXVEs5Sd5g2w2DQfn+jF8GO1ZrakAuXVq+D69ivKd2em8yV+lTM g==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="222870090" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:36:56 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:54 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:51 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v4 09/11] RISC-V: enable extension detection from new properties Date: Mon, 10 Jul 2023 10:35:44 +0100 Message-ID: <20230710-five-unwieldy-aba2d53a6480@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4499; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GCIGwsCwU5RS5bMsoRtWcou0pn3VgTFaZMXbVrYz4DA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL9z4JnFjhoJ6/LLTJyw/zPK5eva5jfETTaUCw2PRgdvi CkJudZSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAi0wMYGbammOba/33U+GvlotCDm9 8WmN/tcj0cwp46xakiIsDOvpXhn9I7Y3HL9I2VrW0Wiy0/rMyp2bt14uxnLhcamplPCE5jZAYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771026725676040206 X-GMAIL-MSGID: 1771026725676040206 Add support for parsing the new riscv,isa-extensions property in riscv_fill_hwcap(), by means of a new "property" member of the riscv_isa_ext_data struct. For now, this shadows the name of the extension for all users, however this may not be the case for all extensions, based on how the dt-binding is written. For the sake of backwards compatibility, fall back to the old scheme if the new properties are not detected. For now, just inform, rather than warn, when that happens. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Pick a more suitable function name than fill_hwcap_new() - Actually use the property member to read from the DT --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 76 ++++++++++++++++++++++++++++++++-- 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a20e4ade1b53..e3cda14a486b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,7 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { const unsigned int id; const char *name; + const char *property; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 41aedeaecb61..2c4503fa984f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_DATA(_name, _id) { \ .name = #_name, \ + .property = #_name, \ .id = _id, \ } @@ -414,11 +415,67 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) acpi_put_table((struct acpi_table_header *)rhct); } +static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) { + unsigned long this_hwcap = 0; + struct device_node *cpu_node; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + if (!of_property_present(cpu_node, "riscv,isa-extensions")) + continue; + + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + riscv_isa_ext[i].property) < 0) + continue; + + if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) + continue; + + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) == 1) + this_hwcap |= isa2hwcap[riscv_isa_ext[i].id]; + + set_bit(riscv_isa_ext[i].id, this_isa); + } + + of_node_put(cpu_node); + + /* + * All "okay" harts should have same isa. Set HWCAP based on + * common capabilities of every "okay" hart, in case they don't. + */ + if (elf_hwcap) + elf_hwcap &= this_hwcap; + else + elf_hwcap = this_hwcap; + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + else + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + return -ENOENT; + + return 0; +} + void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; unsigned long isa2hwcap[26] = {0}; + int i, j; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -428,10 +485,21 @@ void __init riscv_fill_hwcap(void) isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - riscv_fill_hwcap_from_isa_string(isa2hwcap); + if (!acpi_disabled) { + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } else { + int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); - /* We don't support systems with F but without D, so mask those out - * here. */ + if (ret) { + pr_info("Falling back to deprecated \"riscv,isa\"\n"); + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } + } + + /* + * We don't support systems with F but without D, so mask those out + * here. + */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { pr_info("This kernel does not support systems with F but not D\n"); elf_hwcap &= ~COMPAT_HWCAP_ISA_F; From patchwork Mon Jul 10 09:35:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117772 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904480vqx; Mon, 10 Jul 2023 02:50:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlGcMDN3BQTRWMlObay033CRjI/GlX35kvCfa7EBmMejzTbeMnBTRbtH0pHMXHByvzbPPtzK X-Received: by 2002:a05:6358:702:b0:134:e41a:9227 with SMTP id e2-20020a056358070200b00134e41a9227mr9757025rwj.5.1688982638861; Mon, 10 Jul 2023 02:50:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982638; cv=none; d=google.com; s=arc-20160816; b=jSE8ZaT87/igw5qlGnkGjnjP+EbaEca+QfPCL0CpOAM6y38yswNzACBywz2uUVdN9b mAUKQwbsA0AP3xnC+yfbeFGeJTg+HcMXlCHYBAlsZCG49b95CFbTjpnJT/G+Pu4JeWnR M0+QWNp2J6uNYGAyPZpT0s9KdpUeR48YNbO8x0gjbaiv3N5Q/TxE949la1WOLlrPvAEY RWVGrkroS714t2hlUtfAV0Aqb58Tb3siV5sVQzuwlAWuZyqVdWvFFWf3bAbqoBW4X4EP ryLSQNiIGf6YgO1VIxKu/LXqk1cuLFS5ehEeT2iMa+ajb2Olu8vZXLyxh7PnHsoMM1EN JTPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7mRMEMCtqtAeUOhcKcRhtWdUcJLYolxHwb3sQJY5g/Y=; fh=+t+G/OXZaGbelVlx/PAQKy/ssq96RZ9Njlv0n65gx60=; b=wuYkmZz02x9bbxBAwMhnGI87yqshGSd2hWY6Qo5x8SCrqVCSTnkRaegHct3SlnqdgI lm6tBRplW1XM4dvSHvin/JG0lQdoS8OJW82fHDOQ6IPkTIZxxLQKbU/VW4S0op2w3jZ1 DLHbAM3/87TbVzzSxD4OsnAXsZXXfPjibDSmrI606rhj7phb64Yl2DyGACFz2g2HS9z6 BCq8Lmp1d5m21PtDfXKH6lRbX8pFOtJ0nwlz4vBR+agwQ49J066zyUuhm82hL3LYUua2 k70EA6/oL15LEqenF/0O2aCrqonyoE6qex3CqZu5Mt9H3NqoU0n9MzhCM/7pWT2DryRE fCGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=r3P7ayFC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o19-20020a056a0015d300b0068259969675si3656520pfu.297.2023.07.10.02.50.26; Mon, 10 Jul 2023 02:50:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=r3P7ayFC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233081AbjGJJlM (ORCPT + 99 others); Mon, 10 Jul 2023 05:41:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231359AbjGJJjy (ORCPT ); Mon, 10 Jul 2023 05:39:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB079272B; Mon, 10 Jul 2023 02:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981850; x=1720517850; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6+4fXO0Mgsbn0oR0/2jnJO0XttLzGYmDlCcJv+2evZU=; b=r3P7ayFCc7VSFCyHJhjOMbwIuX+iUDOXzPiX+hIzlsQ8Rpxqs4/+QV6i y8/tUGmKeYsviZwN+phnnef6J54EVLctrxJYHS+0bc5FTLtbY+KghrL2X o8rRsoustQlBK40WNrA8JwlX+cSUhcdFf0HNemwdYTJOQQg6FA/qnRh/z p32mscb/l4oSkO8FXm+7dxEsiBTLlz2pBcvHOqhZ8b48vcDB515cuntsT haMV/W0HwxaAvdTSnqtGhxPD3ZSDDDqVjyBvOWwg420WPPR3xry0xWogx v5dS53FHWeOayb45k8Y6swet68V9trmBVB0ZkeD7IRLmslgLM3VrwVufE g==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="160600140" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:36:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:54 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , Subject: [PATCH v4 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Date: Mon, 10 Jul 2023 10:35:45 +0100 Message-ID: <20230710-multitude-badly-1c149269766f@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1977; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=6+4fXO0Mgsbn0oR0/2jnJO0XttLzGYmDlCcJv+2evZU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL9wUYbX9WD13y3kjpZ6UTf6/rI5c3FPLXPWjZuX3dq9n +26zdpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiZ14z/OHlcuBud/F7OUvh6rOLUz d3drdqfX0TZPrtdeJyvT1H1pcw/GbLiw/LZXpsc0+rUSCqLyLlkafxM5vbJo3P9/tfuvCigBMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771026659612541911 X-GMAIL-MSGID: 1771026659612541911 To fully deprecate the kernel's use of "riscv,isa", of_early_processor_hartid() needs to first try using the new properties, before falling back to "riscv,isa". Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v3: - Add some printouts to explain what went wrong while parsing harts, so that if none are found there's at least a hint before we hit a BUG() --- arch/riscv/kernel/cpu.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 4f1f12f34b63..28d5af21f544 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -61,8 +61,35 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) { + pr_warn("CPU with hartid=%lu does not support rv32i", *hart); + return -ENODEV; + } + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) { + pr_warn("CPU with hartid=%lu does not support rv64i", *hart); + return -ENODEV; + } + + if (!of_property_present(node, "riscv,isa-extensions")) + return -ENODEV; + + if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { + pr_warn("CPU with hartid=%lu does not support ima", *hart); + return -ENODEV; + } + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; } From patchwork Mon Jul 10 09:35:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 117770 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4904280vqx; Mon, 10 Jul 2023 02:50:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlGF/2SrzNUv+Xa+8gRvR2C2evmTGXJ7pFcziIrajWO9+dNnV6Mqh3Tb7es12exO0HTmyGe9 X-Received: by 2002:a17:903:1112:b0:1b3:f8db:6f0e with SMTP id n18-20020a170903111200b001b3f8db6f0emr12210970plh.43.1688982604264; Mon, 10 Jul 2023 02:50:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688982604; cv=none; d=google.com; s=arc-20160816; b=lubxtsq0AEoh0ec4unjuntVJ1IkPoXNCbWUYTqO0WQ/6PtvePAAEeV3UpeGORwab4E Z3wLHz533fNoD/Za6+OhNPMykIS8xWMaG2n7ScogDWl8/rSoNG8YqixBhaRmrh0q1RqM iHDeslLCo1EhA+BKah+sThGjH6/AocNfYgyMfIUIN4XsnVYeqtLpO62FNBGBfFrFqYrp lQDQQNsVOXWlc9u1urPt0x2QmWjllyYREBhQ6CwVzoMKlC4GAPVFR2g9Xe4G4MnpxOpp /Z8TeMtfNezHCwo6hJKhpPGFfJRji6gEUiRws2eXSigUdV8tQNJaVakc533fHBGGfC/P cNLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eM9xfCX4d175BMxF6apilrOPY4joD90mRggr6e2PRFs=; fh=NmedlpijBMacxlBO1NzbUohgLks7RaHl1/2Vvbaff2U=; b=YGb6bS9Me7t70aYRWGkctIYqmKuCqUGeOkpwSGqaier2pey2Tn3jtZmnsmC76aQHVi c8xWJov+oLmWMLPQ/iu2RqsffN6m1E3Uma8/SfBxw1yMVWpAdA2lHolTFF0Emuv3rfXl zV8xoK2Bei91bKy4ro4P0M7CXJdX8FSk6PUdTsqn5trqrfHV6ZNh3n9SvUMBI/trwHsQ zyr20uGt7Jqso8b8pJZBvDIoEPt552MoNo9dACtsyWVKw5IYrP3+zl4sS5fPGKx4vXMi 8fovov5c6rvP9hOLj+FS/wiUUjwhDoaA37gNYppH0ukj5kF2AUyR7BUfRobDPW7TxOg3 WerA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LBLIx8Hx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f18-20020a170902f39200b001b89bd6fd59si8136929ple.215.2023.07.10.02.49.51; Mon, 10 Jul 2023 02:50:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LBLIx8Hx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232428AbjGJJk1 (ORCPT + 99 others); Mon, 10 Jul 2023 05:40:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231509AbjGJJjZ (ORCPT ); Mon, 10 Jul 2023 05:39:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52E351BF5; Mon, 10 Jul 2023 02:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688981825; x=1720517825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O+veMtx+JvcXWx4LygV6hHgSQoTVwUJDCTyGDuzrzBQ=; b=LBLIx8HxraHsJs4qdxZJMnyOOT6d/dfzVDMICBJ2XZr2tFxTWZl2W6Zn adHNgUCPcRIxHTs+qCsCjM7rwyhS2rAgZm3tnKpR7FsXLILQJtaD5hHFK p143z1stnt/t7udHMVooZxL/8z67TwOwBH+ilu0q0crxPKVlwmdidj0ao doC4iIr1CjV2T0nUsHphTxnhLYgyy7hDPzqTlBC+awcWveXN23JYL+IsQ vyK0Opnas7kxK1fi3IlaA9rmdfcoYT2kx+RkJAtE0QA7EoU/tSbWxY66Q 4CeV/U88RPAu+TenEvs1KhJenz1doK0JOgMhX1jO+lyYsG6ofRE6NAPDB g==; X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="222870094" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jul 2023 02:37:02 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 10 Jul 2023 02:36:59 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 10 Jul 2023 02:36:57 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , "Jonathan Corbet" , Andrew Jones , "Heiko Stuebner" , Evan Green , Sunil V L , , , , , Palmer Dabbelt Subject: [PATCH v4 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Date: Mon, 10 Jul 2023 10:35:46 +0100 Message-ID: <20230710-reappear-unable-5f954043552a@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230710-equipment-stained-dd042d66ba5d@wendy> References: <20230710-equipment-stained-dd042d66ba5d@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5841; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=O+veMtx+JvcXWx4LygV6hHgSQoTVwUJDCTyGDuzrzBQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmrL9y8PuV2Ys/Sp1ln9klIzzh54OEpA/nQ7D/2q3hOTZnj v/iCeUcpC4MYB4OsmCJL4u2+Fqn1f1x2OPe8hZnDygQyhIGLUwAmUveUkWG1b8Le2iv7uZJ3qqh0xX 8XT9h6piP31ok5+4NWz7AKs05k+Gcnk/aSeyM3J7um42zJ1AaWd3XnZI/ef7F4Xpv/5e1vrvACAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771026623245975067 X-GMAIL-MSGID: 1771026623245975067 As it says on the tin, provide Kconfig option to control parsing the "riscv,isa" devicetree property. If either option is used, the kernel will fall back to parsing "riscv,isa", where "riscv,isa-base" and "riscv,isa-extensions" are not present. The Kconfig options are set up so that the default kernel configuration will enable the fallback path, without needing the commandline option. Suggested-by: Andrew Jones Suggested-by: Palmer Dabbelt Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v4: - add __init to fixup k210 build issue - use Drew's revised wording Changes in v3: - Invert the Kconfig entry. It's now default y & not hidden by NONPORTABLE, but its entablement will now activate the fallback - Add a commandline option to enable the fallback on kernels that do not enable it in Kconfig, as Drew suggested - Default the global var to the Kconfig option & override it with the commandline one, rather than have checks for IS_ENABLED() and for the commandline option in riscv_fill_hwcap() & riscv_early_of_processor_hartid() --- .../admin-guide/kernel-parameters.txt | 7 +++++++ arch/riscv/Kconfig | 18 ++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 8 +++++++- arch/riscv/kernel/cpufeature.c | 14 +++++++++++++- 5 files changed, 46 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index a1457995fd41..bdc3fa712e92 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5468,6 +5468,13 @@ [KNL] Disable ring 3 MONITOR/MWAIT feature on supported CPUs. + riscv_isa_fallback [RISCV] + When CONFIG_RISCV_ISA_FALLBACK is not enabled, permit + falling back to detecting extension support by parsing + "riscv,isa" property on devicetree systems when the + replacement properties are not found. See the Kconfig + entry for RISCV_ISA_FALLBACK. + ro [KNL] Mount root device read-only on boot rodata= [KNL] diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4c07b9189c86..f52dd125ac5e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -848,6 +848,24 @@ config XIP_PHYS_ADDR be linked for and stored to. This address is dependent on your own flash usage. +config RISCV_ISA_FALLBACK + bool "Permit falling back to parsing riscv,isa for extension support by default" + default y + help + Parsing the "riscv,isa" devicetree property has been deprecated and + replaced by a list of explicitly defined strings. For compatibility + with existing platforms, the kernel will fall back to parsing the + "riscv,isa" property if the replacements are not found. + + Selecting N here will result in a kernel that does not use the + fallback, unless the commandline "riscv_isa_fallback" parameter is + present. + + Please see the dt-binding, located at + Documentation/devicetree/bindings/riscv/extensions.yaml for details + on the replacement properties, "riscv,isa-base" and + "riscv,isa-extensions". + endmenu # "Boot options" config BUILTIN_DTB diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e3cda14a486b..b7b58258f6c7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ struct riscv_isa_ext_data { extern const struct riscv_isa_ext_data riscv_isa_ext[]; extern const size_t riscv_isa_ext_count; +extern bool riscv_isa_fallback; unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 28d5af21f544..208f1a700121 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -41,7 +41,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) return 0; } -int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) +int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; @@ -87,6 +87,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return 0; old_interface: + if (!riscv_isa_fallback) { + pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", + *hart); + return -ENODEV; + } + if (of_property_read_string(node, "riscv,isa", &isa)) { pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", *hart); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2c4503fa984f..5945dfc5f806 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -471,6 +471,18 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) return 0; } +#ifdef CONFIG_RISCV_ISA_FALLBACK +bool __initdata riscv_isa_fallback = true; +#else +bool __initdata riscv_isa_fallback; +static int __init riscv_isa_fallback_setup(char *__unused) +{ + riscv_isa_fallback = true; + return 1; +} +early_param("riscv_isa_fallback", riscv_isa_fallback_setup); +#endif + void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; @@ -490,7 +502,7 @@ void __init riscv_fill_hwcap(void) } else { int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); - if (ret) { + if (ret && riscv_isa_fallback) { pr_info("Falling back to deprecated \"riscv,isa\"\n"); riscv_fill_hwcap_from_isa_string(isa2hwcap); }