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[2620:137:e000::1:20]) by mx.google.com with ESMTP id kk6-20020a170903070600b001b88dbc8b09si6800008plb.454.2023.07.09.04.57.04; Sun, 09 Jul 2023 04:57:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=DNZvJCm2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232154AbjGIL4G (ORCPT + 99 others); Sun, 9 Jul 2023 07:56:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230449AbjGIL4F (ORCPT ); Sun, 9 Jul 2023 07:56:05 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8484DB for ; Sun, 9 Jul 2023 04:56:03 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3fbf1b82de7so26700535e9.1 for ; Sun, 09 Jul 2023 04:56:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688903762; x=1691495762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RKSqDzGLT/QQIgfCm4UW9VXcHqwxbjeXId/4Akra8p4=; b=DNZvJCm2pUjlaiEXbxzy2ep3OGh3LZAiNUOKTvLXGJF91I6Qfa3OBdEAAk3KZ7gpEl +SRJqgBbPGXVHkPI+a2Y4jMPxj8nepQ4OYQq85lBFJvJG8oLkUYtqRpyMORxU5X3Co0U 4gbMGzPDMrMTIvIiQr41P3Wefx+e+9HaNxaVdyXtdHDAVsGXxcqI0GsqiZZSBpHaaQvO QbqV/Wk1DaKTFs59VpnYMrjFQy60JcGOSUsGX0hqAeM0GhGZp+BLIQSbNzk+C8wTMsw7 pyMrWYBcMGZ0FAwLzl4fGtC5myIfZzWdfyy0H4vK7bS7r1NY5bpmhqEJDrN8azpoF9et qI3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688903762; x=1691495762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RKSqDzGLT/QQIgfCm4UW9VXcHqwxbjeXId/4Akra8p4=; b=Y0SG94oYEOCjrT+lVBqF1snJcQdT/zxFgL9cpeRzhfac4c8jkrx67nyLMAZ/0UIVuB t98A8WCrD/WAq+/6B04jgSBdXgFBiSmLZUCCNlbfYkAIkuZqFV3zs0uI5OpIz1k2Q4Re 49IlNVu81vOEU5ZEDpIzp7r3xcAf5KCXYTLT8uoI9IksNiVk1m+1CrpX+3uT1oin5Lar yv1J7cCcf9q31RKZ5ziEfZ4w+GzfSUYS+3MLGGLbgvjBj4olFwvwsa93L6Z2H3/cl9oT hNPXIoRKd1DYkr/1K7PZrsFS6LWMwHCvep/uZ3aFUsC85LCeBm5S1Egg/PHSrBt4tDMd 5I0Q== X-Gm-Message-State: ABy/qLYucA6ra/hNOkQSCVAfzgantAR5PstOp+wCkZ6VNHks5HVJYzTO RQLqH62X1Ow99dJiqsXPOHCR5w== X-Received: by 2002:a05:600c:4446:b0:3fa:ef97:1fa5 with SMTP id v6-20020a05600c444600b003faef971fa5mr11903256wmn.6.1688903762307; Sun, 09 Jul 2023 04:56:02 -0700 (PDT) Received: from vermeer.tail79c99.ts.net ([2a01:cb1d:81a9:dd00:b570:b34c:ffd4:c805]) by smtp.gmail.com with ESMTPSA id 2-20020a05600c02c200b003fc007d8a92sm6194101wmn.45.2023.07.09.04.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Jul 2023 04:56:02 -0700 (PDT) From: Samuel Ortiz To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: "Hongren (Zenithal) Zheng" , linux@rivosinc.com, Conor Dooley , Andrew Jones , Heiko Stuebner , Anup Patel , linux-kernel@vger.kernel.org, Guo Ren , Atish Patra , Samuel Ortiz , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Evan Green , devicetree@vger.kernel.org, Jiatai He Subject: [PATCH v3 1/4] RISC-V: Add Bitmanip/Scalar Crypto parsing from DT Date: Sun, 9 Jul 2023 13:55:43 +0200 Message-ID: <20230709115549.2666557-2-sameo@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230709115549.2666557-1-sameo@rivosinc.com> References: <20230709115549.2666557-1-sameo@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770944029283778827?= X-GMAIL-MSGID: =?utf-8?q?1770944029283778827?= From: "Hongren (Zenithal) Zheng" Parse Zb/Zk related string from DT and output them to cpuinfo. It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions. Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk_zks" will generate the following cpuinfo output: "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt". Tested-by: Jiatai He Reviewed-by: Evan Green Reviewed-by: Conor Dooley Signed-off-by: Samuel Ortiz Signed-off-by: Hongren (Zenithal) Zheng Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 11 +++++++++++ arch/riscv/kernel/cpu.c | 11 +++++++++++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..b80ca6e77088 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,17 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZBC 43 +#define RISCV_ISA_EXT_ZBKB 44 +#define RISCV_ISA_EXT_ZBKC 45 +#define RISCV_ISA_EXT_ZBKX 46 +#define RISCV_ISA_EXT_ZKND 47 +#define RISCV_ISA_EXT_ZKNE 48 +#define RISCV_ISA_EXT_ZKNH 49 +#define RISCV_ISA_EXT_ZKR 50 +#define RISCV_ISA_EXT_ZKSED 51 +#define RISCV_ISA_EXT_ZKSH 52 +#define RISCV_ISA_EXT_ZKT 53 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..10524322a4c0 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..9a872a2007a5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX); SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); } #undef SET_ISA_EXT_MAP } From patchwork Sun Jul 9 11:55:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Ortiz X-Patchwork-Id: 117497 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4401172vqx; Sun, 9 Jul 2023 04:57:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlFdCmkyjGuBPuTC54Acg1FcO+3mzeXH7MtVWdBEonVB9xWLUSwsvxkGjPtsEJyg0bf6Hj9s X-Received: by 2002:a05:6a20:7295:b0:12f:405d:c4d0 with SMTP id o21-20020a056a20729500b0012f405dc4d0mr11653179pzk.54.1688903839886; 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This documents all the dt-bindings for the scalar cryptography extensions, including the Zk, Zkn and Zks shorthands. Signed-off-by: Samuel Ortiz Reviewed-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..361756978da1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -190,6 +190,24 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zbkb + description: | + The standard Zbkb cryptography extension for bit-manipulation + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zbkc + description: | + The standard Zbkc cryptography extension for carry-less multiply + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zbkx + description: | + The standard Zbkx cryptography extension for crossbar permutation + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + - const: zicbom description: The standard Zicbom extension for base cache management operations as @@ -240,6 +258,70 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zk + description: | + The standard Zk cryptography extension is a shorthand for the + union of the Zkn, Zkr and Zkt cryptography extensions, as ratified + at commit 73de909 ("Zvk: Update AES instruction specs") of + riscv-crypto. + + - const: zkn + description: | + The standard Zkn cryptography extension covers the NIST algorithm + suite that other cryptography extensions support. It is the union of + the Zbkb, Zbkc, Zbkx, Zknd, Zkne and Zknh extensions, as ratified at + commit 73de909 ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zknd + description: | + The standard Zknd cryptography extension for AES block cipher + decryption acceleration instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkne + description: | + The standard Zkne cryptography extension for AES block cipher + encryption acceleration instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zknh + description: | + The standard Zknh cryptography extension for SHA2 hash algorithm + functions acceleration instructions as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkr + description: | + The standard Zkr cryptography extension for the entropy source CSR + definitions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zks + description: | + The standard Zks cryptography extension covers the ShangMi algorithm + suite that other cryptography extensions support. It is the union of + the Zbkb, Zbkc, Zbkx, Zksed and Zksh extensions, as ratified at + commit 73de909 ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zksed + description: | + The standard Zksed cryptography extension for SM4 block cipher + acceleration instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zksh + description: | + The standard Zksh cryptography extension for SM3 hash algorithm + funstions acceleration instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkt + description: | + The standard Zkt cryptography extension for data independent + execution latency attestation, for a safe subset of instructions, + as ratified at commit 73de909 ("Zvk: Update AES instruction specs") + of riscv-crypto. + - const: ztso description: The standard Ztso extension for total store ordering, as ratified From patchwork Sun Jul 9 11:55:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Ortiz X-Patchwork-Id: 117499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4419712vqx; Sun, 9 Jul 2023 05:35:42 -0700 (PDT) X-Google-Smtp-Source: APBJJlHPH1vFJbNWAWkaiXglrsEUqqMdwaFi6M+3nkL0qQcNp0p6HjoZTfVg2yCycwWh4TK2VybG X-Received: by 2002:a17:902:b942:b0:1b6:797d:33fb with SMTP id h2-20020a170902b94200b001b6797d33fbmr9560619pls.64.1688906142131; Sun, 09 Jul 2023 05:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688906142; cv=none; d=google.com; s=arc-20160816; b=G3wexJvTYhWZXQmgtWvktjZuhpdo+lQVkRzdniBdBQGcpN6GaivVMLyM3iW9EyaJ60 2dB+twKi57iBHhIHkoWm7H9H08IrDkrMDkgnvygfj4efir8zS2TAAL3NiybbK6GXbhua W+RZdimPQPm7D3d635dEaS4ncFf482EnpAvsuu6bXqIL1oOEU4m7bRSZxdSEWoPpFYX/ O3pRG6dQyHByn/NSMkw2/TCLcnTt6DihoOqgo14gDFp7FtmxfiWboLrDc5JImBjJnUB0 mkV56qNpqj9GQmgVdamuvRmqEQSyR6+8kcSJ5qRVeVYUbikmg82nWO0qbgmG39jpk1AI WgOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=c4NrSWdfkQConL7+u+EjtZsZVwzL9nmXD1mG1ZJ9TfY=; fh=EntbM+yooSeyhuzXwbMJsrrH62QgZYLWr0Z9OnyuF7U=; b=Hjp3M5NtfN82rScP8XbVtOg+yrrZjC15bXV1DV2nA//fw67t2h7mybtbG8nTXZN3M9 q/5NLLN2ooaHorzxBtCzD3xZwl7CeHJx+o622JG26wVbX7SySBxknBXunKpROp5snG/a yEYMg10Lb5urOvT/cAGOXZ8BFAfG8eQlx9tZzCyeEukjkoZ6scmr1YMtpy+49iFDQaXf AvrwyEgf15/ofp6jbO3vKLrTsjDs9aWpPMVeZQGrZ2ga+oq77nsjA7fAdts4le2DvnYk Txe38GshHmgcRzigZ5jtSnHfJf/0xWD36+kicD8ol3ollbz3MbjCBsBOdL3Uspvhegt3 Iq3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=gGErSPtg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Add all scalar crypto extensions bits, and define a macro for setting the hwprobe key/pair in a more readable way. Reviewed-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Ortiz --- Documentation/riscv/hwprobe.rst | 33 ++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 11 ++++++++ arch/riscv/kernel/sys_riscv.c | 36 ++++++++++++++++----------- 3 files changed, 66 insertions(+), 14 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 19165ebd82ba..3177550106e0 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -72,11 +72,44 @@ The following keys are defined: extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBC`: The Zbc extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB`: The Zbkb extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC`: The Zbkc extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX`: The Zbkx extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND`: The Zknd extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE`: The Zkne extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH`: The Zknh extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKR`: The Zkr extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED`: The Zksed extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH`: The Zksh extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT`: The Zkt extension is supported, as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 006bfb48343d..8357052061b3 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,17 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZBC (1 << 6) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 9) +#define RISCV_HWPROBE_EXT_ZKND (1 << 10) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 12) +#define RISCV_HWPROBE_EXT_ZKR (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) +#define RISCV_HWPROBE_EXT_ZKT (1 << 16) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 26ef5526bfb4..df15926196b6 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,28 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo = &hart_isa[cpu]; - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |= RISCV_HWPROBE_EXT_ZBA; - else - missing |= RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |= RISCV_HWPROBE_EXT_ZBB; - else - missing |= RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |= RISCV_HWPROBE_EXT_ZBS; - else - missing |= RISCV_HWPROBE_EXT_ZBS; +#define SET_HWPROBE_EXT_PAIR(ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, ext)) \ + pair->value |= RISCV_HWPROBE_EXT_## ext; \ + else \ + missing |= RISCV_HWPROBE_EXT_## ext; \ + } while (false) \ + + SET_HWPROBE_EXT_PAIR(ZBA); + SET_HWPROBE_EXT_PAIR(ZBB); + SET_HWPROBE_EXT_PAIR(ZBC); + SET_HWPROBE_EXT_PAIR(ZBS); + SET_HWPROBE_EXT_PAIR(ZBKB); + SET_HWPROBE_EXT_PAIR(ZBKC); + SET_HWPROBE_EXT_PAIR(ZBKX); + SET_HWPROBE_EXT_PAIR(ZKND); + SET_HWPROBE_EXT_PAIR(ZKNE); + SET_HWPROBE_EXT_PAIR(ZKNH); + SET_HWPROBE_EXT_PAIR(ZKR); + SET_HWPROBE_EXT_PAIR(ZKSED); + SET_HWPROBE_EXT_PAIR(ZKSH); + SET_HWPROBE_EXT_PAIR(ZKT); } /* Now turn off reporting features if any CPU is missing it. */ From patchwork Sun Jul 9 11:55:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Ortiz X-Patchwork-Id: 117498 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp4410133vqx; Sun, 9 Jul 2023 05:14:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlEFr2FUR7XFiMNyHIb23rYUEzbGM0Dxb9QCY2UnL/ctKmAHAedX1PKOznzdHnYUUG0xPUYr X-Received: by 2002:a05:6a20:4327:b0:131:439d:c3c1 with SMTP id h39-20020a056a20432700b00131439dc3c1mr3561607pzk.23.1688904879570; Sun, 09 Jul 2023 05:14:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688904879; cv=none; d=google.com; s=arc-20160816; b=Yt5ohgzgKyXghshuOK6QWWz0Necec+Tg//Jyq8T9sb0mtiS3FhVPzk77hbQzejQcEK 8DWtrTZAoo+v7HcDMToIG4fti0W7MX0onDB1bpEfM3svAdjcnbWL3/ediaJXMKFkc9PM ARkvOyVcQMLN4OJ1AvVjeLh5CLZpotV/lb/QmbA0IJCFW2Z7rbyu5pmcYczL8L2ZCBkE sF3dMJtT6cGXofVmU1qJ/6rxNdIx/Vd3ff+rJHyvwhQgruKb8uRljdj14+8JyWAh6VlS YIm0BnckJwKw2Z4ORiJJuTN5Z42jVeqw8VQIYK3ccdA8ui/rGavGEas3fDj4cF0EgW/o M+PQ== ARC-Message-Signature: i=1; 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We can implement arch_get_random_seed_longs() by doing multiple csrrw to that CSR and filling an unsigned long with valid entropy bits. Acked-by: Conor Dooley Signed-off-by: Samuel Ortiz --- arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 9 ++++ 2 files changed, 79 insertions(+) create mode 100644 arch/riscv/include/asm/archrandom.h diff --git a/arch/riscv/include/asm/archrandom.h b/arch/riscv/include/asm/archrandom.h new file mode 100644 index 000000000000..38f3cced0fd0 --- /dev/null +++ b/arch/riscv/include/asm/archrandom.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Kernel interface for the RISCV arch_random_* functions + * + * Copyright (c) 2023 by Rivos Inc. + * + */ + +#ifndef ASM_RISCV_ARCHRANDOM_H +#define ASM_RISCV_ARCHRANDOM_H + +#include + +#define SEED_RETRY_LOOPS 100 + +static inline bool __must_check csr_seed_long(unsigned long *v) +{ + unsigned int retry = SEED_RETRY_LOOPS, valid_seeds = 0; + const int needed_seeds = sizeof(long) / sizeof(u16); + u16 *entropy = (u16 *)v; + + do { + /* + * The SEED CSR (0x015) must be accessed with a read-write + * instruction. + */ + unsigned long csr_seed = csr_swap(CSR_SEED, 0); + + switch (csr_seed & SEED_OPST_MASK) { + case SEED_OPST_ES16: + entropy[valid_seeds++] = csr_seed & SEED_ENTROPY_MASK; + if (valid_seeds == needed_seeds) + return true; + break; + + case SEED_OPST_DEAD: + pr_err_once("archrandom: Unrecoverable error\n"); + return false; + + case SEED_OPST_BIST: + case SEED_OPST_WAIT: + default: + continue; + } + } while (--retry); + + return false; +} + +static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs) +{ + return 0; +} + +static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs) +{ + if (!max_longs) + return 0; + + /* + * If Zkr is supported and csr_seed_long succeeds, we return one long + * worth of entropy. + */ + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v)) + return 1; + + return 0; +} + +#endif /* ASM_RISCV_ARCHRANDOM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index b98b3b6c9da2..7d0ca9082c66 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -389,6 +389,15 @@ #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 +/* Scalar Crypto Extension - Entropy */ +#define CSR_SEED 0x015 +#define SEED_OPST_MASK _AC(0xC0000000, UL) +#define SEED_OPST_BIST _AC(0x00000000, UL) +#define SEED_OPST_WAIT _AC(0x40000000, UL) +#define SEED_OPST_ES16 _AC(0x80000000, UL) +#define SEED_OPST_DEAD _AC(0xC0000000, UL) +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL) + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE