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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770683817550298471?= X-GMAIL-MSGID: =?utf-8?q?1770683817550298471?= Convert the Amlogic Clock Controller bindings to dt-schema. Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong --- .../bindings/clock/amlogic,gxbb-clkc.txt | 53 ---------------------- .../bindings/clock/amlogic,gxbb-clkc.yaml | 37 +++++++++++++++ 2 files changed, 37 insertions(+), 53 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt deleted file mode 100644 index 7ccecd5c02c1..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Amlogic GXBB Clock and Reset Unit - -The Amlogic GXBB clock controller generates and supplies clock to various -controllers within the SoC. - -Required Properties: - -- compatible: should be: - "amlogic,gxbb-clkc" for GXBB SoC, - "amlogic,gxl-clkc" for GXL and GXM SoC, - "amlogic,axg-clkc" for AXG SoC. - "amlogic,g12a-clkc" for G12A SoC. - "amlogic,g12b-clkc" for G12B SoC. - "amlogic,sm1-clkc" for SM1 SoC. -- clocks : list of clock phandle, one for each entry clock-names. -- clock-names : should contain the following: - * "xtal": the platform xtal - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or - "amlogic,meson-axg-hhi-sysctrl" -- reg: base address and size of the HHI system control register space. - -Example: Clock controller node: - -sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - #clock-cells = <1>; - compatible = "amlogic,gxbb-clkc"; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml new file mode 100644 index 000000000000..63246f1cb539 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Clock Controller + +maintainers: + - Neil Armstrong + +properties: + compatible: + enum: + - amlogic,gxbb-clkc + - amlogic,gxl-clkc + - amlogic,axg-clkc + - amlogic,g12a-clkc + - amlogic,g12b-clkc + - amlogic,sm1-clkc + + clocks: + maxItems: 1 + + clock-names: + const: xtal + + '#clock-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false From patchwork Thu Jul 6 14:52:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 116752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp2626018vqx; Thu, 6 Jul 2023 08:06:02 -0700 (PDT) X-Google-Smtp-Source: APBJJlHWF+3SapnvopjG4vOD/YmXqU1XrVeHEaioc9EhXQ8IjtlKco/l6Av9sgVZ5BEi2YN1rE/a X-Received: by 2002:a17:902:ab01:b0:1b6:6f12:502e with SMTP id ik1-20020a170902ab0100b001b66f12502emr1785499plb.49.1688655962470; Thu, 06 Jul 2023 08:06:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688655962; cv=none; d=google.com; s=arc-20160816; b=EtOBmGiqfImeJvhnwFeXSBho2RJ4qZSatop9jcBeEIMOtR0OrVDTDrgaBhrmcH/7w3 zK1lXy0IVADQGg49xs1xHH6F0tzCg5g0OnJd/ACm2OQjDTuwjupAEqw6UeS7azvV+WKj M1g1CH1N1/n+YEwifpmgrmgdipbi8kuHrGuWlYGPEUvsetB3rE+8N1qfX9arAIJzj4nB 8JyTluYslTVjpeg9nCwYi9T/nRLlr6FTOc3ZYs1bB2t+yxFAbDVFK31dvTEEnK2/GKCd fZI31vpHVRaArX1ds2TrJyK/kch2HvKMK0Vvhsz+kaoLOKFYuG1FZO1n22mdhhhg5Tq4 w6iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=pCHzxbE1tjKBR243NKKB0jh3lIoMBebnovktMIwTJXM=; fh=lcnQUUxO8No9ithnc56/Rk5B2NXyrzkM1I9+IOEi4Ng=; b=DU54EbCNe2pu2As4DsSo5CJhAHM/ivo96rUK5tsDMyNpSvZo2DVGtWv4A9UgH3BOKl IBHCEGceo8lQ5jxUT9bhfgo9reJkDu4IZFpgmjlsKIKTBckYkr/ZVIg6AbuRjqtlXODX EcfZFiOrvteo6cPZUZ98Tsl2zutB7ESBxwZYa8XPyVq5+Ouy+BIoCBnNPJohEU/zaLyN +pPXTsIZdIVCluIiObiqoZM2o/ToaCPbRjGgTL8T3bFzrUcXQnLORIMPM4KWqjwX6iLz Or10R9/qbM/sAhmyGOcfeBt7PsBE//BqN0+fwI7dUXFvbvGTK0ccZIV+fBWBN2s/FVsq ZHYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h9JMtcl6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770684114313414129?= X-GMAIL-MSGID: =?utf-8?q?1770684114313414129?= Convert the Amlogic Always-On Clock Controller bindings to dt-schema. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../bindings/clock/amlogic,gxbb-aoclkc.txt | 64 ---------------- .../bindings/clock/amlogic,gxbb-aoclkc.yaml | 85 ++++++++++++++++++++++ 2 files changed, 85 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt deleted file mode 100644 index c41f0be5d438..000000000000 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Amlogic GXBB AO Clock and Reset Unit - -The Amlogic GXBB AO clock controller generates and supplies clock to various -controllers within the Always-On part of the SoC. - -Required Properties: - -- compatible: value should be different for each SoC family as : - - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" - - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" - - GXM (S912) : "amlogic,meson-gxm-aoclkc" - - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" - - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" - followed by the common "amlogic,meson-gx-aoclkc" -- clocks: list of clock phandle, one for each entry clock-names. -- clock-names: should contain the following: - * "xtal" : the platform xtal - * "mpeg-clk" : the main clock controller mother clock (aka clk81) - * "ext-32k-0" : external 32kHz reference #0 if any (optional) - * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) - * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be -used in device tree sources. - -- #reset-cells: should be 1. - -Each reset is assigned an identifier and client nodes can use this identifier -to specify the reset which they consume. All available resets are defined as -preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be -used in device tree sources. - -Parent node should have the following properties : -- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" -- reg: base address and size of the AO system control register space. - -Example: AO Clock controller node: - -ao_sysctrl: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - -Example: UART controller node that consumes the clock and reset generated - by the clock controller: - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-uart"; - reg = <0x4c0 0x14>; - interrupts = <0 90 1>; - clocks = <&clkc_AO CLKID_AO_UART1>; - resets = <&clkc_AO RESET_AO_UART1>; - }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml new file mode 100644 index 000000000000..25daf313172a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Always-On Clock Controller + +maintainers: + - Neil Armstrong + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,meson-gxbb-aoclkc + - amlogic,meson-gxl-aoclkc + - amlogic,meson-gxm-aoclkc + - amlogic,meson-axg-aoclkc + - const: amlogic,meson-gx-aoclkc + - enum: + - amlogic,meson-axg-aoclkc + - amlogic,meson-g12a-aoclkc + + clocks: + minItems: 2 + maxItems: 5 + + clock-names: + minItems: 2 + items: + - const: xtal + - const: mpeg-clk + - const: ext-32k-0 + - const: ext-32k-1 + - const: ext-32k-2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-aoclkc + + then: + properties: + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + - if: + properties: + compatible: + enum: + - amlogic,meson-gxl-aoclkc + - amlogic,meson-gxm-aoclkc + - amlogic,meson-axg-aoclkc + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + +additionalProperties: false From patchwork Thu Jul 6 14:52:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 116756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp2631754vqx; Thu, 6 Jul 2023 08:12:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlGgWpcMIPGjnXjKD9PLiJnKGEvuV4senlzik9pGsgFMq4/LOQ96IUZmmv977kt8Q7M4ho1M X-Received: by 2002:a17:903:41c6:b0:1b2:1a79:147d with SMTP id u6-20020a17090341c600b001b21a79147dmr2721180ple.2.1688656365488; Thu, 06 Jul 2023 08:12:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688656365; cv=none; d=google.com; s=arc-20160816; b=enAY8RPomck9/xhZad+vdpl3MB3hWMEMahwZr04GFoj1sO1pMTJ9bOTaKpGlDdg4yU TsbJlJj7OcL2rqRePpisKwnICR4DrzA/zOLXkP3lNmcUd9gB9ZfBF9jqd09ROEzuQ+8v QcPlQxrG3gQ4eJbX698k3A6WNLgHOQPUHssg+y3drmrmP2Epc6r95v1xwQtS5oWpb+HQ IELJgbMe3w52NDPejXMpG+i4jxIqZIH3B7qfaZiOTZAij3BYb9YFpOZqevYmIQBK1uaf FLpZFXqa52WRU/OTjDzE+itCA2/gRr6jSOI64jh0U1MexkwkAdg9Z9BD8qJEaK7oWHik DyPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=yCxpHr7ST1gyjjiHsf0Ym9vUzb7jDX0bdoH7ToQxooQ=; fh=Bayft2VGy6LAwn8R1wYV3IuUNMZTYwXOUXr8UxFrUfs=; b=s/QTsEuiykgdv74J6v/1e9Z0Tu/Ag1PUwtEReE7DLvtEEW97mbguOP0bexT/AhEVcA 12dlEExAtYOxSWINw7xUHjFKSgGa8QsXybAZ1SSW+tkLnV14mbqZ9xueGS4w5qUeBo+E xSejGl1k0wjIerQ29rVdj8BS1g3U3//0MCAIipBxsTyXK2yLMg6v8Iv7ZB2fWxv/2ZED CuqX7y8Hfmxmap+TIDYLXNSoxYwQMwX5hO00bPnoFylGF4z8xc3mD+HWLnnNnhNrcxqM Jhc4yBPuikleVYKPbbX54asNxXGTkPzItgjDba8j2Xix+l637Os3Y1ka6QDYRPDW7ZDj PFng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ctHBu4D4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770684536946199588?= X-GMAIL-MSGID: =?utf-8?q?1770684536946199588?= Document the System Control registers regions found on all Amlogic SoC families and it's clock, power, pinctrl and phy subnodes. The regions has various independent registers tied to other hardware devices, thus the syscon compatible. Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong --- .../soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml | 160 +++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml new file mode 100644 index 000000000000..16977e4e4357 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson System Control registers + +maintainers: + - Neil Armstrong + +properties: + compatible: + items: + - enum: + - amlogic,meson-gx-hhi-sysctrl + - amlogic,meson-gx-ao-sysctrl + - amlogic,meson-axg-hhi-sysctrl + - amlogic,meson-axg-ao-sysctrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + type: object + + power-controller: + $ref: /schemas/power/amlogic,meson-ee-pwrc.yaml + + pinctrl: + type: object + + phy: + type: object + +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-hhi-sysctrl + - amlogic,meson-axg-hhi-sysctrl + then: + properties: + clock-controller: + $ref: /schemas/clock/amlogic,gxbb-clkc.yaml# + + required: + - power-controller + + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-ao-sysctrl + - amlogic,meson-axg-ao-sysctrl + then: + properties: + clock-controller: + $ref: /schemas/clock/amlogic,gxbb-aoclkc.yaml# + + power-controller: false + phy: false + + - if: + properties: + compatible: + enum: + - amlogic,meson-gx-hhi-sysctrl + then: + properties: + phy: false + + - if: + properties: + compatible: + enum: + - amlogic,meson-axg-hhi-sysctrl + then: + properties: + phy: + oneOf: + - $ref: /schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml + - $ref: /schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml + +required: + - compatible + - reg + - clock-controller + +additionalProperties: false + +examples: + - | + bus@c883c000 { + compatible = "simple-bus"; + reg = <0xc883c000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc883c000 0x2000>; + + sysctrl: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; + reg = <0 0x400>; + + clock-controller { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + power-controller { + compatible = "amlogic,meson-gxbb-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + + resets = <&reset_viu>, + <&reset_venc>, + <&reset_vcbus>, + <&reset_bt656>, + <&reset_dvin>, + <&reset_rdma>, + <&reset_venci>, + <&reset_vencp>, + <&reset_vdac>, + <&reset_vdi6>, + <&reset_vencl>, + <&reset_vid_lock>; + reset-names = "viu", "venc", "vcbus", "bt656", "dvin", + "rdma", "venci", "vencp", "vdac", "vdi6", + "vencl", "vid_lock"; + clocks = <&clk_vpu>, <&clk_vapb>; + clock-names = "vpu", "vapb"; + }; + }; + }; + + bus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + sysctrl_AO: system-controller@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; + reg = <0 0x100>; + + clock-controller { + compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&xtal>, <&clk81>; + clock-names = "xtal", "mpeg-clk"; + }; + }; + };