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Signed-off-by: Charlie Jenkins --- arch/riscv/Kbuild | 1 + arch/riscv/Kconfig | 1 + arch/riscv/Kconfig.vendor | 3 +++ arch/riscv/include/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 40 ++++++++++++++++++++++++++++++++--- arch/riscv/vendor_extensions/Makefile | 3 +++ 6 files changed, 46 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kbuild b/arch/riscv/Kbuild index afa83e307a2e..bea38010d9db 100644 --- a/arch/riscv/Kbuild +++ b/arch/riscv/Kbuild @@ -3,6 +3,7 @@ obj-y += kernel/ mm/ net/ obj-$(CONFIG_BUILTIN_DTB) += boot/dts/ obj-y += errata/ +obj-y += vendor_extensions/ obj-$(CONFIG_KVM) += kvm/ obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += purgatory/ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c1505c7729ec..19404ede0ee3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -276,6 +276,7 @@ config AS_HAS_OPTION_ARCH source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.errata" +source "arch/riscv/Kconfig.vendor" menu "Platform type" diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor new file mode 100644 index 000000000000..213ac3e6fed5 --- /dev/null +++ b/arch/riscv/Kconfig.vendor @@ -0,0 +1,3 @@ +menu "Vendor extensions selection" + +endmenu # "Vendor extensions selection" diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 78936f4ff513..fadb38b83243 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -9,5 +9,6 @@ #include #define RISCV_HWPROBE_MAX_KEY 5 +#define RISCV_HWPROBE_VENDOR_EXTENSION_SPACE (UL(1)<<63) #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 26ef5526bfb4..2351a5f7b8b1 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -188,9 +188,35 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) return perf; } +static int hwprobe_vendor(__u64 mvendorid, struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + switch (mvendorid) { + default: + return -1; + } + + return 0; +} + static void hwprobe_one_pair(struct riscv_hwprobe *pair, const struct cpumask *cpus) { + int err; + + if (((unsigned long) pair->key) >= RISCV_HWPROBE_VENDOR_EXTENSION_SPACE) { + struct riscv_hwprobe mvendorid = { + .key = RISCV_HWPROBE_KEY_MVENDORID, + .value = 0 + }; + + hwprobe_arch_id(&mvendorid, cpus); + if (mvendorid.value != -1ULL) + err = hwprobe_vendor(mvendorid.value, pair, cpus); + else + err = -1; + } + switch (pair->key) { case RISCV_HWPROBE_KEY_MVENDORID: case RISCV_HWPROBE_KEY_MARCHID: @@ -217,13 +243,21 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, /* * For forward compatibility, unknown keys don't fail the whole - * call, but get their element key set to -1 and value set to 0 - * indicating they're unrecognized. + * call, instead an error is raised to indicate the element key + * is unrecognized. */ default: + err = -1; + break; + } + + /* + * Setting the element key to -1 and value to 0 indicates that + * hwprobe was unable to find the requested key. + */ + if (err != 0) { pair->key = -1; pair->value = 0; - break; } } diff --git a/arch/riscv/vendor_extensions/Makefile b/arch/riscv/vendor_extensions/Makefile new file mode 100644 index 000000000000..e815895e9372 --- /dev/null +++ b/arch/riscv/vendor_extensions/Makefile @@ -0,0 +1,3 @@ +ifdef CONFIG_RELOCATABLE +KBUILD_CFLAGS += -fno-pie +endif From patchwork Thu Jul 6 03:30:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 116490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp2290880vqx; Wed, 5 Jul 2023 20:46:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlGlnMnqmP2OeDD7jFb/bnv6I2zrNfmvi5WnIfimKNK7Q1gmYB76Z5B16JHP+XrqjYi/WRh8 X-Received: by 2002:a17:902:ec88:b0:1b6:b805:5ae3 with SMTP id x8-20020a170902ec8800b001b6b8055ae3mr972834plg.3.1688615198625; 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It is determined to be available only if the kernel is compiled with vector support, and the user is using the c906. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.vendor | 11 +++++++++++ arch/riscv/include/asm/extensions.h | 16 ++++++++++++++++ arch/riscv/kernel/sys_riscv.c | 20 ++++++++++++++++++++ arch/riscv/vendor_extensions/Makefile | 2 ++ arch/riscv/vendor_extensions/thead/Makefile | 8 ++++++++ arch/riscv/vendor_extensions/thead/extensions.c | 24 ++++++++++++++++++++++++ 6 files changed, 81 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index 213ac3e6fed5..b8b9d15153eb 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -1,3 +1,14 @@ menu "Vendor extensions selection" +config VENDOR_EXTENSIONS_THEAD + bool "T-HEAD vendor extensions" + depends on RISCV_ALTERNATIVE + default n + help + All T-HEAD vendor extensions Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all T-HEAD vendor extensions. Please say "Y" + here if your platform uses T-HEAD vendor extensions. + + Otherwise, please say "N" here to avoid unnecessary overhead. + endmenu # "Vendor extensions selection" diff --git a/arch/riscv/include/asm/extensions.h b/arch/riscv/include/asm/extensions.h new file mode 100644 index 000000000000..27ce294a3d65 --- /dev/null +++ b/arch/riscv/include/asm/extensions.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 by Rivos Inc. + */ +#ifndef __ASM_EXTENSIONS_H +#define __ASM_EXTENSIONS_H + +#include +#include + +#define THEAD_ISA_EXT0 (RISCV_HWPROBE_VENDOR_EXTENSION_SPACE) +#define THEAD_ISA_EXT0_V0_7_1 (1 << 0) + +int hwprobe_thead(__u64 marchid, __u64 mimpid, struct riscv_hwprobe *pair, + const struct cpumask *cpus); +#endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 2351a5f7b8b1..58b12eaeaf46 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -192,6 +193,25 @@ static int hwprobe_vendor(__u64 mvendorid, struct riscv_hwprobe *pair, const struct cpumask *cpus) { switch (mvendorid) { +#ifdef CONFIG_VENDOR_EXTENSIONS_THEAD + case THEAD_VENDOR_ID: + struct riscv_hwprobe marchid = { + .key = RISCV_HWPROBE_KEY_MARCHID, + .value = 0 + }; + struct riscv_hwprobe mimpid = { + .key = RISCV_HWPROBE_KEY_MIMPID, + .value = 0 + }; + + hwprobe_arch_id(&marchid, cpus); + hwprobe_arch_id(&mimpid, cpus); + if (marchid.value != -1ULL && mimpid.value != -1ULL) + hwprobe_thead(marchid.value, mimpid.value, pair, cpus); + else + return -1; + break; +#endif default: return -1; } diff --git a/arch/riscv/vendor_extensions/Makefile b/arch/riscv/vendor_extensions/Makefile index e815895e9372..38c3e80469fd 100644 --- a/arch/riscv/vendor_extensions/Makefile +++ b/arch/riscv/vendor_extensions/Makefile @@ -1,3 +1,5 @@ ifdef CONFIG_RELOCATABLE KBUILD_CFLAGS += -fno-pie endif + +obj-$(CONFIG_VENDOR_EXTENSIONS_THEAD) += thead/ diff --git a/arch/riscv/vendor_extensions/thead/Makefile b/arch/riscv/vendor_extensions/thead/Makefile new file mode 100644 index 000000000000..7cf43c629b66 --- /dev/null +++ b/arch/riscv/vendor_extensions/thead/Makefile @@ -0,0 +1,8 @@ +ifdef CONFIG_FTRACE +CFLAGS_REMOVE_extensions.o = $(CC_FLAGS_FTRACE) +endif +ifdef CONFIG_KASAN +KASAN_SANITIZE_extensions.o := n +endif + +obj-y += extensions.o diff --git a/arch/riscv/vendor_extensions/thead/extensions.c b/arch/riscv/vendor_extensions/thead/extensions.c new file mode 100644 index 000000000000..a177501bc99c --- /dev/null +++ b/arch/riscv/vendor_extensions/thead/extensions.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 by Rivos Inc. + */ + +#include + +int hwprobe_thead(__u64 marchid, __u64 mimpid, struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + pair->value = 0; + switch (pair->key) { + case THEAD_ISA_EXT0: +#ifdef CONFIG_RISCV_ISA_V + if (marchid == 0 && mimpid == 0) + pair->value |= THEAD_ISA_EXT0_V0_7_1; +#endif + break; + default: + return -1; + } + + return 0; +} From patchwork Thu Jul 6 03:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 116494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp2292332vqx; Wed, 5 Jul 2023 20:51:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlEoZ8hMBx1sm+q88L/FoEPurF2jneNy7zZyBTmh4H3OB0RvnwXONZ0svvflctoOIuHX6FGh X-Received: by 2002:a05:6808:1b10:b0:3a1:c841:f026 with SMTP id bx16-20020a0568081b1000b003a1c841f026mr562268oib.27.1688615482193; Wed, 05 Jul 2023 20:51:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688615482; cv=none; d=google.com; s=arc-20160816; b=Pa3PB1pqXPnqxT5aQ0KA3NIvFC01aHnMyOo2KpFY8v3kXOHg4VjPNBDrM/2BIXrafg VNTbyyR7C72oiLUAwU0tvAzkEEN+sz7vL919cmc72D+g5Hp3Kv0Vhuxpl+rode3919pV 2LPyD43CmNQ3fz66ch2f01si/8QXGCO/ElX8HIi+evQj6Z7RTcPzu78olbWho/pC+LIQ 2bIBEvn60SzvcoTrxgIMcexxUdGComitreDj6p+dzfmuG+9Xajao/JaVWrH05hqPcUKu AsC+w1/CGOv5xoYQJs8OETNsOy7nT+WAdjc5HVDqm6//se+3OfDjJ1KJaVkaMay+z4OS zEog== ARC-Message-Signature: i=1; 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Signed-off-by: Charlie Jenkins --- Documentation/riscv/hwprobe.rst | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 19165ebd82ba..167fd3e25632 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -97,3 +97,20 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are not supported at all and will generate a misaligned address fault. + +RISC-V Hardware Probing Interface Vendor Extensions +--------------------------------------------------- + +All vendor extensions live at and beyond +:c:macro:`RISCV_HWPROBE_VENDOR_EXTENSION_SPACE`. Each vendor can specify vendor +extensions at any value above or equal to +:c:macro:`RISCV_HWPROBE_VENDOR_EXTENSION_SPACE` without worrying about +conflicting with values from other vendors. Only extensions from the vendor of +the cpus passed into riscv_hwprobe will be matched. + +T-HEAD +~~~~~~ + +* :c:macro:`THEAD_ISA_EXT0`: Contains all of the EXT0 extensions + + * :c:macro:`THEAD_ISA_EXT0_V0_7_1`: Vector extension V0.7.1 is supported