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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 1/9] riscv: remove unused functions in traps_misaligned.c Date: Tue, 4 Jul 2023 16:09:16 +0200 Message-Id: <20230704140924.315594-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770499555193061243?= X-GMAIL-MSGID: =?utf-8?q?1770499555193061243?= Replace macros by the only two function calls that are done from this file, store_u8() and load_u8(). Signed-off-by: Clément Léger --- arch/riscv/kernel/traps_misaligned.c | 46 +++++----------------------- 1 file changed, 7 insertions(+), 39 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 378f5b151443..e7bfb33089c1 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -151,51 +151,19 @@ #define PRECISION_S 0 #define PRECISION_D 1 -#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ -static inline type load_##type(const type *addr) \ -{ \ - type val; \ - asm (#insn " %0, %1" \ - : "=&r" (val) : "m" (*addr)); \ - return val; \ -} +static inline u8 load_u8(const u8 *addr) +{ + u8 val; -#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ -static inline void store_##type(type *addr, type val) \ -{ \ - asm volatile (#insn " %0, %1\n" \ - : : "r" (val), "m" (*addr)); \ -} + asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr)); -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw) -#if defined(CONFIG_64BIT) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) -#else -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) - -static inline u64 load_u64(const u64 *addr) -{ - return load_u32((u32 *)addr) - + ((u64)load_u32((u32 *)addr + 1) << 32); + return val; } -static inline void store_u64(u64 *addr, u64 val) +static inline void store_u8(u8 *addr, u8 val) { - store_u32((u32 *)addr, val); - store_u32((u32 *)addr + 1, val >> 32); + asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); } -#endif static inline ulong get_insn(ulong mepc) { From patchwork Tue Jul 4 14:09:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115819 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1258543vqx; Tue, 4 Jul 2023 07:22:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlGg945gQWpjROMh9HUxszJfa+iWceYKlegCPKhYRq/LSDkqWnrWcCvqA0BF4kC8uFHwSdDx X-Received: by 2002:a92:daca:0:b0:345:ac89:6c42 with SMTP id o10-20020a92daca000000b00345ac896c42mr12603205ilq.2.1688480566940; Tue, 04 Jul 2023 07:22:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480566; cv=none; d=google.com; s=arc-20160816; b=opL6kVS1P4nIOqyiAIY6eMt7/cAIYL0pZKzJnzdNFUMOwg3TFr/y1yyN2rkugtU6t7 wqP8172rpgoTdjGwGWPZ0INB4KY87LDnmfUdXXGcAnxgr/tf5+Qv7zB3j/SqrpIC8TcR fmZ1sbNDnDkQGwoOT7Q1YU9PItD5tzreiVX6QrgB85VHQuTRuGnA438Y+3Mp58QD1be6 Rgzt22OLQXS67eUNfG/LEcVI8T/WA1PI4EprksNwNi4VwoHh1HP7i0uzshhfNbJt6WNu DnJ3mRLRT+eX/w12Ko2Cifbrl/cYEZ1BUL2N5WcBLTIkbWvGOhmQwIMFWDgvGo9P/enZ 9pOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hP9LYFgOAjVow+h4CXKR68tZiOwggsdorDJAE/dJK2A=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=axPHBKt1AUGds6SyhQet1yCQc9zhtvEYKcJevDLNjzZQvBtglErCq+AEUKvye6PQ2P lMRl9Hwco7EspbG0Q793PSen1jKBq867GwCyBf4nRQry3nEqD36poq54QkhHWFmBWQJi n5jvZD8tCuyhMhM4z2NENGuDD/4yiuAK1TpmkLZMYvNVLxEGX7VC/s0oegzOBsVtMUO6 INrxbPBpa+f5+ENuDTpeZzXqpaOlrl08YRCulkpjn99NfcMe49L8lQKSJo3mu3UQdGV5 9skscM5MCypjSy0Q3bfZ0U4k2yCyAOal856BCBVvIYTSwpFRLKuiMghNmHIAUSJsXy33 xhdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=pYjDpVSe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning Date: Tue, 4 Jul 2023 16:09:17 +0200 Message-Id: <20230704140924.315594-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770500199179572659?= X-GMAIL-MSGID: =?utf-8?q?1770500199179572659?= Declare handle_misaligned_store/load() functions in entry-common.h and include that file in traps_misaligned.c file to avoid warnings. Signed-off-by: Clément Léger --- arch/riscv/include/asm/entry-common.h | 3 +++ arch/riscv/kernel/traps.c | 2 -- arch/riscv/kernel/traps_misaligned.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index 6e4dee49d84b..58e9e2976e1b 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -8,4 +8,7 @@ void handle_page_fault(struct pt_regs *regs); void handle_break(struct pt_regs *regs); +int handle_misaligned_load(struct pt_regs *regs); +int handle_misaligned_store(struct pt_regs *regs); + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c258b78c925..7fcaf2fd27a1 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -155,8 +155,6 @@ DO_ERROR_INFO(do_trap_load_misaligned, DO_ERROR_INFO(do_trap_store_misaligned, SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned"); #else -int handle_misaligned_load(struct pt_regs *regs); -int handle_misaligned_store(struct pt_regs *regs); asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index e7bfb33089c1..0cccac4822a8 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -12,6 +12,7 @@ #include #include #include +#include #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f From patchwork Tue Jul 4 14:09:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115815 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1255560vqx; Tue, 4 Jul 2023 07:17:49 -0700 (PDT) X-Google-Smtp-Source: APBJJlGnQi0kUVrXVGTyqtkZa8lta4zQlmeU585RhJIvMmVZzmOOTrnPd1PO/d3pgcC6TuOgbTkA X-Received: by 2002:a17:90a:f6c8:b0:25b:c8b7:9e5b with SMTP id er8-20020a17090af6c800b0025bc8b79e5bmr14332245pjb.31.1688480269611; Tue, 04 Jul 2023 07:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480269; cv=none; d=google.com; s=arc-20160816; b=xLRCq6Vv2IzeAILYpdd5ZTV2r53eevO3xrcZ6E29xHR9Nrj8756hBEROpP59QpFkBS HHWDIsbd29GPZA3SqH2JLyQ3A9nLMiQLnG+D+0axUS1Qt2Kd8ALBjYonKAhb+Jj3q42i EsnenUN3rynN2pMskwcXDoWqU5x2na7eHSKRLwB+oLJWKKpu6y6RsEu8o5hs6WFT2Sfb Jk39Moh9zV3CrLHjX4zN5MILkvV9zfc99C5XnJCHq4NkB8p8dKUtqs/r/5jwvXIOrnW0 /mly3lm2Or1fkQ5dKAIXdzBBEkDs28AdthkG84M70Y/SSc+QcXW5cWLm1ZS+8kA9XZxc Cd5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tjQ2GzX04kf0h9GMnyJoWtp+hj7mtUQd1bUdoSwTimI=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=w6p6o5+ZWGVGytg5WkMuA/sOlTOQM0uP2UL5crm8XK95X059D2DQE1zMIUjv8VkETM y9DmYuxU370O4LajH56dnjAlaqaf+whW507CFtdTSSXQ9DTsFTYSXdzRJfBSNJSKgNxe 3eHuaB2phaf9un1IVqUyNkODrWcYewoE5+a1f3edNAuIuY2vQxQGA6BDMiCsgFvcfMdT D3uDa9VERat7rzkl+1/6sdYd62NeeO/SAlC7/phs0KFJ41a9U6MZdliXBdc4HDtn8gUb XvlUcOgFKq5pTBF5AKxOexfeZ5zM/DsRhBqsMEYuAbW8paHGkUX9B3ATq13VqYmVFXzj s8lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=2D84fmx8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 3/9] riscv: add support for misaligned handling in S-mode Date: Tue, 4 Jul 2023 16:09:18 +0200 Message-Id: <20230704140924.315594-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770499886893460987?= X-GMAIL-MSGID: =?utf-8?q?1770499886893460987?= Misalignment handling is only supported for M-mode and uses direct accesses to user memory. in S-mode, this requires to use the get_user()/put_user() accessors. Implement load_u8(), store_u8() and get_insn() using these accessors. Signed-off-by: Clément Léger --- arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/traps.c | 7 -- arch/riscv/kernel/traps_misaligned.c | 118 ++++++++++++++++++++++++--- 3 files changed, 106 insertions(+), 21 deletions(-) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 153864e4f399..79b8dafc699d 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -55,10 +55,10 @@ obj-y += riscv_ksyms.o obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o +obj-y += traps_misaligned.o obj-y += probes/ obj-$(CONFIG_MMU) += vdso.o vdso/ -obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 7fcaf2fd27a1..b2fb2266fb83 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -149,12 +149,6 @@ DO_ERROR_INFO(do_trap_insn_illegal, SIGILL, ILL_ILLOPC, "illegal instruction"); DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); -#ifndef CONFIG_RISCV_M_MODE -DO_ERROR_INFO(do_trap_load_misaligned, - SIGBUS, BUS_ADRALN, "Oops - load address misaligned"); -DO_ERROR_INFO(do_trap_store_misaligned, - SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned"); -#else asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { @@ -197,7 +191,6 @@ asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs irqentry_nmi_exit(regs, state); } } -#endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_s, diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 0cccac4822a8..9daed7d756ae 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -152,21 +152,25 @@ #define PRECISION_S 0 #define PRECISION_D 1 -static inline u8 load_u8(const u8 *addr) +#ifdef CONFIG_RISCV_M_MODE +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { u8 val; asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr)); + *r_val = val; - return val; + return 0; } -static inline void store_u8(u8 *addr, u8 val) +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) { asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); + + return 0; } -static inline ulong get_insn(ulong mepc) +static inline int get_insn(struct pt_regs *regs, ulong mepc, ulong *r_insn) { register ulong __mepc asm ("a2") = mepc; ulong val, rvc_mask = 3, tmp; @@ -195,9 +199,87 @@ static inline ulong get_insn(ulong mepc) : [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (XLEN_MINUS_16)); - return val; + *r_insn = val; + + return 0; +} +#else +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) +{ + if (user_mode(regs)) { + return __get_user(*r_val, addr); + } else { + *r_val = *addr; + return 0; + } } +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) +{ + if (user_mode(regs)) { + return __put_user(val, addr); + } else { + *addr = val; + return 0; + } +} + +#define __read_insn(regs, insn, insn_addr) \ +({ \ + int __ret; \ + \ + if (user_mode(regs)) { \ + __ret = __get_user(insn, insn_addr); \ + } else { \ + insn = *insn_addr; \ + __ret = 0; \ + } \ + \ + __ret; \ +}) + +static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn) +{ + ulong insn = 0; + + if (epc & 0x2) { + ulong tmp = 0; + u16 __user *insn_addr = (u16 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + /* __get_user() uses regular "lw" which sign extend the loaded + * value make sure to clear higher order bits in case we "or" it + * below with the upper 16 bits half. + */ + insn &= GENMASK(15, 0); + if ((insn & __INSN_LENGTH_MASK) != __INSN_LENGTH_32) { + *r_insn = insn; + return 0; + } + insn_addr++; + if (__read_insn(regs, tmp, insn_addr)) + return -EFAULT; + *r_insn = (tmp << 16) | insn; + + return 0; + } else { + u32 __user *insn_addr = (u32 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) { + *r_insn = insn; + return 0; + } + insn &= GENMASK(15, 0); + *r_insn = insn; + + return 0; + } +} +#endif + union reg_data { u8 data_bytes[8]; ulong data_ulong; @@ -208,10 +290,13 @@ int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; unsigned long epc = regs->epc; - unsigned long insn = get_insn(epc); - unsigned long addr = csr_read(mtval); + unsigned long insn; + unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + if (get_insn(regs, epc, &insn)) + return -1; + regs->epc = 0; if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) { @@ -275,8 +360,10 @@ int handle_misaligned_load(struct pt_regs *regs) } val.data_u64 = 0; - for (i = 0; i < len; i++) - val.data_bytes[i] = load_u8((void *)(addr + i)); + for (i = 0; i < len; i++) { + if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) + return -1; + } if (fp) return -1; @@ -291,10 +378,13 @@ int handle_misaligned_store(struct pt_regs *regs) { union reg_data val; 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 4/9] riscv: report perf event for misaligned fault Date: Tue, 4 Jul 2023 16:09:19 +0200 Message-Id: <20230704140924.315594-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770500290704892700?= X-GMAIL-MSGID: =?utf-8?q?1770500290704892700?= Add missing calls to account for misaligned fault event using perf_sw_event(). Signed-off-by: Clément Léger --- arch/riscv/kernel/traps_misaligned.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 9daed7d756ae..804f6c5e0e44 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; @@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; From patchwork Tue Jul 4 14:09:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115814 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1253989vqx; Tue, 4 Jul 2023 07:15:32 -0700 (PDT) X-Google-Smtp-Source: APBJJlHdclI8scba0SEdkCG2LcWgngdMeAVTvN4qBdWbAAhaEnVma2R/DTcWc//9urFLQPefctf0 X-Received: by 2002:a05:6808:140f:b0:3a3:a041:d2e1 with SMTP id w15-20020a056808140f00b003a3a041d2e1mr8267122oiv.10.1688480131909; Tue, 04 Jul 2023 07:15:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480131; cv=none; d=google.com; s=arc-20160816; b=gZMhOe8zRgehBaKP21Vo1Py2BXNX+FoCNEgHD7GRRGKP3UU/nUMhW+Gv46mtrCOi7V QcIwGeo+AYyYEBw3h3XW95/+yUQ07X8+r84Skgql/VvlST79RDZLg2LTXpCh1+qIVpSt d7P23lMrJnGQ5ohvZ/KHGz1aOwuxnIRdIAiwDHUNzH257cNpKPNmEJcroP9JbHfeA8zg YrA59bW4VluMxMKZPAaILU/VSCUQW7K2TxwzpzPsLK6A0Jig1rE1uuDTllizGxUlXZqK RICqQYkih6NphnYNiaOw3kat9Arh5WaphDLsD8TJnphqJczLfjvwlEZ6VYnUDaPW/img 0O2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JxIfI7L8QtMZ5B4oD7tB4oC/oAl/mItJTbe2vhSQwvU=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=v+E60ZqLwAOyIipm2Fk5NbPcyRWgknbdg7maElYrFQMZ1JXwCtLz0/l5QBuO8TRNXm tLik6FkFalI2t3EK9ph6IZX/DqWPSHZSCVU+LHVnsZY4HfSAPs74RNl7Z2EyfpPKDjXJ tz7eCpjEMmDRbwV2K3yg4tqLw+1Q6STztdK7vqFxb0s4XJ8hZB3i9XZw2dVZR2J+X9aC LsM6OAYolEBTSq2DFWGynVHyeNiT5iTt0iXiWIBjJ7F9DBRnQVCE3NMEAxtQMsWDjVd7 sVF8mg060ezkgt+m8EZSCp3kXgJ2o6Xxl+wkyIckncEVqEn9VgWs+1EW48XhcN3UFSoP EiZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=Q0HCtGy+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 5/9] riscv: add support for sysctl unaligned_enabled control Date: Tue, 4 Jul 2023 16:09:20 +0200 Message-Id: <20230704140924.315594-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770499742464065143?= X-GMAIL-MSGID: =?utf-8?q?1770499742464065143?= This sysctl tuning option allows the user to disable misaligned access handling globally on the system. This will also be used by misaligned detection code to temporarily disable misaligned access handling. Signed-off-by: Clément Léger --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/traps_misaligned.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c69572fbe613..99fd951def39 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -139,6 +139,7 @@ config RISCV select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC select SPARSE_IRQ + select SYSCTL_ARCH_UNALIGN_ALLOW select SYSCTL_EXCEPTION_TRACE select THREAD_INFO_IN_TASK select TRACE_IRQFLAGS_SUPPORT diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 804f6c5e0e44..39ec6caa6234 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -287,6 +287,9 @@ union reg_data { u64 data_u64; }; +/* sysctl hooks */ +int unaligned_enabled __read_mostly = 1; /* Enabled by default */ + int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; @@ -297,6 +300,9 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; @@ -387,6 +393,9 @@ int handle_misaligned_store(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; From patchwork Tue Jul 4 14:09:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115817 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1256009vqx; Tue, 4 Jul 2023 07:18:30 -0700 (PDT) X-Google-Smtp-Source: APBJJlG2hSlETXkLpwh95QkzqYS/WOyHGrUdvSN5YXcaUCjI7A45MMcv4rHnovXhaCdSoIK6Sfqi X-Received: by 2002:a92:d2c8:0:b0:345:af82:dc3a with SMTP id w8-20020a92d2c8000000b00345af82dc3amr13603895ilg.14.1688480310184; Tue, 04 Jul 2023 07:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480310; cv=none; d=google.com; s=arc-20160816; b=vhOQi3G+T0aIlC86bY3LZQ7A3zRMeKy0MjH/p+WokPQbd5kAo7Jx8wwPCtrpb++xv1 S4lMFu/xaxNUQ5suplvCvCyiRvwnFQmrW/W0llVnndNHHfAjBpnfSW2D5/6vwEqlbRh+ f8lDe56wqXTNppuq1HNUKEi12i8eFbhQgVbUx4isdLJ19EWNyOqDdo3i+R4A+K9Ue40l rT5QHigPl3lRKSlc5K/jBuNgEK4ons88Ap/G8EGwfOWrHgrUHUMkDoS2IJHgwa+OJKKx b2XWJPCAh8u3D0cbk+lUbYSTE+5fsr1GUZFIuRt6OzeQk6Kdd2vIz/U96DF0sdebj9CW vubQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pj3KtNcskxGwBQpyjif+BbQZv3sqa1IZuxdbRGC5RTE=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=mCDesu/2CUFhKXH8grFtn/dnGMSBJ9uirfuQA7zovwLIibBWFiiXVKwKGfH+9Lmihc D855+Udyj/88QgdsWL41KQReybS6MWfHAlmvf8ZQ8jTpTaQRaJta4h5wV0rC+Tiiqijd U8XPd3HVU3py6xMSfgcZP2GYHKPNmk/A2BB/KMJ7k1nujedSJXCKXeoTAnNp4Fbcp8W/ 79yDT7e0/xw5ZverODeERT9KllJSGAHpVzXVUwsy9xVIdiy9rSMqK/YocCx+gZoWbHt6 WDOdfYJc2c36KMxckuZldMrc4uy5ltSgJZJCpx6dY3e9ZBDUeLxGEwwZRMXt3vbvvNow 6BxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=JshnIAR8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 6/9] riscv: add support for SBI misalignment trap delegation Date: Tue, 4 Jul 2023 16:09:21 +0200 Message-Id: <20230704140924.315594-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770499929393858335?= X-GMAIL-MSGID: =?utf-8?q?1770499929393858335?= Add support for misalignment trap delegation by setting it with SBI_EXT_FW_FEATURE SBI extension. This extension allows to control SBI behavior by requesting to set them to specific value. In order to implement prctl(PR_SET_UNALIGN, PR_UNALIGN_SIGBUS) behavior properly, we need to let the kernel handle the misalignment error by itself. Signed-off-by: Clément Léger --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ arch/riscv/kernel/sbi.c | 21 +++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..c1b74c7d0d56 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_FW_FEATURE = 0x46574654, /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START = 0x08000000, @@ -236,6 +237,16 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FW_FEATURE_SET 0x0 +#define SBI_EXT_FW_FEATURE_GET 0x1 + +enum sbi_fw_features_t { + SBI_FW_FEATURE_MISALIGNED_DELEG = 0, + + SBI_FW_FEATURE_MAX, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index c672c8ba9a2a..3be48791455a 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -494,6 +494,16 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, } EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid); +static int sbi_fw_feature_set(enum sbi_fw_features_t feature, bool set) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_FW_FEATURE, SBI_EXT_FW_FEATURE_SET, feature, + set, 0, 0, 0, 0); + + return sbi_err_map_linux_errno(ret.error); +} + static void sbi_srst_reset(unsigned long type, unsigned long reason) { sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, @@ -624,6 +634,17 @@ void __init sbi_init(void) sbi_srst_reboot_nb.priority = 192; register_restart_handler(&sbi_srst_reboot_nb); } + /* + * TODO: this will likely need to be updated when SBI extension + * is ratified + */ + if ((sbi_spec_version >= sbi_mk_version(1, 0)) && + (sbi_probe_extension(SBI_EXT_FW_FEATURE) > 0)) { + pr_info("SBI FW_FEATURE extension detected\n"); + /* Request misaligned handling delegation */ + sbi_fw_feature_set(SBI_FW_FEATURE_MISALIGNED_DELEG, + true); + } } else { __sbi_set_timer = __sbi_set_timer_v01; __sbi_send_ipi = __sbi_send_ipi_v01; From patchwork Tue Jul 4 14:09:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115821 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1259556vqx; Tue, 4 Jul 2023 07:24:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlHGAMJW4ctK7tpp6DycNJM3/VHU2oIAih/XxaSYEM0HqCzYM0fdkLcbM3C27lVXPPEx/lEP X-Received: by 2002:a17:902:e541:b0:1b8:a54c:6183 with SMTP id n1-20020a170902e54100b001b8a54c6183mr2648004plf.46.1688480669513; Tue, 04 Jul 2023 07:24:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480669; cv=none; d=google.com; s=arc-20160816; b=hHrZbC7K1L1KfRrPtAGqkM28gWHRlkT1YXcYTGbrwB2nFYL1E4m4Ge0fuBd6zUY5YK 32D7H3YYAhRlhMfXn3dixNczkgUh0siwNkN0OtqVwpsGWt3vcJww95GTQcPSYwZzTK3v YVsuGx7p20UuKkVzEFCG8tW55lEgACMXb//5+mJDRdFTBFN4eja91TbNk09k4bosCT2G ctEXSOLxWTFeGATO67d+xReUWV0Ttvno9rCcMiJFS5gzxAbB6KZ1z4Pr5MuHfKts8zmV sGSk6Ya/nUzvwdlgvj/UQ+2iI/SCw9Q0AcpJGvp+c/23EeDs4lxHCjaPWya3E2UYxQt0 VdSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UuTcFW+DQo5Mx+nRwuPd1unzmxWKunsazuyjaErlxZk=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=wt7Abn1LxuHH1MQnB1Kkuw3Ib/sSo+9kZziEocpoxHy/oV4JttuUxr4PwYmh2QfPdp vLNfYud+YZuDXjweeT2/QSkmS4CWuznZjTMBNOC1Ator2y4OxPr0EdWFX9R03cSMx+QG DuVHDcFzM6kCe52Kaijlxn2vrZ5xJu98EUzgVqQaeFgOAHoH6PcpoA+uxlCYBlk890jj lOlbUylGXDCMR3eJ32+gSQA67TtVoeCc4PV9ike0Zz0fGy5+BE5x5HvU6aP03SLwjkg4 2WphGDsLyTXNTvi5RJGqLh26jBDtF1Q2LQZlDbumSv9+n+h8ank3L0WVE6+b6N+Yt0GN S4fA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=NIi0ovTy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 7/9] riscv: report misaligned accesses emulation to hwprobe Date: Tue, 4 Jul 2023 16:09:22 +0200 Message-Id: <20230704140924.315594-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770500306531043085?= X-GMAIL-MSGID: =?utf-8?q?1770500306531043085?= hwprobe provides a way to report if misaligned access are emulated. In order to correctly populate that feature, if the SBI delegated us misaligned access handling, then we can check if it actually traps when doing a misaligned access. This can be checked using an exception table entry which will actually be used when a misaligned access is done from kernel mode. Signed-off-by: Clément Léger --- arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/setup.c | 2 ++ arch/riscv/kernel/traps_misaligned.c | 32 ++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 808d5403f2ac..7e968499db49 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -20,4 +20,6 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); DECLARE_PER_CPU(long, misaligned_access_speed); +void __init misaligned_emulation_init(void); + #endif diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..820a8158e4f7 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -284,6 +285,7 @@ void __init setup_arch(char **cmdline_p) init_resources(); sbi_init(); + misaligned_emulation_init(); #ifdef CONFIG_KASAN kasan_init(); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 39ec6caa6234..243ef9314734 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -441,3 +443,33 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } + +void __init misaligned_emulation_init(void) +{ + int cpu; + unsigned long emulated = 1, tmp_var; + + /* Temporarily disable unaligned accesses support so that we fixup the + * exception for code below. + */ + unaligned_enabled = 0; + + __asm__ __volatile__ ( + "1:\n" + " ld %[tmp], 1(%[ptr])\n" + " li %[emulated], 0\n" + "2:\n" + _ASM_EXTABLE(1b, 2b) + : [emulated] "+r" (emulated), [tmp] "=r" (tmp_var) + : [ptr] "r" (&tmp_var) + : "memory" ); + + unaligned_enabled = 1; + if (!emulated) + return; + + for_each_possible_cpu(cpu) { + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_EMULATED; + } +} From patchwork Tue Jul 4 14:09:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115818 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1257038vqx; Tue, 4 Jul 2023 07:20:22 -0700 (PDT) X-Google-Smtp-Source: APBJJlE5u16IKnByEHhORdYIiBIhdU17l5/qM7VWrZdFBt8Vy44bkVT4mE3+zYR1fmknciMJFJpQ X-Received: by 2002:a05:687c:12:b0:1ad:3199:cead with SMTP id yf18-20020a05687c001200b001ad3199ceadmr12478941oab.15.1688480422406; Tue, 04 Jul 2023 07:20:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688480422; cv=none; d=google.com; s=arc-20160816; b=aRYqVWd+jqQvt2YmX7qxA9chVgsPQVWyKxHBFliN8hAEazXfAKvHq2X6gqjQCnlTj2 OwrV04CwoBH1Rehs0356NTQ60gsK/B8Lt3y04JZNTggZR3BCsEHym2t83J19ssztHxkB jgW0DcOExGutz6LdXzJRv2D0t0tEdc8Du4yiqltg4tKVBzelYKRzrDMHul0iPmdgbjQR xopHwYCAbRxGKYRk1kqZA5exfg9cU7GM3raBeC+DVrHPKHzm/3+NE8BXiE/xSbtQWWt1 Sg232MxPC+4sufFYAI1pOTI25ZFnw+28+ztJWQj9NnUotXZyYotn0iMg54+K8OrUg491 NIwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AzBMq7R5xdVR7lBpakM9B1ewv3x8Aa9s+j6b6UY73u8=; fh=9wrou+MQEPZGr1Z6SaqMAXmpjnaJyNXl4Ao+MUOh3Is=; b=Osp/Rw0XrFGCQUaZODSJu6yumomJFCMa1cuPS2O7G0/wjvPKn6V8Wk7Kk/izIK7Qpw kAghdU7qepMIAjKB5p1r3Lqwma4nzkcFm+Ydbj2LK2AmfKtcB52oPC/Z81YyKQu80vEz FZ6I3Y35OQ21udyn/cabAhnEatMkGiM6cweMgtV3tkMKYAr+TqkR6CJ2xzxU02JXgMmu AmtkTZT+ZbyhWbkZ3X2lZhZPMP1PokuOmtym5yci7q4i0AwCN2dwHTr4gcBAJ8XiJyHb bY7Cj/0pSu0K0YU61n9iiMtp3Meutw4F61UVyXF/ufSxSiR1OnCjJdfIjAYgAY2QsG5U lmvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=hvWRzizV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 8/9] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Date: Tue, 4 Jul 2023 16:09:23 +0200 Message-Id: <20230704140924.315594-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770500047278090846?= X-GMAIL-MSGID: =?utf-8?q?1770500047278090846?= Now that trap support is ready to handle misalignment errors in S-mode, allow the user to control the behavior of misalignment accesses using prctl(). Add an align_ctl flag in thread_struct which will be used to determine if we should SIGBUS the process or not on such fault. Signed-off-by: Clément Léger --- arch/riscv/include/asm/cpufeature.h | 8 ++++++++ arch/riscv/include/asm/processor.h | 9 +++++++++ arch/riscv/kernel/process.c | 18 ++++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 7 +++++++ 4 files changed, 42 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 7e968499db49..e2fd6fc7157f 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -6,6 +6,8 @@ #ifndef _ASM_CPUFEATURE_H #define _ASM_CPUFEATURE_H +#include + /* * These are probed via a device_initcall(), via either the SBI or directly * from the corresponding CSRs. @@ -20,6 +22,12 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); DECLARE_PER_CPU(long, misaligned_access_speed); +static inline bool misaligned_access_emulated(void) +{ + return per_cpu(misaligned_access_speed, 0) == + RISCV_HWPROBE_MISALIGNED_EMULATED; +} + void __init misaligned_emulation_init(void); #endif diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..4e6667d5ca68 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include +#include #include @@ -39,6 +40,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + unsigned long align_ctl; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -51,6 +53,7 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, #define INIT_THREAD { \ .sp = sizeof(init_stack) + (long)&init_stack, \ + .align_ctl = PR_UNALIGN_NOPRINT, \ } #define task_pt_regs(tsk) \ @@ -80,6 +83,12 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern int get_unalign_ctl(struct task_struct *, unsigned long addr); +extern int set_unalign_ctl(struct task_struct *, unsigned int val); + +#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) +#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e2a060066730..88a71359396b 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -24,6 +24,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -40,6 +41,23 @@ void arch_cpu_idle(void) cpu_do_idle(); } +int set_unalign_ctl(struct task_struct *tsk, unsigned int val) +{ + if (!misaligned_access_emulated()) + return -EINVAL; + + tsk->thread.align_ctl = val; + return 0; +} + +int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) +{ + if (!misaligned_access_emulated()) + return -EINVAL; + + return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr); +} + void __show_regs(struct pt_regs *regs) { show_regs_print_info(KERN_DEFAULT); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 243ef9314734..5fb6758b0bf9 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -305,6 +306,9 @@ int handle_misaligned_load(struct pt_regs *regs) if (!unaligned_enabled) return -1; + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1; @@ -398,6 +402,9 @@ int handle_misaligned_store(struct pt_regs *regs) if (!unaligned_enabled) return -1; + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1; From patchwork Tue Jul 4 14:09:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 115823 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp1264569vqx; Tue, 4 Jul 2023 07:32:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ71th5SN/Xqk1TPffU4+q75qLyjJp5kY18v0VSm4OA4qaoTLaCsVK7u0fn02EZLJ2YH2SZq X-Received: by 2002:a05:6a20:3d1a:b0:123:a604:df73 with SMTP id y26-20020a056a203d1a00b00123a604df73mr18469800pzi.30.1688481164711; Tue, 04 Jul 2023 07:32:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688481164; cv=none; d=google.com; s=arc-20160816; b=0EaYAIfjdwIR2R7Bs11TiX1VimzS88mKoWgH2Gbz6zGgpNxd2/4i8s1dKsaEkb8Upo wc51w+5jd+FphJ095BP2K/JHe2CoM7nOvw6OOSB6buFkH9QrV0R1diqTgpKgCEI+FSRB YZHt/DyJQudRz4T6C/sU8N4G6KK7uGeYB20BB+ANGqDpHgs9URXMyrl/3kG2oJHbGrEx 9NIKcDRzhesovMmGDRaDcmT1/gD8wg1Dic5hURlKk3Lo//UmfBfi0dNPPeKE2/W8D9YQ AQc+0HegU0ydLaeLVCMJPOElDRsxx/UD5y1Ltlfa8YxZ3NqMNuIhdHk41DBmKXGHnp+E 6uJw== ARC-Message-Signature: i=1; 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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 9/9] riscv: add floating point insn support to misaligned access emulation Date: Tue, 4 Jul 2023 16:09:24 +0200 Message-Id: <20230704140924.315594-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770500825477356897?= X-GMAIL-MSGID: =?utf-8?q?1770500825477356897?= This support is partially based of openSBI misaligned emulation floating point instruction support. It provides support for the existing floating point instructions (both for 32/64 bits as well as compressed ones). Since floating point registers are not part of the pt_regs struct, we need to modify them directly using some assembly. We also dirty the pt_regs status in case we modify them to be sure context switch will save FP state. With this support, Linux is on par with openSBI support. Signed-off-by: Clément Léger --- arch/riscv/kernel/fpu.S | 117 +++++++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 152 ++++++++++++++++++++++++++- 2 files changed, 265 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S index dd2205473de7..2785badb247c 100644 --- a/arch/riscv/kernel/fpu.S +++ b/arch/riscv/kernel/fpu.S @@ -104,3 +104,120 @@ ENTRY(__fstate_restore) csrc CSR_STATUS, t1 ret ENDPROC(__fstate_restore) + +#define get_f32(which) fmv.x.s a0, which; j 2f +#define put_f32(which) fmv.s.x which, a1; j 2f +#if __riscv_xlen == 64 +# define get_f64(which) fmv.x.d a0, which; j 2f +# define put_f64(which) fmv.d.x which, a1; j 2f +#else +# define get_f64(which) fsd which, 0(a1); j 2f +# define put_f64(which) fld which, 0(a1); j 2f +#endif + +.macro fp_access_prologue + /* + * Compute jump offset to store the correct FP register since we don't + * have indirect FP register access + */ + sll t0, a0, 3 + la t2, 1f + add t0, t0, t2 + li t1, SR_FS + csrs CSR_STATUS, t1 + jr t0 +1: +.endm + +.macro fp_access_epilogue +2: + csrc CSR_STATUS, t1 + ret +.endm + +#define fp_access_body(__access_func) \ + __access_func(f0); \ + __access_func(f1); \ + __access_func(f2); \ + __access_func(f3); \ + __access_func(f4); \ + __access_func(f5); \ + __access_func(f6); \ + __access_func(f7); \ + __access_func(f8); \ + __access_func(f9); \ + __access_func(f10); \ + __access_func(f11); \ + __access_func(f12); \ + __access_func(f13); \ + __access_func(f14); \ + __access_func(f15); \ + __access_func(f16); \ + __access_func(f17); \ + __access_func(f18); \ + __access_func(f19); \ + __access_func(f20); \ + __access_func(f21); \ + __access_func(f22); \ + __access_func(f23); \ + __access_func(f24); \ + __access_func(f25); \ + __access_func(f26); \ + __access_func(f27); \ + __access_func(f28); \ + __access_func(f29); \ + __access_func(f30); \ + __access_func(f31) + + +/* + * Disable compressed instructions set to keep a constant offset between FP + * load/store/move instructions + */ +.option norvc +/* + * put_f32_reg - Set a FP register from a register containing the value + * a0 = FP register index to be set + * a1 = value to be loaded in the FP register + */ +SYM_FUNC_START(put_f32_reg) + fp_access_prologue + fp_access_body(put_f32) + fp_access_epilogue +SYM_FUNC_END(put_f32_reg) + +/* + * get_f32_reg - Get a FP register value and return it + * a0 = FP register index to be retrieved + */ +SYM_FUNC_START(get_f32_reg) + fp_access_prologue + fp_access_body(get_f32) + fp_access_epilogue +SYM_FUNC_END(put_f32_reg) + +/* + * put_f64_reg - Set a 64 bits FP register from a value or a pointer. + * a0 = FP register index to be set + * a1 = value/pointer to be loaded in the FP register (when xlen == 32 bits, we + * load the value to a pointer). + */ +SYM_FUNC_START(put_f64_reg) + fp_access_prologue + fp_access_body(put_f64) + fp_access_epilogue +SYM_FUNC_END(put_f64_reg) + +/* + * put_f64_reg - Get a 64 bits FP register value and returned it or store it to + * a pointer. + * a0 = FP register index to be retrieved + * a1 = If xlen == 32, pointer which should be loaded with the FP register value + * or unused if xlen == 64. In which case the FP register value is returned + * through a0 + */ +SYM_FUNC_START(get_f64_reg) + fp_access_prologue + fp_access_body(get_f64) + fp_access_epilogue +SYM_FUNC_END(get_f64_reg) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 5fb6758b0bf9..c4c4672a4554 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -156,6 +156,115 @@ #define PRECISION_S 0 #define PRECISION_D 1 +#ifdef CONFIG_FPU + +#define FP_GET_RD(insn) (insn >> 7 & 0x1F) + +extern void put_f32_reg(unsigned long fp_reg, unsigned long value); + +static int set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) +{ + unsigned long fp_reg = FP_GET_RD(insn); + + put_f32_reg(fp_reg, val); + regs->status |= SR_FS_DIRTY; + + return 0; +} + +extern void put_f64_reg(unsigned long fp_reg, unsigned long value); + +static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) +{ + unsigned long fp_reg = FP_GET_RD(insn); + unsigned long value; + +#if __riscv_xlen == 32 + value = (unsigned long) &val; +#else + value = val; +#endif + put_f64_reg(fp_reg, value); + regs->status |= SR_FS_DIRTY; + + return 0; +} + +#if __riscv_xlen == 32 +extern void get_f64_reg(unsigned long fp_reg, u64 *value); + +static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + u64 val; + + get_f64_reg(fp_reg, &val); + regs->status |= SR_FS_DIRTY; + + return val; +} +#else + +extern unsigned long get_f64_reg(unsigned long fp_reg); + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val = get_f64_reg(fp_reg); + regs->status |= SR_FS_DIRTY; + + return val; +} + +#endif + +extern unsigned long get_f32_reg(unsigned long fp_reg); + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val = get_f32_reg(fp_reg); + regs->status |= SR_FS_DIRTY; + + return val; +} + +#else /* CONFIG_FPU */ +static void set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) {} + +static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {} + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +#endif + +#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs)) +#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs)) +#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs)) + +#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs)) +#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs)) +#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs)) + #ifdef CONFIG_RISCV_M_MODE static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { @@ -374,15 +483,21 @@ int handle_misaligned_load(struct pt_regs *regs) return -1; } + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + val.data_u64 = 0; for (i = 0; i < len; i++) { if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) return -1; } - if (fp) - return -1; - SET_RD(insn, regs, val.data_ulong << shift >> shift); + if (!fp) + SET_RD(insn, regs, val.data_ulong << shift >> shift); + else if (len == 8) + set_f64_rd(insn, regs, val.data_u64); + else + set_f32_rd(insn, regs, val.data_ulong); regs->epc = epc + INSN_LEN(insn); @@ -395,7 +510,7 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long epc = regs->epc; unsigned long insn; unsigned long addr = regs->badaddr; - int i, len = 0; + int i, len = 0, fp = 0; perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); @@ -418,6 +533,14 @@ int handle_misaligned_store(struct pt_regs *regs) } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { len = 8; #endif + } else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2(insn, regs); + } else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2(insn, regs); } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { len = 2; #if defined(CONFIG_64BIT) @@ -436,11 +559,32 @@ int handle_misaligned_store(struct pt_regs *regs) ((insn >> SH_RD) & 0x1f)) { len = 4; val.data_ulong = GET_RS2C(insn, regs); + } else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2C(insn, regs); +#if !defined(CONFIG_64BIT) + } else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2C(insn, regs); +#endif } else { regs->epc = epc; return -1; } + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + for (i = 0; i < len; i++) { if (store_u8(regs, (void *)(addr + i), val.data_bytes[i])) return -1;