From patchwork Fri Oct 28 22:55:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1083504wru; Fri, 28 Oct 2022 16:00:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7iyQ3i1mrRzQAUjWVk5sAvB/n8ULsiIRt79j2bxFjZeNz7fOZxxZvSqS6xUEsQX2kBNudj X-Received: by 2002:a17:907:3e02:b0:782:1267:f2c8 with SMTP id hp2-20020a1709073e0200b007821267f2c8mr1424178ejc.585.1666998052038; Fri, 28 Oct 2022 16:00:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666998052; cv=none; d=google.com; s=arc-20160816; b=u9niIdjCAVCmO0AJa7Yf1iJ/ks7Zml7MEeIggAiZ0s4cY0HIoXPyt8pWOj2ssTXbmT GsrR+dZPD74FfSEXqoS2vLgURQ1LZhOx1WRKeakFoWO1ZJiqaVxB1XgpWXa2j5khDq6T WT0G8H6u/0hwNTB15Vxhem0lOHQgpkejQ8SJrtwqO1OsYvftejGrlwR6W2cGVPyVejvt 4Myncl9UCXWoTQLczZ50OLmoDm6Fw7lthr96ZX/X5ukOMKMjKNMvAuk75aCu/KaCl3l+ IcLwCzfaKwT8nMYEuFD3W5ycg9Ti0FcuM/4S02kppJPm9OrmQaR92d5Bb6B3POd7SawA CY3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8fNxdddGM77vcHk/0yqRmbXWir62aBErY4gRc5JUiCw=; b=GID9iZ84R8lEr7TcxrCYTkbMLGxKKGTpxK9MB/dpIglcxdx+dCBL7Dzb3k6JRnIKqg NRbviD+egBIfnQyCALhpW76vYq4rRPQxDSYsK8+0RiA87iP1iMIgwSH7UC9SCUZpUKF2 ZAyGBDeAsxdanvBxOOFmJ7fAQShWa9oA0PNmabYPJYp8fW3M1nU+ClCuZWtBdM7O8E78 n+ro4btqarS0v8cRoiWEutR35G47iHGShzQxvsVAsTP51onGfh07kmhFtO8srNHO+X4i Ex0z5Iq7MNwRtYSvADBVVBJHEspdWV5IqVpR5oCSBSXEBG7rwf1SlF6tOnoUqHylC49e aJ3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=VR4p+0NC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bu8-20020a170906a14800b0078dcd8dfac5si5026608ejb.467.2022.10.28.16.00.28; Fri, 28 Oct 2022 16:00:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=VR4p+0NC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbiJ1Wz6 (ORCPT + 99 others); Fri, 28 Oct 2022 18:55:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230229AbiJ1Wzm (ORCPT ); Fri, 28 Oct 2022 18:55:42 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C60F71D441A; Fri, 28 Oct 2022 15:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1666997727; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8fNxdddGM77vcHk/0yqRmbXWir62aBErY4gRc5JUiCw=; b=VR4p+0NC6nSMVR2ccrFgESFuFGCFuETqs+ZwWDQyh3U87liaLemoSCnJz7LEF2/C+CxVxh wRddo3vkGjB7oWieN1dDQGXUBgEbVWMW18TMW328k7xBDt10JxEXGYJN0xdj25nMTAggf4 cvJeJqdcxZfn8VQ8OHzfzuu0omA4bkI= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, od@opendingux.net, Paul Cercueil Subject: [PATCH v2 1/4] dt-bindings: rtc: ingenic: Rework compatible strings and add #clock-cells Date: Fri, 28 Oct 2022 23:55:16 +0100 Message-Id: <20221028225519.89210-2-paul@crapouillou.net> In-Reply-To: <20221028225519.89210-1-paul@crapouillou.net> References: <20221028225519.89210-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747974149342618910?= X-GMAIL-MSGID: =?utf-8?q?1747974149342618910?= The RTC in the JZ4770 is compatible with the JZ4760, but has an extra register that permits to configure the behaviour of the CLK32K pin. The same goes for the RTC in the JZ4780. Therefore, the ingenic,jz4770-rtc and ingenic,jz4780-rtc strings do not fall back anymore to ingenic,jz4760-rtc. The ingenic,jz4780-rtc string now falls back to the ingenic,jz4770-rtc string. Additionally, since the RTCs in the JZ4770 and JZ4780 support outputting the input oscillator's clock to the CLK32K pin, the RTC node is now also a clock provider on these SoCs, so a #clock-cells property is added. Signed-off-by: Paul Cercueil --- v2: - add constraint on which SoCs can have the #clock-cells property - add JZ4780 example which has a #clock-cells .../devicetree/bindings/rtc/ingenic,rtc.yaml | 32 +++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml index b235b2441997..d63bb727cee5 100644 --- a/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/ingenic,rtc.yaml @@ -11,6 +11,16 @@ maintainers: allOf: - $ref: rtc.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - ingenic,jz4770-rtc + then: + properties: + "#clock-cells": false properties: compatible: @@ -18,14 +28,14 @@ properties: - enum: - ingenic,jz4740-rtc - ingenic,jz4760-rtc + - ingenic,jz4770-rtc - items: - const: ingenic,jz4725b-rtc - const: ingenic,jz4740-rtc - items: - enum: - - ingenic,jz4770-rtc - ingenic,jz4780-rtc - - const: ingenic,jz4760-rtc + - const: ingenic,jz4770-rtc reg: maxItems: 1 @@ -39,6 +49,9 @@ properties: clock-names: const: rtc + "#clock-cells": + const: 0 + system-power-controller: description: | Indicates that the RTC is responsible for powering OFF @@ -83,3 +96,18 @@ examples: clocks = <&cgu JZ4740_CLK_RTC>; clock-names = "rtc"; }; + + - | + #include + rtc: rtc@10003000 { + compatible = "ingenic,jz4780-rtc", "ingenic,jz4770-rtc"; + reg = <0x10003000 0x4c>; + + interrupt-parent = <&intc>; + interrupts = <32>; + + clocks = <&cgu JZ4780_CLK_RTCLK>; + clock-names = "rtc"; + + #clock-cells = <0>; + }; From patchwork Fri Oct 28 22:55:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1083458wru; Fri, 28 Oct 2022 16:00:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6UoKWazsCF0kdpmSmr7nsFMLVIID9tA1l1CzFaST5BYksp+rHmUTk+BivnvVTEFFBa4eao X-Received: by 2002:a17:907:a48:b0:7a7:3714:1629 with SMTP id be8-20020a1709070a4800b007a737141629mr1397154ejc.569.1666998041826; Fri, 28 Oct 2022 16:00:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666998041; cv=none; d=google.com; s=arc-20160816; b=eAxn7bXstR2TpuaRnnhDo5L7YhbEwXVPPFVsBmoQhPUdb+QdQy0Q7X1SSHXXPChAyT dcRIhxVeZ2jecsjXAVwbOFHu2YFNuM4LJzwYqyNvr0nmsFZ5ZuHw3eDkqTgmzdz+4RoC jvVHroQ9bsTv3naT29rm01uGozpxHdScHpyk2SltNeFkTcGixUxyXgfuuG31fqaXOcmk X3FrTHuIILD3V/hy3ynIibcyb3RdvX325drkpttKigc3YUQSrQdvvVsRuMvQ2cBLh+NR L5Kw+08bdRwWQyy6NbjOAhg3gWeYt/wIt0FmoNnv6ms+N6RFhfo1oPWG+8FJv91zKv97 btAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VRHSnhFqlAbB4ByXHkBp5FSSjtyBVVmk/Lv0SwF9ti8=; b=sSia2XQvqT37IJOKu8l8nUFt87ZtsIRJ58NY8GDONNRknmRaLKUjyU3TplWd16Dov7 B1Xe86X8u7oBl+0l3vnd5aGxpWU7T/bnmxLpBXq1jUOwtToZYzX0N9nOnLyPILvZWh9f 9qN3ZJZkeJ7ta8w7X/C010UI6lbCSJt2A0iCC7Z3ZwmzA8BJV9krM0IUZqP/bMpbTUMv QXdgV+ESurKsdiV7OlqyMzvwuOeHYjjc2F8MiHZ/RHPp+DthwWyLSvOy8vKSy8jH5+sn rvqOOgozPNpxMFqfJ2C469u3Y4oz1527poD1/Le1Q+moLL1UhhavcU/Nq4jTtxW5xHcH a9Ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=ok9Fs3gb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o24-20020a50fd98000000b004608c0b9a8asi765984edt.201.2022.10.28.16.00.18; Fri, 28 Oct 2022 16:00:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=ok9Fs3gb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230149AbiJ1W4G (ORCPT + 99 others); Fri, 28 Oct 2022 18:56:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230030AbiJ1Wzz (ORCPT ); Fri, 28 Oct 2022 18:55:55 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D2BA1EF06D; Fri, 28 Oct 2022 15:55:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1666997728; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VRHSnhFqlAbB4ByXHkBp5FSSjtyBVVmk/Lv0SwF9ti8=; b=ok9Fs3gbFSdHNylRdcL+uco+GLwquJAiuljCCeoCxNdupA9Q+12Aj8bhmYqlOMAgHfFRAW xaBoP5hpECfimN0t+gXSLjp8ifJz5rqSdEQ/tASvC1Zf+1evUBlMdocy03o2CCEhESbKHj YRPqJANJ3ZQpMI1BvgxcNloqgQGOUk8= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, od@opendingux.net, Paul Cercueil Subject: [PATCH v2 2/4] rtc: jz4740: Use readl_poll_timeout Date: Fri, 28 Oct 2022 23:55:17 +0100 Message-Id: <20221028225519.89210-3-paul@crapouillou.net> In-Reply-To: <20221028225519.89210-1-paul@crapouillou.net> References: <20221028225519.89210-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747974138491107698?= X-GMAIL-MSGID: =?utf-8?q?1747974138491107698?= Use readl_poll_timeout() from instead of using custom poll loops. The timeout settings are different, but that shouldn't be much of a problem. Instead of polling 10000 times in a close loop, it polls for one millisecond. Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index c383719292c7..4ee6e5ee09b1 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -69,19 +70,15 @@ static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg) static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc) { uint32_t ctrl; - int timeout = 10000; - do { - ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); - } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); - - return timeout ? 0 : -EIO; + return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, + ctrl & JZ_RTC_CTRL_WRDY, 0, 1000); } static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc) { uint32_t ctrl; - int ret, timeout = 10000; + int ret; ret = jz4740_rtc_wait_write_ready(rtc); if (ret != 0) @@ -89,11 +86,8 @@ static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc) writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); - do { - ctrl = readl(rtc->base + JZ_REG_RTC_WENR); - } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); - - return timeout ? 0 : -EIO; + return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, + ctrl & JZ_RTC_WENR_WEN, 0, 1000); } static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg, From patchwork Fri Oct 28 22:55:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1083855wru; Fri, 28 Oct 2022 16:01:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5/mzQjImbPCHeYhgTZtIdJDnrJAUwPFS7giFbb5W0Oh8x2tLPcnY+Q4akaqUufSoJKBBt4 X-Received: by 2002:a17:907:1ca2:b0:78d:ec49:9c2f with SMTP id nb34-20020a1709071ca200b0078dec499c2fmr1411403ejc.308.1666998100604; Fri, 28 Oct 2022 16:01:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666998100; cv=none; d=google.com; s=arc-20160816; b=bVphAdqlZNJYxVlxksDS7wu6lpWT96k1GULrglTgnvynNrEnJK6k3akLGNk8rZb/9p 9gv7UlSTEchTeJhyO1wrEvVTGWEC+QL//hKiapLAwf/ODlmuOwxvOGMpx3DRnrACYMKf BBsD8ftooPdOmAAIq7SLVkZ8H431jEsdRTJZMc4S2HKUdxB1Ajiau4FtyoGan48PcUZV 1mJqAvDtAwDQJp7Uy5BLKGHp/pZreaVBCmzHDjAP1pzy8nCV4V3+QIf/gTV6EjFJCfVe I7I0EoyO03dxzRzkRqK79/s2JGZdFuy4HHhSHWFAhPxzzOA2B540Fr/gzzqvV5YAsoZB QoXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mlXqJG8CZMGS3pje+4PkrK1pUmHZdP2M9X8uDTfAoIQ=; b=jv6H3B227tIM7sTWkYsRieJqkBy0vBXHOiyqH5JiCFV0A8l+ZZfioJURtqqxa0Bl5Y RpKWHAdQfAuDPg2vfdEdryY5nLjpHzp26ffQHt2ajseFUdZUaI3Lc+3pqjtdJF829vDI InxJumAXORR99hmtSn/Lj+Dk6NDf/MATws54rl5fmWvSKMHLs0BAzl83+ZLrI8Uhn976 dvU4PXmMqNspGoa+JVXkrhSJ5oFzTPmIlsfu8mBNa6HwzUMx5AMJQFYTj0XI7yZFuQ8g 4fzTw0pwb5Kzd3R3q9ayCFRGuSjZxt0/BB8IyhoRiOLE59mhZJB89tpKU6cz7MFptcwa AQNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=RtnGwrKZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hd39-20020a17090796a700b0073dced7204bsi6865963ejc.767.2022.10.28.16.01.15; Fri, 28 Oct 2022 16:01:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=RtnGwrKZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230112AbiJ1W4S (ORCPT + 99 others); Fri, 28 Oct 2022 18:56:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229717AbiJ1W4B (ORCPT ); Fri, 28 Oct 2022 18:56:01 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4661622BADF; Fri, 28 Oct 2022 15:55:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1666997729; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mlXqJG8CZMGS3pje+4PkrK1pUmHZdP2M9X8uDTfAoIQ=; b=RtnGwrKZMc+tnMe5uAD+C9HHgeKLBPZIy1pTQCSxP0cQgrFmG/C0PqnBoQQWN6BF38TEaf 1LOEo1c3kcWNoi3iFS0Y4cr7SUUkxmOUK+G+3iwj/vfZThvIAiFWSk2LNwVYHBVuMbyCUQ /ZHis+/+zUs7gJiOjYn5CJXpXoY9hf4= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, od@opendingux.net, Paul Cercueil Subject: [PATCH v2 3/4] rtc: jz4740: Register clock provider for the CLK32K pin Date: Fri, 28 Oct 2022 23:55:18 +0100 Message-Id: <20221028225519.89210-4-paul@crapouillou.net> In-Reply-To: <20221028225519.89210-1-paul@crapouillou.net> References: <20221028225519.89210-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747974200707036580?= X-GMAIL-MSGID: =?utf-8?q?1747974200707036580?= On JZ4770 and JZ4780, the CLK32K pin is configurable. By default, it is configured as a GPIO in input mode, and its value can be read through GPIO PD14. With this change, clients can now request the 32 kHz clock on the CLK32K pin, through Device Tree. This clock is simply a pass-through of the input oscillator's clock with enable/disable operations. This will permit the WiFi/Bluetooth chip to work on the MIPS CI20 board, which does source one of its clocks from the CLK32K pin. Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 50 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 4ee6e5ee09b1..1602e8a4283a 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -26,6 +27,7 @@ #define JZ_REG_RTC_WAKEUP_FILTER 0x24 #define JZ_REG_RTC_RESET_COUNTER 0x28 #define JZ_REG_RTC_SCRATCHPAD 0x34 +#define JZ_REG_RTC_CKPCR 0x40 /* The following are present on the jz4780 */ #define JZ_REG_RTC_WENR 0x3C @@ -45,10 +47,13 @@ #define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 #define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 +#define JZ_RTC_CKPCR_CK32PULL_DIS BIT(4) +#define JZ_RTC_CKPCR_CK32CTL_EN (BIT(2) | BIT(1)) + enum jz4740_rtc_type { ID_JZ4740, ID_JZ4760, - ID_JZ4780, + ID_JZ4770, }; struct jz4740_rtc { @@ -57,6 +62,8 @@ struct jz4740_rtc { struct rtc_device *rtc; + struct clk_hw clk32k; + spinlock_t lock; }; @@ -254,7 +261,8 @@ static void jz4740_rtc_power_off(void) static const struct of_device_id jz4740_rtc_of_match[] = { { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 }, { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 }, - { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 }, + { .compatible = "ingenic,jz4770-rtc", .data = (void *)ID_JZ4770 }, + { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4770 }, {}, }; MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match); @@ -295,6 +303,27 @@ static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc, jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks); } +static int jz4740_rtc_clk32k_enable(struct clk_hw *hw) +{ + struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k); + + return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, + JZ_RTC_CKPCR_CK32PULL_DIS | + JZ_RTC_CKPCR_CK32CTL_EN); +} + +static void jz4740_rtc_clk32k_disable(struct clk_hw *hw) +{ + struct jz4740_rtc *rtc = container_of(hw, struct jz4740_rtc, clk32k); + + jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, 0); +} + +static const struct clk_ops jz4740_rtc_clk32k_ops = { + .enable = jz4740_rtc_clk32k_enable, + .disable = jz4740_rtc_clk32k_disable, +}; + static int jz4740_rtc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -370,6 +399,23 @@ static int jz4740_rtc_probe(struct platform_device *pdev) dev_warn(dev, "Poweroff handler already present!\n"); } + if (rtc->type == ID_JZ4770) { + rtc->clk32k.init = CLK_HW_INIT("clk32k", "rtc", + &jz4740_rtc_clk32k_ops, 0); + + ret = devm_clk_hw_register(dev, &rtc->clk32k); + if (ret) { + dev_err(dev, "Unable to register clk32k clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &rtc->clk32k); + if (ret) { + dev_err(dev, "Unable to register clk32k clock provider: %d\n", ret); + return ret; + } + } + return 0; } From patchwork Fri Oct 28 22:55:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 12587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1084621wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hp14-20020a1709073e0e00b00797e151e584si6143621ejc.605.2022.10.28.16.02.48; Fri, 28 Oct 2022 16:03:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@crapouillou.net header.s=mail header.b=HZOqXXpf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbiJ1W43 (ORCPT + 99 others); Fri, 28 Oct 2022 18:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbiJ1W4I (ORCPT ); Fri, 28 Oct 2022 18:56:08 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E8C91F5246; Fri, 28 Oct 2022 15:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1666997730; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RvJj+3xY9RbhTi17+j1hh7xVviAFKRxXo4nyj02tbpM=; b=HZOqXXpfdzNX6zPLA4Js1X6WpuSNU4ALdzg43R66pCt/RenTadFhbMEsdRZcYygTQ1AL3u 0c6IvJqM2oPiJc5hzZih4B90wWxQWosKbEqk8yofZDHTU8xO/sG2nzBbQcgfYoWqxfSNyA BvuGgGA12b2iW26xvKZqhPdbMe5qoEw= From: Paul Cercueil To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, od@opendingux.net, Paul Cercueil Subject: [PATCH v2 4/4] rtc: jz4740: Support for fine-tuning the RTC clock Date: Fri, 28 Oct 2022 23:55:19 +0100 Message-Id: <20221028225519.89210-5-paul@crapouillou.net> In-Reply-To: <20221028225519.89210-1-paul@crapouillou.net> References: <20221028225519.89210-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747974307526025039?= X-GMAIL-MSGID: =?utf-8?q?1747974307526025039?= Write the NC1HZ and ADJC register fields, which allow to tweak the frequency of the RTC clock, so that it can run as accurately as possible. Signed-off-by: Paul Cercueil --- drivers/rtc/rtc-jz4740.c | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c index 1602e8a4283a..70b63ce75e21 100644 --- a/drivers/rtc/rtc-jz4740.c +++ b/drivers/rtc/rtc-jz4740.c @@ -5,6 +5,7 @@ * JZ4740 SoC RTC driver */ +#include #include #include #include @@ -41,6 +42,9 @@ #define JZ_RTC_CTRL_AE BIT(2) #define JZ_RTC_CTRL_ENABLE BIT(0) +#define JZ_RTC_REGULATOR_NC1HZ_MASK GENMASK(15, 0) +#define JZ_RTC_REGULATOR_ADJC_MASK GENMASK(25, 16) + /* Magic value to enable writes on jz4780 */ #define JZ_RTC_WENR_MAGIC 0xA55A @@ -61,6 +65,7 @@ struct jz4740_rtc { enum jz4740_rtc_type type; struct rtc_device *rtc; + struct clk *clk; struct clk_hw clk32k; @@ -217,12 +222,51 @@ static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable); } +static int jz4740_rtc_read_offset(struct device *dev, long *offset) +{ + struct jz4740_rtc *rtc = dev_get_drvdata(dev); + long rate = clk_get_rate(rtc->clk); + s32 nc1hz, adjc, offset1k; + u32 reg; + + reg = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_REGULATOR); + nc1hz = FIELD_GET(JZ_RTC_REGULATOR_NC1HZ_MASK, reg); + adjc = FIELD_GET(JZ_RTC_REGULATOR_ADJC_MASK, reg); + + offset1k = (nc1hz - rate + 1) * 1024L + adjc; + *offset = offset1k * 1000000L / (rate * 1024L); + + return 0; +} + +static int jz4740_rtc_set_offset(struct device *dev, long offset) +{ + struct jz4740_rtc *rtc = dev_get_drvdata(dev); + long rate = clk_get_rate(rtc->clk); + s32 offset1k, adjc, nc1hz; + + offset1k = div_s64_rem(offset * rate * 1024LL, 1000000LL, &adjc); + nc1hz = rate - 1 + offset1k / 1024L; + + if (adjc < 0) { + nc1hz--; + adjc += 1024; + } + + nc1hz = FIELD_PREP(JZ_RTC_REGULATOR_NC1HZ_MASK, nc1hz); + adjc = FIELD_PREP(JZ_RTC_REGULATOR_ADJC_MASK, adjc); + + return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, nc1hz | adjc); +} + static const struct rtc_class_ops jz4740_rtc_ops = { .read_time = jz4740_rtc_read_time, .set_time = jz4740_rtc_set_time, .read_alarm = jz4740_rtc_read_alarm, .set_alarm = jz4740_rtc_set_alarm, .alarm_irq_enable = jz4740_rtc_alarm_irq_enable, + .read_offset = jz4740_rtc_read_offset, + .set_offset = jz4740_rtc_set_offset, }; static irqreturn_t jz4740_rtc_irq(int irq, void *data) @@ -353,6 +397,7 @@ static int jz4740_rtc_probe(struct platform_device *pdev) spin_lock_init(&rtc->lock); + rtc->clk = clk; platform_set_drvdata(pdev, rtc); device_init_wakeup(dev, 1);