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Signed-off-by: Lad Prabhakar Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Tested-by: Conor Dooley # tyre-kicking on a d1 --- v9 -> v10 * Included TB tag from Conor v8 -> v9 * Included RB tag from Geert v7 -> v8 * No change v6 -> v7 * No change v5 -> v6 * No change v4 -> v5 * Included RB tags RFC v3 -> v4 * New patch --- arch/riscv/include/asm/vendorid_list.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index cb89af3f0704..e55407ace0c3 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -5,6 +5,7 @@ #ifndef ASM_VENDOR_LIST_H #define ASM_VENDOR_LIST_H +#define ANDESTECH_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 From patchwork Sun Jul 2 20:34:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 115152 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp135960vqx; Sun, 2 Jul 2023 13:43:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlGMwZRZYJJoyhqfjO9OX8bwLXDKZ1VCkEVEGa00ds/TtvwRMaXQCotfKTJkHEP0l53PDaQc X-Received: by 2002:a17:903:1385:b0:1b8:95fc:cfe with SMTP id jx5-20020a170903138500b001b895fc0cfemr1472473plb.3.1688330625627; Sun, 02 Jul 2023 13:43:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688330625; cv=none; d=google.com; s=arc-20160816; b=a6bH5x/B5dVhqoaoWV9j+NBUeKiBrceKX4VjeJxCzq2hXfd3OKAjq6MHFD2uxI1J51 TBq9O16ignMEt/P5mc+cT3BqVXExgj2iqScBUTtFg4MqYgn5pxX8ETCmkwcENYHcimDp p/ZCUyFKy52yNhL35REhOIYKc6dfKi9PSaA3xW+aVCpYu5Py1P5aral9GbFlwNB5NeKD z7z1g5JtRjxRLV2xw/AJ9DR4uYvtZ8ZSLcpT8WSvrixmK9+d4YXej93VbbqZBZpFmk20 h3MNQeaw/rsw1S590vpTuvu6VMlEAYtKbLW7WTug8lfKsjbQkxid6FdJAcx0kfvN+cyb vH6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bBA4mxMo21nxV3389WkUubCwMwiWrbVQrJuncENzqoM=; fh=ImlRZ5Wv1GG2NvepRpgcgxhgxwuio+u2pVZQ1x7Pk04=; b=RaiyQ+jrcwUA0RrSc7yR0FrfR+7JpEauxPkQWVM6/gkiD+Gaxqc/mupsttQXOCDtul SgVU+1D/GOxp/li/0y3YMyAqQpko6DpZerEiz/9zMUWzjWcOyd9WTuM/zuwnnpKQ4D66 Ki2raec8oLwhVdzg5TXNfsea+Vq2QI/HOQfEHDEGbMjAw4/L5nRQazhoQN1e2Wp/vVbg nyHXUTBFh81JR32x0Qt29Wu8Nndu2SC77yFFUs/RM2MZp45rJ7xh7iucjX9mNYxMMLtM eJy9iR6SKGm+qp5XDAxRhSBg0boTKlmt4R0r0eFgydO9JWixwz8JWlfUwzLS+/eNdGQl EgUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="h0K5X4E/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 --- v9 -> v10 * Included TB tag from Conor v8 -> v9 * Rebased to code on Palmer's for/next * Dropped calling patch_text_nosync() as dont use patch_text_nosync() call v7 -> v8 * Now patching the code using patch_text_nosync() and riscv_alternative_fix_offsets() v6 -> v7 * Renamed RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND -> ANDES_SBI_EXT_IOCP_SW_WORKAROUND * Dropped "depends on !XIP_KERNEL" for ERRATA_ANDES config v5 -> v6 * Dropped patching alternative and now just probing IOCP v4 -> v5 * Sorted the Kconfig/Makefile/Switch based on Core name * Added a comments * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if CMO needs to be applied. Is there a way we can access the DTB while patching as we can drop this SBI EXT ID and add a DT property instead for cmo? RFC v3 -> v4 * New patch --- arch/riscv/Kconfig.errata | 21 +++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 66 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/errata_list.h | 5 +++ arch/riscv/kernel/alternative.c | 5 +++ 7 files changed, 102 insertions(+) create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 0c8f4652cd82..92c779764b27 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -1,5 +1,26 @@ menu "CPU errata selection" +config ERRATA_ANDES + bool "Andes AX45MP errata" + depends on RISCV_ALTERNATIVE + help + All Andes errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all Andes errata. Please say "Y" + here if your platform uses Andes CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_ANDES_CMO + bool "Apply Andes cache management errata" + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043 + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on Andes cores. + + If you don't know what to do here, say "Y". + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index 7b2637c8c332..8a2739485123 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -2,5 +2,6 @@ ifdef CONFIG_RELOCATABLE KBUILD_CFLAGS += -fno-pie endif +obj-$(CONFIG_ERRATA_ANDES) += andes/ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/andes/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c new file mode 100644 index 000000000000..197db68cc8da --- /dev/null +++ b/arch/riscv/errata/andes/errata.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for Andes CPU cores + * + * Copyright (C) 2023 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL +#define ANDESTECH_AX45MP_MIMPID 0x500UL +#define ANDESTECH_SBI_EXT_ANDES 0x0900031E + +#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1 + +static long ax45mp_iocp_sw_workaround(void) +{ + struct sbiret ret; + + /* + * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and + * cache is controllable only then CMO will be applied to the platform. + */ + ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND, + 0, 0, 0, 0, 0, 0); + + return ret.error ? 0 : ret.value; +} + +static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) + return false; + + if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) + return false; + + if (!ax45mp_iocp_sw_workaround()) + return false; + + /* Set this just to make core cbo code happy */ + riscv_cbom_block_size = 1; + riscv_noncoherent_supported(); + + return true; +} + +void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + errata_probe_iocp(stage, archid, impid); + + /* we have nothing to patch here ATM so just return back */ +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 6a41537826a7..f6cfca939c92 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -46,6 +46,9 @@ struct alt_entry { u32 patch_id; /* The patch ID (erratum ID or cpufeature ID) */ }; +void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index fb1a810f3d8c..e2ecd01bfac7 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -11,6 +11,11 @@ #include #include +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDESTECH_NO_IOCP 0 +#define ERRATA_ANDESTECH_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_SIFIVE #define ERRATA_SIFIVE_CIP_453 0 #define ERRATA_SIFIVE_CIP_1200 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 6b75788c18e6..b0345992a35e 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -45,6 +45,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info cpu_mfr_info->feature_probe_func = NULL; switch (cpu_mfr_info->vendor_id) { +#ifdef CONFIG_ERRATA_ANDES + case ANDESTECH_VENDOR_ID: + cpu_mfr_info->patch_func = andes_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func = sifive_errata_patch_func; From patchwork Sun Jul 2 20:34:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 115151 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp135916vqx; Sun, 2 Jul 2023 13:43:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlGmiaETz5f6XgrDh4gl4cS/Mpr872yyzqPgArCslPy3fgvnibhevEJPAyfkSMs5Iqwqb8vz X-Received: by 2002:a17:902:ea0a:b0:1b8:35fa:cdcc with SMTP id s10-20020a170902ea0a00b001b835facdccmr9291033plg.5.1688330617844; Sun, 02 Jul 2023 13:43:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688330617; cv=none; d=google.com; s=arc-20160816; b=0JsLrUN2G4ULwfB0Ml1C3P4vHjqLBibwFJYFqOBJ0lMlvVpxPxzjqJVs/ZF1nopVHE zUFw6MmnjoJ8JpUd/PKTwfQC9uAZOqxKYxfcGzcW4OuImDlet8D3Xseta3c4bJXz//X5 yqRxk1P9arg/gnDmcbqVAQ7GcYrjx7Pl3PSeFBSKdus9NSywGW58G+oJPGrpj4OKDZ3+ iTe0tnYBRyXbeztpxvGAvGLMGODIyP51ACSGxlgx1wLI+XEZTTo9td3y8iAlZ+sRE8rw TOXoKO8mE3DD5Ks2ptQNYbcU0mfwwTBpUHfl7t14pOX/W8A5wBtEHCO7GDcLHGM3B2CN Af4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HcexdVQPBw2rdGBbBDTUXB1gr2v058VsgGzEZRfGeYk=; fh=ImlRZ5Wv1GG2NvepRpgcgxhgxwuio+u2pVZQ1x7Pk04=; b=qKEgI1s8AoXnr8SGWC5i80OrZmnFhBUE8GzYA4i+YwU6KXQ8Fpt8tsK8ZtO9nHWgQh l5TzBogJGrCwOMgD03rTb+noR50Yp7yWFW1t4L/2QrBwmogobYQ1viN2EIxeTDRhjPKC 8RH6CU8WdvVMFeEtWB9bjoQlgIi1CPpxsbDgvTkqzowlEc+iT3ZdHOJzGDUnxdLqC+so 5csK3v3+V7rqtHksr9L7kgCFn+AhOp74o+9KWMFxSzDp+1DGaaZpWlp8tGvSnsPkil5l Cjwc6Rx0qERXMhQ8xso1fVA/eEfNW6XlCv6VTtkuMkrV+/9Z7ZBt+/ixv5j47+kv70+F Scig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=W8dcPNYn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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It enables function pointer support to handle cache management in such systems. This patch adds a new configuration option called "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer support for cache management in nonstandard noncoherent systems. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 --- v9 -> v10 * Added __ro_after_init compiler attribute for noncoherent_cache_ops * Renamed clean -> wback * Renamed inval -> inv * Renamed flush -> wback_inv v8 -> v9 * New patch --- arch/riscv/Kconfig | 7 ++++ arch/riscv/include/asm/dma-noncoherent.h | 28 +++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 43 ++++++++++++++++++++++++ arch/riscv/mm/pmem.c | 13 +++++++ 4 files changed, 91 insertions(+) create mode 100644 arch/riscv/include/asm/dma-noncoherent.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d9e451ac862a..42c86b13c5e1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -265,6 +265,13 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP +config RISCV_NONSTANDARD_CACHE_OPS + bool + depends on RISCV_DMA_NONCOHERENT + help + This enables function pointer support for non-standard noncoherent + systems to handle cache management. + config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h new file mode 100644 index 000000000000..969cf1f1363a --- /dev/null +++ b/arch/riscv/include/asm/dma-noncoherent.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#ifndef __ASM_DMA_NONCOHERENT_H +#define __ASM_DMA_NONCOHERENT_H + +#include + +/* + * struct riscv_cache_ops - Structure for CMO function pointers + * + * @wback: Function pointer for cache writeback + * @inv: Function pointer for invalidating cache + * @wback_inv: Function pointer for flushing the cache (writeback + invalidating) + */ +struct riscv_cache_ops { + void (*wback)(phys_addr_t paddr, unsigned long size); + void (*inv)(phys_addr_t paddr, unsigned long size); + void (*wback_inv)(phys_addr_t paddr, unsigned long size); +}; + +extern struct riscv_cache_ops noncoherent_cache_ops; + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops); + +#endif /* __ASM_DMA_NONCOHERENT_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b9a9f57e02be..4c2e3f1cdfe6 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -9,13 +9,26 @@ #include #include #include +#include static bool noncoherent_supported; +struct riscv_cache_ops noncoherent_cache_ops __ro_after_init = { + .wback = NULL, + .inv = NULL, + .wback_inv = NULL, +}; + static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback)) { + noncoherent_cache_ops.wback(paddr, size); + return; + } +#endif ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); } @@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inv)) { + noncoherent_cache_ops.inv(paddr, size); + return; + } +#endif + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); } @@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { void *vaddr = phys_to_virt(paddr); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback_inv)) { + noncoherent_cache_ops.wback_inv(paddr, size); + return; + } +#endif + ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); } @@ -50,6 +77,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback_inv)) { + noncoherent_cache_ops.wback_inv(page_to_phys(page), size); + return; + } +#endif + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); } @@ -75,3 +109,12 @@ void riscv_noncoherent_supported(void) "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; } + +void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops) +{ + if (!ops) + return; + + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index 089df92ae876..c5fc5ec96f6d 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -7,15 +7,28 @@ #include #include +#include void arch_wb_cache_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.wback)) { + noncoherent_cache_ops.wback(virt_to_phys(addr), size); + return; + } +#endif ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); void arch_invalidate_pmem(void *addr, size_t size) { +#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS + if (unlikely(noncoherent_cache_ops.inv)) { + noncoherent_cache_ops.inv(virt_to_phys(addr), size); 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The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. The AX45MP core has an L2 cache controller, this patch describes the L2 cache block. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 --- v9 -> v10 * No Change v8 -> v9 * No Change v7 -> v8 * Updated commit header message v6 -> v7 * No Change v5 -> v6 * Included RB tag from Rob v4 -> v5 * Dropped L2 cache configuration properties * Dropped PMA configuration properties * Ordered the required list to match the properties list RFC v3 -> v4 * Dropped l2 cache configuration parameters * s/larger/large * Added minItems/maxItems for andestech,pma-regions --- .../cache/andestech,ax45mp-cache.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + }; From patchwork Sun Jul 2 20:34:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 115154 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp136647vqx; Sun, 2 Jul 2023 13:46:12 -0700 (PDT) X-Google-Smtp-Source: APBJJlGAaH2il7HJ45WKLMBe4fLxzKwGK6CPkvzrH2cgnJeWugLrnP89i/l5tcLpYRX/JlyrXWjP X-Received: by 2002:a17:902:f201:b0:1b8:811:b05a with SMTP id m1-20020a170902f20100b001b80811b05amr9328010plc.6.1688330772469; Sun, 02 Jul 2023 13:46:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688330772; cv=none; d=google.com; s=arc-20160816; b=u4Lu7aMSw+GULQUuRS+8br0XFEIaDLfbHh5x3s/eaL5nAOB5LNAV+QnVTI8kToI1z5 a0QTtz9v8IqigRvO12V5Mbx8HD5158t1cL6AclfD5m+ciTzcNCc4FEFe02QQ6KFbkkZI eOmhCbINNA6qI4/ElL9FWwDB0Lf2ycXJu1TjCm3oQpvk1Tt2jUk32YqT/Apc8Veclis8 VTOtO4DbRLO7VrwWjKxrIUParDoLU6x5CsN70FBqahJDrNRYl9qQ5IqxvOa0mrDpWHqc x7B6iv4ryud1MNOkDiPEioxZonby0ehHRkXEhhy/i/O4tJLRvNWNAECrbNOYd/yRCuWF p9cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zJjSJrFD46rql5SQeLkNxGE/SD7DDj1gOMvfywUg8kE=; fh=ImlRZ5Wv1GG2NvepRpgcgxhgxwuio+u2pVZQ1x7Pk04=; b=YGgr3wsWUygpF7bmUkEiVOScSyQJuasXJs2eG6ojzlWnqoobOWmHUM6XVsAkeQeobL 0bOAyGnPXZIfh31kYBMeA8xtkC30JE4u8rPhApOCnVLwjqsCAW3ls0g20F2Fv9A7Sibi SmTP85jnrlZ55KQU7/GFR1w4RRefIh4pAiXBi5f7BTOvI1LXB143KunlQJJVcdJk/CF4 BNDuO98c6iarA33o6EY8h3hxGgsGSFD5XErlquC9v+m6R7CVVXl3uyoB6Z4iq4tjvszV 5c77nr786DkSCtjjt9h9a5h1loAtL11jzABqfTMcaQjEIn9PW2jONG/NwdizjhyzDL/p hn6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=DKYNThji; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Tested-by: Conor Dooley # tyre-kicking on a d1 --- v8 -> v9 * Updated function pointers v8 -> v9 * Dropped exporting CMO functions as we no more used ALTERNATIVE_X() macro * Now using the riscv_noncoherent_register_cache_ops() for registering CMO ops * Added RB tag from Conor v7 -> v8 * Dropped function pointer usage * Now exporting the functions for clean/inval/flush * Switched to using early_initcall instead of arch_initcall * Dropped entry for "include/cache" from MAINTAINERS * Dropped dependency of RISCV on AX45MP_L2_CACHE * Returning error in case of cache line mismatch * Renamed clean/inval/flush functions v6 -> v7 * Implemented flush callback * Dropped using riscv_dma_noncoherent_cmo_ops v5 -> v6 * Moved driver to cache folder * Switched to new API for CMO v4 -> v5 * Dropped code for configuring L2 cache * Dropped code for configuring PMA * Updated commit message * Added comments * Changed static branch enable/disable order RFC v3 -> v4 * Made use of runtime patching instead of compile time * Now just exposing single function ax45mp_no_iocp_cmo() for CMO handling * Added a check to make sure cache line size is always 64 bytes * Renamed folder rzf -> rzfive * Improved Kconfig description * Dropped L2 cache configuration * Dropped unnecessary casts * Fixed comments pointed by Geert. --- MAINTAINERS | 7 ++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 11 ++ drivers/cache/Makefile | 3 + drivers/cache/ax45mp_cache.c | 213 +++++++++++++++++++++++++++++++++++ 6 files changed, 237 insertions(+) create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c diff --git a/MAINTAINERS b/MAINTAINERS index 55ac73793856..899452038a5b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20073,6 +20073,13 @@ S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git F: drivers/staging/ +STANDALONE CACHE CONTROLLER DRIVERS +M: Conor Dooley +L: linux-riscv@lists.infradead.org +S: Maintained +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: drivers/cache + STARFIRE/DURALAN NETWORK DRIVER M: Ion Badulescu S: Odd Fixes diff --git a/drivers/Kconfig b/drivers/Kconfig index 514ae6b24cb2..2ae1b6707c2c 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -15,6 +15,8 @@ source "drivers/base/Kconfig" source "drivers/bus/Kconfig" +source "drivers/cache/Kconfig" + source "drivers/connector/Kconfig" source "drivers/firmware/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 7241d80a7b29..23eb201fe18a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -11,6 +11,7 @@ ifdef building_out_of_srctree MAKEFLAGS += --include-dir=$(srctree) endif +obj-y += cache/ obj-y += irqchip/ obj-y += bus/ diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig new file mode 100644 index 000000000000..a57677f908f3 --- /dev/null +++ b/drivers/cache/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +menu "Cache Drivers" + +config AX45MP_L2_CACHE + bool "Andes Technology AX45MP L2 Cache controller" + depends on RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + help + Support for the L2 cache controller on Andes Technology AX45MP platforms. + +endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile new file mode 100644 index 000000000000..2012e7fb978d --- /dev/null +++ b/drivers/cache/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c new file mode 100644 index 000000000000..863bf0bfef98 --- /dev/null +++ b/drivers/cache/ax45mp_cache.c @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * non-coherent cache functions for Andes AX45MP + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +#include + +/* L2 cache registers */ +#define AX45MP_L2C_REG_CTL_OFFSET 0x8 + +#define AX45MP_L2C_REG_C0_CMD_OFFSET 0x40 +#define AX45MP_L2C_REG_C0_ACC_OFFSET 0x48 +#define AX45MP_L2C_REG_STATUS_OFFSET 0x80 + +/* D-cache operation */ +#define AX45MP_CCTL_L1D_VA_INVAL 0 /* Invalidate an L1 cache entry */ +#define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */ + +/* L2 CCTL status */ +#define AX45MP_CCTL_L2_STATUS_IDLE 0 + +/* L2 CCTL status cores mask */ +#define AX45MP_CCTL_L2_STATUS_C0_MASK 0xf + +/* L2 cache operation */ +#define AX45MP_CCTL_L2_PA_INVAL 0x8 /* Invalidate an L2 cache entry */ +#define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */ + +#define AX45MP_L2C_REG_PER_CORE_OFFSET 0x10 +#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET 4 + +#define AX45MP_L2C_REG_CN_CMD_OFFSET(n) \ + (AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_L2C_REG_CN_ACC_OFFSET(n) \ + (AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET)) +#define AX45MP_CCTL_L2_STATUS_CN_MASK(n) \ + (AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET)) + +#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM 0x80b +#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM 0x80c + +#define AX45MP_CACHE_LINE_SIZE 64 + +struct ax45mp_priv { + void __iomem *l2c_base; + u32 ax45mp_cache_line_size; +}; + +static struct ax45mp_priv ax45mp_priv; + +/* L2 Cache operations */ +static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void) +{ + return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET); +} + +static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end, + unsigned int l1_op, unsigned int l2_op) +{ + unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size; + void __iomem *base = ax45mp_priv.l2c_base; + int mhartid = smp_processor_id(); + unsigned long pa; + + while (end > start) { + csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start); + csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op); + + pa = virt_to_phys((void *)start); + writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid)); + writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid)); + while ((ax45mp_cpu_l2c_get_cctl_status() & + AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) != + AX45MP_CCTL_L2_STATUS_IDLE) + ; + + start += line_size; + } +} + +/* Write-back L1 and L2 cache entry */ +static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end) +{ + ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB, + AX45MP_CCTL_L2_PA_WB); +} + +/* Invalidate the L1 and L2 cache entry */ +static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end) +{ + ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL, + AX45MP_CCTL_L2_PA_INVAL); +} + +static void ax45mp_dma_cache_inv(phys_addr_t paddr, unsigned long size) +{ + unsigned long start = (unsigned long)phys_to_virt(paddr); + unsigned long end = start + size; + unsigned long line_size; + unsigned long flags; + + if (unlikely(start == end)) + return; + + line_size = ax45mp_priv.ax45mp_cache_line_size; + + start = start & (~(line_size - 1)); + end = ((end + line_size - 1) & (~(line_size - 1))); + + local_irq_save(flags); + + ax45mp_cpu_dcache_inval_range(start, end); + + local_irq_restore(flags); +} + +static void ax45mp_dma_cache_wback(phys_addr_t paddr, unsigned long size) +{ + unsigned long start = (unsigned long)phys_to_virt(paddr); + unsigned long end = start + size; + unsigned long line_size; + unsigned long flags; + + line_size = ax45mp_priv.ax45mp_cache_line_size; + start = start & (~(line_size - 1)); + local_irq_save(flags); + ax45mp_cpu_dcache_wb_range(start, end); + local_irq_restore(flags); +} + +static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size) +{ + ax45mp_dma_cache_wback(paddr, size); + ax45mp_dma_cache_inv(paddr, size); +} + +static int ax45mp_get_l2_line_size(struct device_node *np) +{ + int ret; + + ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size); + if (ret) { + pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n"); + return ret; + } + + if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) { + pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n", + ax45mp_priv.ax45mp_cache_line_size); + return -EINVAL; + } + + return 0; +} + +static const struct riscv_cache_ops ax45mp_cmo_ops = { + .wback = &ax45mp_dma_cache_wback, + .inv = &ax45mp_dma_cache_inv, + .wback_inv = &ax45mp_dma_cache_wback_inv, +}; + +static const struct of_device_id ax45mp_cache_ids[] = { + { .compatible = "andestech,ax45mp-cache" }, + { /* sentinel */ } +}; + +static int __init ax45mp_cache_init(void) +{ + struct device_node *np; + struct resource res; + int ret; + + np = of_find_matching_node(NULL, ax45mp_cache_ids); + if (!of_device_is_available(np)) + return -ENODEV; + + ret = of_address_to_resource(np, 0, &res); + if (ret) + return ret; + + /* + * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size + * will be 0 for sure, so we can definitely rely on it. If + * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any + * more so we just return success here and only if its being set we + * continue further in the probe path. + */ + if (!riscv_cbom_block_size) + return 0; + + ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res)); + if (!ax45mp_priv.l2c_base) + return -ENOMEM; + + ret = ax45mp_get_l2_line_size(np); + if (ret) { + iounmap(ax45mp_priv.l2c_base); + return ret; + } + + riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops); + + return 0; +} +early_initcall(ax45mp_cache_init); From patchwork Sun Jul 2 20:34:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 115155 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f45:0:b0:3ea:f831:8777 with SMTP id v5csp141854vqx; Sun, 2 Jul 2023 14:02:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGmKAEJRDOun8Ibs/OQdnRSVfTJrWkFXpaQ0WuEiA/vpOTvPpB5J625Gjy6X1BXg6/aULjH X-Received: by 2002:a17:902:e294:b0:1af:adc2:ab5b with SMTP id o20-20020a170902e29400b001afadc2ab5bmr9420324plc.0.1688331755112; Sun, 02 Jul 2023 14:02:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688331755; cv=none; d=google.com; s=arc-20160816; b=N0nLxxxrP+ms+PN+I5ZgVkhogKlL8ChIjlk9bEwTa5YTCLbpNRWbVjG39tMKBCV07q E+9syi/sZDfeDMTypnG7u0P8e7IaWJkydBhjciMZhSaxKyDQSOIevNz5N/H2gDsJ4Fig dD8ElQXDXuidxssSO/Cw/t1npQ7ySr5Svi95b4Rpto47T9W+JxktbxDe7jz8TCU1A0hN 4R0M95Dmc5d/KldBQy4Dd2S0et/Vw6ioaN14j7Ib7AborarzhHbBVFx9doolu55AkXkY m40Vj28yW5rYRIaEKZJhbifIJkEZlieQKWqD1mgbd0HdaDPQ2h0/gCHV+SqXnpmVJBRt NtVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Urzo+tFsGAkOnz5ecpB6iDl1xPRU1BRxrnQ2HFHQvFc=; fh=ImlRZ5Wv1GG2NvepRpgcgxhgxwuio+u2pVZQ1x7Pk04=; b=LHpy/QfpUwKA9QvLI9kwnlxxpfbabBgulEwf6nbiFrP9x/bXxjB3fC98X7F6tWz0SH QPFsFUy7ENUWoNPhchOHm5UheFy+elUAa9WlMIl6CPcMwI7NGXRZcYjC+KizpKCBI1iN EWBE+4FttcFSUJuESvOU3aQs0TBUYgYMkbYj375liuxqGsThl9zoVeTvkLmMIQIrHj7h 1Rik8IE634D8Q7x4VIXPKzW/XCVGBQtJig3HjJ5aLAoPSZZlRltoGfV/+CBNtk08EV/A pOnz45neBmin8sDrHehIrrMPsx6cImEVDduzz9bXTFTCqMFi6ex/+QAy7wm6k4zGs6s6 4oWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=JzpxMDAE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Tested-by: Conor Dooley # tyre-kicking on a d1 --- v9 -> v10 * No change v8 -> v9 * No change v7 -> v8 * Included RB tag from Geert v6 -> v7 * Included RB tag from Conor v5 -> v6 * New patch --- drivers/soc/renesas/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index de31589ed054..67604f24973e 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,10 @@ if RISCV config ARCH_R9A07G043 bool "RISC-V Platform support for RZ/Five" select ARCH_RZG2L + select AX45MP_L2_CACHE + select DMA_GLOBAL_POOL + select ERRATA_ANDES + select ERRATA_ANDES_CMO help This enables support for the Renesas RZ/Five SoC.