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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bm4-20020a056a00320400b0067bb1f0b329si7058194pfb.93.2023.06.30.05.41.13; Fri, 30 Jun 2023 05:41:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=XyNzagDV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232970AbjF3MGf (ORCPT + 99 others); Fri, 30 Jun 2023 08:06:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233017AbjF3MGF (ORCPT ); Fri, 30 Jun 2023 08:06:05 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23A4B3C32; Fri, 30 Jun 2023 05:05:26 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f95bf5c493so2759630e87.3; Fri, 30 Jun 2023 05:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688126717; x=1690718717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=samC88JToQJggQkwPP9LLv4m1XMmLyVNduLSuH7L0a8=; b=XyNzagDVD/naZSkDvfGdbA70OJsmTZFqdPh6Nr9bijz7op3b4yt7JA0T3D/rRXD502 wAU1ZaPGpySUwosUCRSsBnpOZgiYN4rhWT1+w86IJxdIp4gIB8M04P5PMMtKPSJvpaqc rwRcM5SJ9bxpGGT8i0p2CU5LD+Fo/8dtlJBvUg0GJkYCMKV2Xx7YlUS9UePYChEl0Osm jGEn8JhZOCyDvfrK/6gxaDBUsD4ZhpSTxfUxc/htYHT5XZxHrmwOeNGQOjt1v/LQzc5N Cyx879x3kG2mDMLfVhu5TCh27NOXot+r5P7eHogD9ukPSwwLLRoVIZYeX/XD2an+1f0Y rHYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688126717; x=1690718717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=samC88JToQJggQkwPP9LLv4m1XMmLyVNduLSuH7L0a8=; b=KyE6iUxxRixHn1aaBa+i1Pe4FRMwZXaQzJgYPL41VIEgn8ECDF3JIPKf9NknWqtUk6 jGeFI2h7Oxep1mxi6k9rAyn9719cak4JQ7pyrBzW8bPv7hwDZV9UfyxAujnnpM8/PXuB VtH2M5x6nvyx8Y/K763yxtVjmxwbxQX6YhfftfHl662Ex7cnJz9rSnCu3BcXJRG9i2Ec W7xjljB0GjxEx+nWcLGf0UtwpSMD298QgScq+wnoOrmNE8/F7CWpjB7tkjU8tBqAI9wW +y/yaFFSjCQzN4enu6b4OJaBKhqTlN85DsDj+iRmc58EqMtMu2BYKKtNRAcvvG6V/vV8 MYQg== X-Gm-Message-State: ABy/qLatJpTEmpAHvadEz3iOVIPBIuAi5a6jY60FVtyOMv7vhPLW5R/1 CeyYqREE61hMGjE7B+ovTaM= X-Received: by 2002:a19:675a:0:b0:4f8:6d99:f4f3 with SMTP id e26-20020a19675a000000b004f86d99f4f3mr1919162lfj.52.1688126717020; Fri, 30 Jun 2023 05:05:17 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:dbbb:7082:18ec:f407]) by smtp.gmail.com with ESMTPSA id k22-20020a05600c0b5600b003fb40f5f553sm11766912wmr.31.2023.06.30.05.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 05:05:16 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Date: Fri, 30 Jun 2023 13:04:30 +0100 Message-Id: <20230630120433.49529-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770131434338676354?= X-GMAIL-MSGID: =?utf-8?q?1770131434338676354?= From: Lad Prabhakar Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. With this we also get additional pin validation, for example on the RZ/G2L SOC P0 has two pins P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7. While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to validate the gpio pin. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------ 1 file changed, 86 insertions(+), 81 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 9511d920565e..a0c2e585e765 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -67,10 +67,12 @@ PIN_CFG_FILCLKSEL) /* - * n indicates number of pins in the port, a is the register index - * and f is pin configuration capabilities supported. + * m indicates the bitmap of supported pins, n indicates number + * of pins in the port, a is the register index and f is pin + * configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28) | ((a) << 20) | (f)) +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32) #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) @@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs { struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -445,13 +447,16 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); - u32 data; + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg); + u64 data; - if (bit >= pincount || port >= pctrl->data->n_port_pins) + if (port >= pctrl->data->n_port_pins) + return -EINVAL; + + if (!(pinmap & BIT(bit))) return -EINVAL; data = pctrl->data->port_pin_configs[port]; @@ -501,7 +506,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; unsigned int arg = 0; unsigned long flags; void __iomem *addr; @@ -591,7 +596,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, { struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; enum pin_config_param param; unsigned long flags; void __iomem *addr; @@ -965,78 +970,78 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 rzg2l_gpio_configs[] = { - RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), +static const u64 rzg2l_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x11, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x12, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x13, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x14, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x17, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x18, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x19, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x23, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x36, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x37, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x38, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x39, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x3a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a07g043_gpio_configs[] = { - RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), - RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +static const u64 r9a07g043_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; static struct { @@ -1396,7 +1401,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) { struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; pctrl->desc.name = DRV_NAME; From patchwork Fri Jun 30 12:04:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 114702 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp10314741vqr; Fri, 30 Jun 2023 05:17:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlE4fYED10h512TCvUQTze1GfnxVt+Yo6LcgmiQbDsZQII8JdMZnSZABddQNz4DCak3F+J6p X-Received: by 2002:a17:902:c94d:b0:1b2:4852:9a5f with SMTP id i13-20020a170902c94d00b001b248529a5fmr1652231pla.54.1688127453067; Fri, 30 Jun 2023 05:17:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688127453; cv=none; d=google.com; s=arc-20160816; b=KPeoYZvAD9Z9zcoylZJKdPZjk12EzzuzyhiU5inop8JVfOmeaKskTiGnoztc9fHpRP oiJgH5PA9sEy4KPaTQWmJIACykpY9ZRVHp7UBTQu3xF/DoLmqGqrC3X1Gs6CT0OnddsO ugcm2IyPBy+/cO5w1gdOGswyuD4pkZDjN4Tp6/AFfVTbFdq3xtH+GTy+rkQAoHBH74it QGHoQBE1mp459OwFX6e2sWzAbppU5fzwZg8LdP7c1lrQKRS8aAgjrkW+a28D/EqasMAb u8ZJGcNVQjTcvDxb1Otz1DZ7Pk6Lt//U/zQn07yNZAA4Ply7bqnMudnJ0n5ypScMFXlW NSqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/M+822NMBcWFhtW8psDduBe6caBnlnfKm7WRYzHuukU=; fh=punYVBkjAbr65jYL2GuvUngXdSB2Eb1DCYORMK3W2vY=; b=Xullu5Bw3UTIwVSblBqj58xxx+PYcCjhgDiuUaQoMeprx8V2M8NCpQDYelcI50nqbx fXN6qJaKxYVYCFM156CeB6f3QydXuxQJca/tB3gH4Vm/jfpv6OP/HYVaQnQi4bwmbgVm GRS4COThSFnQTIkjfJLZUcW9O4MzrCLHfAwGikZvIuVGOE4kRgAqdLckRMuj0FEfnqYm eeVekfBOjkZzug+D4IJ/1H4zd0c8lPoytKQA/5l/u1yAwzz9dV+JMRFySRPkqEP1DzEB BMlLQtD/43m9vPr1XdGBY1J7fnRtK/38vk2Dyf5X0QiKR4Bl95MugylpR6K8bd1okW8a XqzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b=rLdjIQN7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a0c2e585e765..2fc1b880db0c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -780,12 +780,18 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = { static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[offset]; + u64 *pin_data = pin->drv_data; u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; u8 reg8; int ret; + ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); + if (ret) + return ret; + ret = pinctrl_gpio_request(chip->base + offset); if (ret) return ret; From patchwork Fri Jun 30 12:04:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 114703 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp10322438vqr; Fri, 30 Jun 2023 05:30:19 -0700 (PDT) X-Google-Smtp-Source: APBJJlFxs5css7UKV5K7R/Mfsx44J+AsdJhKHc3bFGGlKS37eACUQ83lSGPxHdGTGSH3smA2AJDp X-Received: by 2002:a92:c6c9:0:b0:345:7c28:1edf with SMTP id v9-20020a92c6c9000000b003457c281edfmr2068049ilm.32.1688128218645; Fri, 30 Jun 2023 05:30:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688128218; cv=none; d=google.com; s=arc-20160816; b=qTsC+2CW6GlXv2iMvGyRpiL62cPJm5j81H0zelwTDPjfcTiusPoXXs49c6ZI2nv6A5 i18GSbTPLcKMT+61bMGRUiHweuPFJDrGsbJzlLAduuAUdwvW9QXiRPPXrcxbLeyJnF2e j5NWyCuZrWdBepeyxJr7u6EQZVTYejp6Ojqyats57nQN65EgVU0YtW5IrPlqoo1iQKmq cjI2ZeqOua0yXBbYxUDI9vnErsb1Gl1NZFDyVqYV/uKFKzfKsC8JJczfcmYB7NjBgeV5 Tun6UWik3QmogqHIwFszcHCmG3/niNhu6CjtXtoTRpzchcp1Q3iD1NjUm7HpvTN5QmRz h2fA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PAapxjBD/rwbhfxji86yGKwLK1ac+lCSTHoejUz0sCA=; fh=punYVBkjAbr65jYL2GuvUngXdSB2Eb1DCYORMK3W2vY=; b=D1M90UoUeiRTOQC4eDrwmWlPaTzmVnsR4LXBlmVPfPXq1FWr1sO5MTMOKPq6y+l6dO obzKKYiL6GE0KEvBhzENOKjaF4A7kPbUCUhU+T7OgAt8grQ7lOPI2rYGEYn8YUt+Qz3O gbR30xnzU/me1jk1wnEtnwJUl7MjcbsUoSx30NU/M2hebP/tMK9Jo651QbGL8qp9QGyr +dcRx2zqCJqTRWadBjvJODDhMgxhjvMuOrJlUJ0nHf2IdapNYjClWRYV997G4cSCfiyc cSbeO53y4puFa1eoW4nuQQaBYUyOVVac3FhDgQWxLnCwFGHq3Xxxeycj3WPluOILl2pS Q2AA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="G2hm/3wb"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w29-20020a63161d000000b00557a26e5fefsi11284498pgl.684.2023.06.30.05.30.04; Fri, 30 Jun 2023 05:30:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20221208 header.b="G2hm/3wb"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232710AbjF3MGm (ORCPT + 99 others); Fri, 30 Jun 2023 08:06:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233089AbjF3MGG (ORCPT ); Fri, 30 Jun 2023 08:06:06 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0575B3C3F; Fri, 30 Jun 2023 05:05:27 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3fbc59de009so9243905e9.3; Fri, 30 Jun 2023 05:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688126719; x=1690718719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PAapxjBD/rwbhfxji86yGKwLK1ac+lCSTHoejUz0sCA=; b=G2hm/3wbHT0wdTRF7Ea5NM+45CGLivRnJb/bhiN7YvbTVDF6UKc1ItVDMFUINx75gj /4/FFdJ8sMckmZ3wphiO+3xKSY8GI6DQ0OBoJPGssSpp6uyKdES9t8GxQOfK3slypcic FaHedPYgaQhhq6u2gqDBTdOhs0ttIBxACyB/ycGLjM9V2P7AlUPzUo/iCHiOD8JcP478 7TDRQ3UBbkZ5BR3m764DM09VzhG84IPlactzdrqz2HlhmLNR+szB3mLasJLZLnyPKFqj TwDwSNSvLW1XQrxiOGIc9iUppvbsphFiShxlKpvtH08Rw0nf3uitJnn2/7bWGv71QAd/ XxTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688126719; x=1690718719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PAapxjBD/rwbhfxji86yGKwLK1ac+lCSTHoejUz0sCA=; b=hdrOumT2+IiMZcxVKe3/Q0HZ7s+LjuBktmr44ddkPBDmc2C+lkKzc1G4nADdW7CM2R MBriTq1WK1tIUEi+8MiPm+0ufmhnilRS6QCknx5HyLoRjb39EHRrk6SDExZqo6lxqDQH PUo+Z40UAhix0SoevLUKgkAzZV8tAU4CdD+5rfmuYUh0AxH9Kgl80VH0vAZXkOZ27oiJ lJBgvfDixvSIpD0HwmCxcwiXuX0RhHnkP9I+g2vn+nPcml3M5QTMbGnxDfrNjq110qeZ mpKqJU0uN0oNkUpVvhcOegnuyWUPe7+vZIEO0pmwfzV8tRQm268okX0EaxiEJed06GFk GJHw== X-Gm-Message-State: AC+VfDx7SqBLaFkw4vDBG8jT3fHBxmqWUD2RADOy74Lf/88id/FaZ7uJ hIPpleuViDpWjzywXIB270Cp7TGXTeIlyQ== X-Received: by 2002:a05:600c:2902:b0:3fb:739d:27b2 with SMTP id i2-20020a05600c290200b003fb739d27b2mr1807622wmd.8.1688126719204; Fri, 30 Jun 2023 05:05:19 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:dbbb:7082:18ec:f407]) by smtp.gmail.com with ESMTPSA id k22-20020a05600c0b5600b003fb40f5f553sm11766912wmr.31.2023.06.30.05.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 05:05:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Linus Walleij , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Date: Fri, 30 Jun 2023 13:04:32 +0100 Message-Id: <20230630120433.49529-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230630120433.49529-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770130734480995391?= X-GMAIL-MSGID: =?utf-8?q?1770130734480995391?= From: Lad Prabhakar Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Furthermore, a new variant called r9a07g043_data has been introduced specifically for the RZ/Five SoC. When CONFIG_RISCV is enabled, this variant replaces the previous data configuration. Additionally, a new macro named PIN_CFG_NOGPIO has been implemented. This macro serves as an indicator to determine whether the port pins can be utilized as GPIO pins. Signed-off-by: Lad Prabhakar --- Please note that I have only included the necessary changes for PFC settings in this paragraph. However, further work is required to set the attributes of the pin. While we already have generic properties in place for most of the attributes, setting the ISEL attribute for those pins may require a specific property unique to Renesas. Alternatively, is there a possibility of addressing this requirement in a different manner? --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 94 +++++++++++++++++++++---- 1 file changed, 82 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 2fc1b880db0c..61004733c2eb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -53,6 +54,7 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_NOGPIO BIT(13) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -101,6 +103,12 @@ #define SD_CH(n) (0x3000 + (n) * 4) #define QSPI (0x3008) +#define RZFIVE_P_EX(n) (0x0000 + 0x06 + ((n) - 19)) +#define RZFIVE_PM_EX(n) (0x0100 + 0x0c + ((n) - 19) * 2) +#define RZFIVE_PMC_EX(n) (0x0200 + 0x06 + ((n) - 19)) +#define RZFIVE_PFC_EX(n) (0x0400 + 0x18 + ((n) - 19) * 4) +#define RZFIVE_PIN_EX(n) (0x0800 + 0x06 + ((n) - 19)) + #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ @@ -160,39 +168,53 @@ struct rzg2l_pinctrl { static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; +static const struct soc_device_attribute rzfive_match[] = { + { .family = "RZ/Five" }, + { /* sentinel */} +}; + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 port, u8 pin, u8 func) { + u32 pm_offset = PM(port); + u32 pmc_offset = PMC(port); + u32 pfc_offset = PFC(port); unsigned long flags; u32 reg; + if (soc_device_match(rzfive_match) && port > 18) { + pm_offset = RZFIVE_PM_EX(port); + pmc_offset = RZFIVE_PMC_EX(port); + pfc_offset = RZFIVE_PFC_EX(port); + } + spin_lock_irqsave(&pctrl->lock, flags); /* Set pin to 'Non-use (Hi-Z input protection)' */ - reg = readw(pctrl->base + PM(port)); + reg = readw(pctrl->base + pm_offset); reg &= ~(PM_MASK << (pin * 2)); - writew(reg, pctrl->base + PM(port)); + writew(reg, pctrl->base + pm_offset); /* Temporarily switch to GPIO mode with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + pmc_offset); + writeb(reg & ~BIT(pin), pctrl->base + pmc_offset); /* Set the PWPR register to allow PFC register to write */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ /* Select Pin function mode with PFC register */ - reg = readl(pctrl->base + PFC(port)); + reg = readl(pctrl->base + pfc_offset); reg &= ~(PFC_MASK << (pin * 4)); - writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); + writel(reg | (func << (pin * 4)), pctrl->base + pfc_offset); /* Set the PWPR register to be write-protected */ writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ /* Switch to Peripheral pin function with PMC register */ - reg = readb(pctrl->base + PMC(port)); - writeb(reg | BIT(pin), pctrl->base + PMC(port)); + reg = readb(pctrl->base + pmc_offset); + writeb(reg | BIT(pin), pctrl->base + pmc_offset); spin_unlock_irqrestore(&pctrl->lock, flags); }; @@ -447,12 +469,15 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u64 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit, bool pfc) { u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg); u64 data; + if (!pfc && (cfg & PIN_CFG_NOGPIO)) + return -EINVAL; + if (port >= pctrl->data->n_port_pins) return -EINVAL; @@ -526,7 +551,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); - if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) + if (rzg2l_validate_gpio_pin(pctrl, *pin_data, + RZG2L_PIN_ID_TO_PORT(_pin), bit, true)) return -EINVAL; } @@ -617,7 +643,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); bit = RZG2L_PIN_ID_TO_PIN(_pin); - if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) + if (rzg2l_validate_gpio_pin(pctrl, *pin_data, + RZG2L_PIN_ID_TO_PORT(_pin), bit, true)) return -EINVAL; } @@ -788,7 +815,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) u8 reg8; int ret; - ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); + ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit, false); if (ret) return ret; @@ -1050,6 +1077,38 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; +static const u64 r9a07g043f_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x06, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO), + RZG2L_GPIO_PORT_PACK(0xff, 8, 0x07, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO), + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x08, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)), + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x09, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)), + RZG2L_GPIO_PORT_PACK(0x3e, 5, 0x0a, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0b, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO), + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x0c, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO), + RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0d, 0x0), + RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0e, 0x0), + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO), +}; + static struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; @@ -1534,6 +1593,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) return 0; } +#ifdef CONFIG_RISCV +static struct rzg2l_pinctrl_data r9a07g043_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = r9a07g043f_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g043f_gpio_configs), + .dedicated_pins = rzg2l_dedicated_pins.common, + .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), +}; +#else static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, @@ -1542,6 +1611,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), }; +#endif static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, From patchwork Fri Jun 30 12:04:33 2023 Content-Type: text/plain; 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Signed-off-by: Lad Prabhakar --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index b0796015e36b..e68a91c9fe77 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>;