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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p38-20020a634f66000000b0053fd39c7f6csi11815538pgl.646.2023.06.29.23.37.34; Thu, 29 Jun 2023 23:37:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=hyZowN5q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232173AbjF3G3I (ORCPT + 99 others); Fri, 30 Jun 2023 02:29:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232113AbjF3G3E (ORCPT ); Fri, 30 Jun 2023 02:29:04 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 371272D63; Thu, 29 Jun 2023 23:29:03 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35U2ohTq000994; Thu, 29 Jun 2023 23:28:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=7Sn/Y+AbUWE7dkM+A9+BIA9m6WqrGPdGyljUWLW3b+4=; b=hyZowN5qbBCxmtnErzTRsNyzahCyeUh6KDPzI0NPW5QyaT9+rPsZTXmjYzGhlWIDEGLY iH6TrjQ6+veRpVNl8cRy4p4D0dkuU7GCk7YeLR3ivFxjSCbugdASAVseoxrvK0jObaJu f9xTLt65K6Yf83PqVAPE0olsXv424/2JyQyFzGABeYy5mqyqmayF63tpSQZkk9Ny/H4u jQ5Y65XwBgpw0/7HA9Kycm7s8w3fvM20Z4TKULdc+PwRl7qHYKe/A2bk4caGAK5BfVdn ODvZ8SArFx24vA8gGDqMfGq8MK5oXCVz1XDPD49dGf/rfJSw/e2a8NHDHWAVlu+KsTma 5g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3rgvpc58rm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Jun 2023 23:28:55 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 29 Jun 2023 23:28:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 29 Jun 2023 23:28:53 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 83ACE3F707D; Thu, 29 Jun 2023 23:28:49 -0700 (PDT) From: Hariprasad Kelam To: , CC: , , , , , , , , Subject: [net Patch 1/4] octeontx2-af: cn10kb: fix interrupt csr addresses Date: Fri, 30 Jun 2023 11:58:42 +0530 Message-ID: <20230630062845.26606-2-hkelam@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230630062845.26606-1-hkelam@marvell.com> References: <20230630062845.26606-1-hkelam@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: mA6qFLl_vVdoBXgilk0OvOYgoaz0j_mE X-Proofpoint-ORIG-GUID: mA6qFLl_vVdoBXgilk0OvOYgoaz0j_mE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-30_03,2023-06-27_01,2023-05-22_02 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770108558110011822?= X-GMAIL-MSGID: =?utf-8?q?1770108558110011822?= The current design is that, for asynchronous events like link_up and link_down firmware raises the interrupt to kernel. The previous patch which added RPM_USX driver has a bug where it uses old csr addresses for configuring interrupts. Which is resulting in losing interrupts from source firmware. This patch fixes the issue by correcting csr addresses. Fixes: b9d0fedc6234 ("octeontx2-af: cn10kb: Add RPM_USX MAC support") Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham Reviewed-by: Simon Horman --- drivers/net/ethernet/marvell/octeontx2/af/rpm.c | 2 +- drivers/net/ethernet/marvell/octeontx2/af/rpm.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c index de0d88dd10d6..a433f92c51ea 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c @@ -47,7 +47,7 @@ static struct mac_ops rpm2_mac_ops = { .int_set_reg = RPM2_CMRX_SW_INT_ENA_W1S, .irq_offset = 1, .int_ena_bit = BIT_ULL(0), - .lmac_fwi = RPM_LMAC_FWI, + .lmac_fwi = RPM2_LMAC_FWI, .non_contiguous_serdes_lane = true, .rx_stats_cnt = 43, .tx_stats_cnt = 34, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h index 22147b4c2137..be294eebab26 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h @@ -94,7 +94,8 @@ /* CN10KB CSR Declaration */ #define RPM2_CMRX_SW_INT 0x1b0 -#define RPM2_CMRX_SW_INT_ENA_W1S 0x1b8 +#define RPM2_CMRX_SW_INT_ENA_W1S 0x1c8 +#define RPM2_LMAC_FWI 0x12 #define RPM2_CMR_CHAN_MSK_OR 0x3120 #define RPM2_CMR_RX_OVR_BP_EN BIT_ULL(2) #define RPM2_CMR_RX_OVR_BP_BP BIT_ULL(1) From patchwork Fri Jun 30 06:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hariprasad Kelam X-Patchwork-Id: 114586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp10142959vqr; Thu, 29 Jun 2023 23:30:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Qe+WIYIddYj3hOr8u0UfmbN9/BbUygPlqPcSbmGtoZ3eiLqtwAiah/mzD4tiOzoik/e8/ X-Received: by 2002:a05:6a20:3d89:b0:125:6443:4eb8 with SMTP id s9-20020a056a203d8900b0012564434eb8mr2444357pzi.5.1688106610964; Thu, 29 Jun 2023 23:30:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688106610; cv=none; d=google.com; s=arc-20160816; b=XyVk/vxFGQw9dyWW6U8m7fac2uWGU5Vj+L/DXUZ8E60zwXF6lKPDbI0rrrxfDzMJ5F cDH2aB9qXklpo5uqHg641znhq9KdcQw523/IVEb6hBxN6fgJgZFK/xe20tTVvUPCgDrw xJEV6eIiaLfynXi0wSrc4ZAEdI1ZafnWAeOW6edEBc26mSV8f/b8cyxIou4clsCuHXQL 4p/MKrcLDxbH/d9jz6jtQBlwk+ZlE7rf/xMiyXwkIFC0nFAVL95UGL+VXuCeywEYRZQx JWV2h0gx4DJM2i/qZHAwV7g5CYscJ+lCEsV1HXTjQyOsjp0GqrJuPdI8kVrTZK92ZGAO FEcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=PLWDmL0719Hr2gG3EEl+0qUnU6cpLO9FxdrIP7mwvNs=; fh=aySem5gJZU8KoN3ZvLLhtOqzGItlX5yXPmrSZTzKnCg=; b=ksBfYn0QqI5vD1FVaQBgKRBHSA4KBN5AtSbolBiqSSR2+BcilHcOw//+08f+ekeKp6 ci9RqlTTA7cSVVzJidTWEAAbm6acLNYIklm9TctdtJi3qAEEJGYQpRTdDmljh0eTPxg4 4kmldsMdZR9ewuIL4/h9AUKWoNtu0FMwI9ZOtSNn5C6LMyMn1dPHa1V3qhl96Gwrxnvp 7yxd7q71VpE6vKWFA1MYv6orE7EbmaEPXs+tr2/HQje1RXgF/4QTxfXgJJNnwnrwpJ6o rcSlp57AXoqWi1R06j2qEIHTrzWEUqUOjuh2EctW7lYrsIGSYha++gzhGhHEh+av4WVI Vusg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=dsDcFKDg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cw24-20020a056a00451800b00666e8e573a4si10767126pfb.241.2023.06.29.23.29.58; Thu, 29 Jun 2023 23:30:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=dsDcFKDg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232212AbjF3G3O (ORCPT + 99 others); Fri, 30 Jun 2023 02:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230455AbjF3G3G (ORCPT ); Fri, 30 Jun 2023 02:29:06 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88FF42D63; Thu, 29 Jun 2023 23:29:05 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35TIb9Pj007758; Thu, 29 Jun 2023 23:28:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=PLWDmL0719Hr2gG3EEl+0qUnU6cpLO9FxdrIP7mwvNs=; b=dsDcFKDgy6Ec0YC38FMCWn1GwXjQjMO++2rQXpZk/vfyykrAwF9MBBdeMmj/cGjKsBqN 7IQTNawyahzvj5AsD8Jz7i1aXT6Hhx/kNqKdn7v2sBaA5Nk6LGAqJzibQUNaJ5ese7sX JdII8AN+iOKxTcG1X1CBRxKfT4XGmaoV1Hru8ZKjcfMxTXnkBsWw1Pj1XIrQbXxDkslS pJ5F3n4Xkyq5ypHbfj21WPMfwJWedKDa1/FbaFXuPhxmvW18I+T2oEZ8kWRHlyVeLZVq Nb/BUanLnQubRxrJA0NqLNF49VWLjOFmez6fgxz70AxR8uQv1NKIhio+KbjbME5VuLPT XA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3rgvpc58rs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Jun 2023 23:28:59 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 29 Jun 2023 23:28:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 29 Jun 2023 23:28:56 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 3B8F43F707B; Thu, 29 Jun 2023 23:28:52 -0700 (PDT) From: Hariprasad Kelam To: , CC: , , , , , , , , Subject: [net Patch 2/4] octeontx2-af: Fix mapping for NIX block from CGX connection Date: Fri, 30 Jun 2023 11:58:43 +0530 Message-ID: <20230630062845.26606-3-hkelam@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230630062845.26606-1-hkelam@marvell.com> References: <20230630062845.26606-1-hkelam@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wddn4KaAuwT7qENWxf-rtnn45D_WJnaY X-Proofpoint-ORIG-GUID: wddn4KaAuwT7qENWxf-rtnn45D_WJnaY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-30_03,2023-06-27_01,2023-05-22_02 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770108077848321332?= X-GMAIL-MSGID: =?utf-8?q?1770108077848321332?= Firmware configures NIX block mapping for all MAC blocks. The current implementation reads the configuration and creates the mapping between RVU PF and NIX blocks. But this configuration is only valid for silicons that support multiple blocks. For all other silicons, all MAC blocks map to NIX0. This patch corrects the mapping by adding a check for the same. Fixes: c5a73b632b90 ("octeontx2-af: Map NIX block from CGX connection") Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham Reviewed-by: Simon Horman --- drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 11 +++++++++++ drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index b5a7ee63508c..d4b8d4546de2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -23,6 +23,7 @@ #define PCI_DEVID_OCTEONTX2_LBK 0xA061 /* Subsystem Device ID */ +#define PCI_SUBSYS_DEVID_98XX 0xB100 #define PCI_SUBSYS_DEVID_96XX 0xB200 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 @@ -686,6 +687,16 @@ static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) return rvu->hw->cpt_chan_base + chan; } +static inline bool is_rvu_supports_nix1(struct rvu *rvu) +{ + struct pci_dev *pdev = rvu->pdev; + + if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) + return true; + + return false; +} + /* Function Prototypes * RVU */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c index 83b342fa8d75..48611e603228 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c @@ -114,7 +114,7 @@ static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf, p2x = cgx_lmac_get_p2x(cgx_id, lmac_id); /* Firmware sets P2X_SELECT as either NIX0 or NIX1 */ pfvf->nix_blkaddr = BLKADDR_NIX0; - if (p2x == CMR_P2X_SEL_NIX1) + if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1) pfvf->nix_blkaddr = BLKADDR_NIX1; } From patchwork Fri Jun 30 06:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hariprasad Kelam X-Patchwork-Id: 114587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp10144396vqr; Thu, 29 Jun 2023 23:33:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6h8De1smmqME8CB9JgL3S1S7iIRuHLg4zO7OBdB1pb5GhTJRbm3nJTbet7wXaqABqbSUE3 X-Received: by 2002:a05:6830:2aa0:b0:6b8:7de3:8a3f with SMTP id s32-20020a0568302aa000b006b87de38a3fmr2435665otu.3.1688106803279; Thu, 29 Jun 2023 23:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688106803; cv=none; d=google.com; s=arc-20160816; b=DiHQIjw61HXxA5EL50HF/TcsDXWg6CZZOECZ3ryQfuzgErJI/dUXjRtw+opj3ePxaw 20E8PD9Ab3rxVx3PtQRHfnM56Ahe5Z5IdgUrmuOQMplMxUFBrEgyS3vKCTdJo7Qi81XT /MJQ9M8WWTVF/Q9AwKeQet8QXlbx+a4EMBtbb82/1Vr4R+esLbRLg9KYEEJ83AglIRSB 36DtCwbybx7AaxG+tCHV7I5W+/1SwJrjlTxtMyy74Nn4gxriaishuCLC/cVq26xE0cV3 pOfw9JCMgmnv9BTkOgNltk/MyMyMhobnZWQZZCcwWmNXfJhtk31QZ+ZtvqYMPJFgkk9c A2Jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=rWyzZqcmXgpWtJawATcjZRNO+M4ovmpNa6UwHV2ObrQ=; fh=aySem5gJZU8KoN3ZvLLhtOqzGItlX5yXPmrSZTzKnCg=; b=mcIm0T0sAJiKNmBkZW5eKtrs8qqa9LH3t4FzG+cm8Nc8Kvgen+Vo7kCifCSKx7+aCG A6uPaFSh+yV47l8bWzlBcSIpBRSFsakkZzrTMxdeGgixkEHWzr5/ts1GGDs2TSqNVlzq NATLwC0acsIICwQTHygDJxS8MJwd+Mty3IthbOpEduHkka/BKy5Rhe9vcILS6EHsJB7n Hri+1NPZ/DF+5h0upuItjmv3cCRjOhxMdqCpjBiD77XwwYvM46IKyICmhS4f5ni/KhEE U2l1RzszoojeCUIcMKMrpBryXWssIsVIMBftJWBpnxafOtUZjDrJKiI8KUy5yzp+EKwD 7JvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=b7JXoL8B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c20-20020a6566d4000000b0055aed54f22bsi7713744pgw.710.2023.06.29.23.33.09; Thu, 29 Jun 2023 23:33:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=b7JXoL8B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232267AbjF3G3T (ORCPT + 99 others); Fri, 30 Jun 2023 02:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232180AbjF3G3J (ORCPT ); Fri, 30 Jun 2023 02:29:09 -0400 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94C5E30C5; Thu, 29 Jun 2023 23:29:08 -0700 (PDT) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35U2CEYA013691; Thu, 29 Jun 2023 23:29:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=rWyzZqcmXgpWtJawATcjZRNO+M4ovmpNa6UwHV2ObrQ=; b=b7JXoL8B81QbYKXBfWLGenN1N9vFsjzCNyf7gXGBqvXnafMDiOTtO3W3Y4uJ/oDFVQYw u1gxkeLO6zR0yXnebDRxxYtBk1RYKvJF6PRMbBAZo1T/NFsTHvGiEuGMVTk1m84YWfcH x+1ArVT7ZM0ttiQ7jU/XtnogTjRE9vJDUpkuhojRRlDrEDhPWiEB+jJQRHvZhxy/cEEB RSiog1XjAS7uIrkr1csMaRuYHwklOWnqi6yyguLBSE6HBNlehaJRKpiHmHu/efGi7Xju DwMqsuLk7GKD0RZOHfioptyBRNO2PnFHY7gvdNDeI6Ho8vy56jJHHShQuG/HhZjf5ba8 Ug== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3rhp2egqtg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 29 Jun 2023 23:29:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 29 Jun 2023 23:29:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 29 Jun 2023 23:29:00 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id E96FA3F707D; Thu, 29 Jun 2023 23:28:56 -0700 (PDT) From: Hariprasad Kelam To: , CC: , , , , , , , , Subject: [net Patch 3/4] octeontx2-af: Add validation before accessing cgx and lmac Date: Fri, 30 Jun 2023 11:58:44 +0530 Message-ID: <20230630062845.26606-4-hkelam@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230630062845.26606-1-hkelam@marvell.com> References: <20230630062845.26606-1-hkelam@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: KihpqnPpPuci-9vTPrLmHMojzsG8Mxhj X-Proofpoint-GUID: KihpqnPpPuci-9vTPrLmHMojzsG8Mxhj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-30_03,2023-06-27_01,2023-05-22_02 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770108279371578755?= X-GMAIL-MSGID: =?utf-8?q?1770108279371578755?= with the addition of new MAC blocks like CN10K RPM and CN10KB RPM_USX, LMACs are noncontiguous and CGX blocks are also noncontiguous. But during RVU driver initialization, the driver is assuming they are contiguous and trying to access cgx or lmac with their id which is resulting in kernel panic. This patch fixes the issue by adding proper checks. [ 23.219150] pc : cgx_lmac_read+0x38/0x70 [ 23.219154] lr : rvu_program_channels+0x3f0/0x498 [ 23.223852] sp : ffff000100d6fc80 [ 23.227158] x29: ffff000100d6fc80 x28: ffff00010009f880 x27: 000000000000005a [ 23.234288] x26: ffff000102586768 x25: 0000000000002500 x24: fffffffffff0f000 Fixes: 91c6945ea1f9 ("octeontx2-af: cn10k: Add RPM MAC support") Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham Reviewed-by: Simon Horman --- drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c index bd77152bb8d7..f4bdca662d61 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -169,6 +169,9 @@ void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) { struct cgx *cgx_dev = cgx_get_pdata(cgx_id); + /* Software must not access disabled LMAC registers */ + if (!is_lmac_valid(cgx_dev, lmac_id)) + return; cgx_write(cgx_dev, lmac_id, offset, val); } @@ -176,6 +179,10 @@ u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) { struct cgx *cgx_dev = cgx_get_pdata(cgx_id); + /* Software must not access disabled LMAC registers */ + if (!is_lmac_valid(cgx_dev, lmac_id)) + return 0; + return cgx_read(cgx_dev, lmac_id, offset); } From patchwork Fri Jun 30 06:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hariprasad Kelam X-Patchwork-Id: 114588 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp10144638vqr; Thu, 29 Jun 2023 23:34:04 -0700 (PDT) X-Google-Smtp-Source: APBJJlF2XCJ5LhPhyxKIlB3HaFqbkzbmnonL5gpd/KUDWUXzTGn4o1BGccnMZMDRPiYQbe77mzm3 X-Received: by 2002:a17:903:268b:b0:1b8:1591:9f8c with SMTP id jf11-20020a170903268b00b001b815919f8cmr1409831plb.3.1688106843850; Thu, 29 Jun 2023 23:34:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688106843; cv=none; d=google.com; s=arc-20160816; b=umw8wLdT+AHf4vVDVXiAdCudfVlaYe2bwPPbCU4kOp8DmjdpOj3ce+5LHosKd3DWP+ S/S5CQQjF5E1oBBKYwF+BJEvu+ikSoXI1AQErD2ObG9qhhhmEWMfirM7MfGeSOXQi96N /qQNIrwmY7bw9vbT8oXk2TU5qp5BPaRGHPlOiAuCzGGcL0kfIEzxZZmwXyWkNBB7i2uf x1DukqmuI7uV6kOg8G1xdWOFABhIAsi1otWzhH6wSj/ao0Cg1NXt7bK9nCZ7ZbtK6r50 xavkx3B45goFs9qQMjZDIo5Ua4G+KaeqIpJv5Cl6NvyEQhiQ0iaZY6UwIAeGNbRYxAGu E7IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3tSr+RNlu5c90zTQc8RZlZQwxk7z8fDmjfhvkyvZtmg=; fh=aySem5gJZU8KoN3ZvLLhtOqzGItlX5yXPmrSZTzKnCg=; b=rEYtRTsNbF90LQcOyBlv9DJE0GdBkLArSpo6IRL2dPwzrSXZrOvCAnH0UqSWCTSkbU ZFxoM6/KJCVfItHxpX6dlbDnXMKNzQZCxN2EP2yikW63m5lmLLmhr7GTQuhHdWo3wQTu 4zJhv61rC3tZHVitUSMw7GCZdvsYqKFUEIlkRENGWfx/0miKmY5+iLOIlEsHoffnOJgd aGycqT81QQ7rcqE3By0s5R63xPxRiB+IySNrE/nXtqLMRkBaSByKLHpOli9U+LxucOhg o5aMJauKpkLsFWw1bRVIZkHHqKRHmakx525xgQz/xtbKMqCEoG4AmJp0EELv9IluYFkz C7GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=WZufsuGz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com Received: from out1.vger.email (out1.vger.email. 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But these features are not getting reset in FLR. This patch fixes the issue by resetting the same. Fixes: 23999b30ae67 ("octeontx2-af: Enable or disable CGX internal loopback") Fixes: 1121f6b02e7a ("octeontx2-af: Priority flow control configuration support") Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham --- .../net/ethernet/marvell/octeontx2/af/cgx.c | 26 ++++++++++++++-- .../net/ethernet/marvell/octeontx2/af/cgx.h | 2 ++ .../marvell/octeontx2/af/lmac_common.h | 3 ++ .../net/ethernet/marvell/octeontx2/af/rpm.c | 30 +++++++++++++++++-- .../net/ethernet/marvell/octeontx2/af/rpm.h | 2 ++ .../net/ethernet/marvell/octeontx2/af/rvu.c | 1 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_cgx.c | 18 +++++++++++ 8 files changed, 77 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c index f4bdca662d61..592037f4e55b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c @@ -537,14 +537,15 @@ static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id) int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) { struct cgx *cgx = cgxd; - u8 lmac_type; + struct lmac *lmac; u64 cfg; if (!is_lmac_valid(cgx, lmac_id)) return -ENODEV; - lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id); - if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) { + lmac = lmac_pdata(lmac_id, cgx); + if (lmac->lmac_type == LMAC_MODE_SGMII || + lmac->lmac_type == LMAC_MODE_QSGMII) { cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); if (enable) cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; @@ -1563,6 +1564,23 @@ int cgx_lmac_linkup_start(void *cgxd) return 0; } +int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr) +{ + struct cgx *cgx = cgxd; + u64 cfg; + + if (!is_lmac_valid(cgx, lmac_id)) + return -ENODEV; + + /* Resetting PFC related CSRs */ + cfg = 0xff; + cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg); + + if (pf_req_flr) + cgx_lmac_internal_loopback(cgxd, lmac_id, false); + return 0; +} + static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, int cnt, bool req_free) { @@ -1682,6 +1700,7 @@ static int cgx_lmac_init(struct cgx *cgx) cgx->lmac_idmap[lmac->lmac_id] = lmac; set_bit(lmac->lmac_id, &cgx->lmac_bmap); cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); + lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id); } return cgx_lmac_verify_fwi_version(cgx); @@ -1778,6 +1797,7 @@ static struct mac_ops cgx_mac_ops = { .mac_tx_enable = cgx_lmac_tx_enable, .pfc_config = cgx_lmac_pfc_config, .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg, + .mac_reset = cgx_lmac_reset, }; static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h index 5a20d93004c7..574114179688 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h @@ -35,6 +35,7 @@ #define CGXX_CMRX_INT_ENA_W1S 0x058 #define CGXX_CMRX_RX_ID_MAP 0x060 #define CGXX_CMRX_RX_STAT0 0x070 +#define CGXX_CMRX_RX_LOGL_XON 0x100 #define CGXX_CMRX_RX_LMACS 0x128 #define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset) #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) @@ -181,4 +182,5 @@ int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, u8 *rx_pause); int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, int pfvf_idx); +int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr); #endif /* CGX_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h index 39aaf0e4467d..0b4cba03f2e8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h @@ -24,6 +24,7 @@ * @cgx: parent cgx port * @mcast_filters_count: Number of multicast filters installed * @lmac_id: lmac port id + * @lmac_type: lmac type like SGMII/XAUI * @cmd_pend: flag set before new command is started * flag cleared after command response is received * @name: lmac port name @@ -43,6 +44,7 @@ struct lmac { struct cgx *cgx; u8 mcast_filters_count; u8 lmac_id; + u8 lmac_type; bool cmd_pend; char *name; }; @@ -125,6 +127,7 @@ struct mac_ops { int (*mac_get_pfc_frm_cfg)(void *cgxd, int lmac_id, u8 *tx_pause, u8 *rx_pause); + int (*mac_reset)(void *cgxd, int lmac_id, u8 pf_req_flr); /* FEC stats */ int (*get_fec_stats)(void *cgxd, int lmac_id, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c index a433f92c51ea..b4fcb20c3f4f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c @@ -37,6 +37,7 @@ static struct mac_ops rpm_mac_ops = { .mac_tx_enable = rpm_lmac_tx_enable, .pfc_config = rpm_lmac_pfc_config, .mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg, + .mac_reset = rpm_lmac_reset, }; static struct mac_ops rpm2_mac_ops = { @@ -68,6 +69,7 @@ static struct mac_ops rpm2_mac_ops = { .mac_tx_enable = rpm_lmac_tx_enable, .pfc_config = rpm_lmac_pfc_config, .mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg, + .mac_reset = rpm_lmac_reset, }; bool is_dev_rpm2(void *rpmd) @@ -537,14 +539,15 @@ u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id) int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable) { rpm_t *rpm = rpmd; - u8 lmac_type; + struct lmac *lmac; u64 cfg; if (!is_lmac_valid(rpm, lmac_id)) return -ENODEV; - lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id); - if (lmac_type == LMAC_MODE_QSGMII || lmac_type == LMAC_MODE_SGMII) { + lmac = lmac_pdata(lmac_id, rpm); + if (lmac->lmac_type == LMAC_MODE_QSGMII || + lmac->lmac_type == LMAC_MODE_SGMII) { dev_err(&rpm->pdev->dev, "loopback not supported for LPC mode\n"); return 0; } @@ -713,3 +716,24 @@ int rpm_get_fec_stats(void *rpmd, int lmac_id, struct cgx_fec_stats_rsp *rsp) return 0; } + +int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr) +{ + u64 rx_logl_xon, cfg; + rpm_t *rpm = rpmd; + + if (!is_lmac_valid(rpm, lmac_id)) + return -ENODEV; + + /* Resetting PFC related CSRs */ + rx_logl_xon = is_dev_rpm2(rpm) ? RPM2_CMRX_RX_LOGL_XON : + RPMX_CMRX_RX_LOGL_XON; + cfg = 0xff; + + rpm_write(rpm, lmac_id, rx_logl_xon, cfg); + + if (pf_req_flr) + rpm_lmac_internal_loopback(rpm, lmac_id, false); + + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h index be294eebab26..b79cfbc6f877 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h @@ -74,6 +74,7 @@ #define RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA 0x80A8 #define RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA 0x8108 #define RPM_DEFAULT_PAUSE_TIME 0x7FF +#define RPMX_CMRX_RX_LOGL_XON 0x4100 #define RPMX_MTI_MAC100X_XIF_MODE 0x8100 #define RPMX_ONESTEP_ENABLE BIT_ULL(5) @@ -132,4 +133,5 @@ int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, int rpm2_get_nr_lmacs(void *rpmd); bool is_dev_rpm2(void *rpmd); int rpm_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); +int rpm_lmac_reset(void *rpmd, int lmac_id, u8 pf_req_flr); #endif /* RPM_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 0069e60afa3b..8dbc35c481f6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2629,6 +2629,7 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) * Since LF is detached use LF number as -1. */ rvu_npc_free_mcam_entries(rvu, pcifunc, -1); + rvu_mac_reset(rvu, pcifunc); mutex_unlock(&rvu->flr_lock); } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h index d4b8d4546de2..e8e65fd7888d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -895,6 +895,7 @@ int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, u16 pfc_en); int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); +void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, int type); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c index 48611e603228..4b8559ac0404 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c @@ -1250,3 +1250,21 @@ int rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause); return err; } + +void rvu_mac_reset(struct rvu *rvu, u16 pcifunc) +{ + int pf = rvu_get_pf(pcifunc); + struct mac_ops *mac_ops; + struct cgx *cgxd; + u8 cgx, lmac; + + if (!is_pf_cgxmapped(rvu, pf)) + return; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); + cgxd = rvu_cgx_pdata(cgx, rvu); + mac_ops = get_mac_ops(cgxd); + + if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc))) + dev_err(rvu->dev, "Failed to reset MAC\n"); +}