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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hd34-20020a17090796a200b0078db6f5f4b2si323680ejc.546.2022.10.28.10.03.14; Fri, 28 Oct 2022 10:03:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=HWshL2JJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbiJ1RAT (ORCPT + 99 others); Fri, 28 Oct 2022 13:00:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230452AbiJ1Q75 (ORCPT ); Fri, 28 Oct 2022 12:59:57 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71092E0A6; Fri, 28 Oct 2022 09:59:32 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id g12so7394590wrs.10; Fri, 28 Oct 2022 09:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Ku5lF3CTU+uK+oU1JYQf2lS5QXHn/wjM4We6ht5jRA=; b=HWshL2JJrihm1Gcnitlj9oBwqZbG7dBrNPu2swm/BttlGesn2PbwoludpIRmUqu/c2 u+0/lEsEtreics+jk1lNEkNPjhSw5mGVmG2QSDOHoxlSEz0ifhRdpu4uWhF+MEkjtmq/ 04vDzTVzawaOTdfjoJuDrVR2oY9jHtBU3HBPCDwVkjFC3f8Dxqhpj0AVZSQU5GfS4j5R FPi6r3ZTA9vXDzWqsawkQMZ7ubdJBKiAP11uCgLSxDvzd4O99NaZaFOPers0C0iGlf8U m0ETAFo43FIj0Cp/iqz/bCurJahrqxEnLcpf7SlMoVldil5UWxZPIp1Cv89lOrUMzzPF HBEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Ku5lF3CTU+uK+oU1JYQf2lS5QXHn/wjM4We6ht5jRA=; b=pOtnPTlLkvFr7jhG5pChVdJtW4PmxOyJY7L4vQL8loI6SKo03hbtJJjSZq2LzDtGpL 0R4odJnB2/i55yvmpujwnqxsLt8jaHg+CiSjFshE/aU6X8ad5Igt2V3m/9AfpSDos0rM MwIORcNmbun6xSbEgPJPwH4w6sGSfzEG0BxIUyaiitY3fjNrhG7FQhrFikpIFKnfRlby 6zz6H9kX9tQGjWMlqQWuhH3KGCjV+ZNITNckFg7egRPC87q4cptiJt01YIT/wjoW1m+o aatHpXf/MqbqjJyOFRa8DpPudjawnMoawh1fzuxhbCBKUZG0ce/THpa0ncVyElY2HuA5 BnSw== X-Gm-Message-State: ACrzQf1qfzPJ9E0ishFcUoZDPeFMYSNcP61fROXMAtPAIvOJ3+Jv65Ks ugrBF49Fi+upqcNQDfYuDGk= X-Received: by 2002:adf:aa8d:0:b0:236:588f:71f with SMTP id h13-20020adfaa8d000000b00236588f071fmr170388wrc.205.1666976371539; Fri, 28 Oct 2022 09:59:31 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d53b:eaf9:15f:6a8a]) by smtp.gmail.com with ESMTPSA id h2-20020adfe982000000b002322bff5b3bsm4939689wrm.54.2022.10.28.09.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 09:59:30 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Conor Dooley , Guo Ren , Anup Patel , Atish Patra , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Date: Fri, 28 Oct 2022 17:59:15 +0100 Message-Id: <20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747951677839824542?= X-GMAIL-MSGID: =?utf-8?q?1747951677839824542?= From: Lad Prabhakar Sort the CPU cores list alphabetically for maintenance. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- v4 -> v5 * Included RB tag from Conor v3 -> v4 * Included RB tag from Heiko v2 -> v3 * Included RB tag from Geert v1 -> v2 * Included RB tag from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..ae7963e99225 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,17 +28,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: From patchwork Fri Oct 28 16:59:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12476 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941747wru; Fri, 28 Oct 2022 10:04:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4vpTLybN7FSZVbkFX/PkFn65oE5Dxv0niWDt9P6F5Ja4vNdW83baQLQOfIRKIeux0DiMOz X-Received: by 2002:a17:906:16d9:b0:7ad:a2ef:54c8 with SMTP id t25-20020a17090616d900b007ada2ef54c8mr299502ejd.632.1666976672012; Fri, 28 Oct 2022 10:04:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666976672; cv=none; d=google.com; s=arc-20160816; b=Hb3wNxfb7TS3Wm3Se0JJfYib/HXWa19fv16jhl3NQ9QMUr8Sa0riGWHdwtlXwXz5Zu dFX4K2jhxdNlmPkUzraGC3Yu2pUfNKVeNuSJn6VX4haSQGZ6289II4E0TmeoldZC8503 Lu/IyKUpoGV7qapABm8I4EOkZzNQmtT8+QwPy6a9+to3BJ/b6GlQxVLHV53wgwm1F/OQ wS+qszqTMJQvaRwCNF/TtAT0xfHiNasoj8LtA/NcpGOav3hCHNPuYV/cWe2nOVije40+ vD0VaN/8H5ZWwXOUgvnmTSxqUd1dahByQmxWMPgztvyrBdLS6fai40RTlmH69maN+AW0 txpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s2faLQwm60FIW0toXle/b/I/Kg1QLaRnJK5/efYQgUQ=; b=ipV+AM0c0+zXw10L4vZCfaCW0SFWxbjim+4SuCmfld8RgADmS+9snwK0R5iMyyq6Ao 8JVHhwUUOzMMFcdhTxah7SYW11wk7lZkAOZeheq4pqsXdfe+vRifGJQMT9FDA0nfGb8I 3j31P1Uhwij0jJE/mEkIPRyd5qzOv3Re3XxviD5VkmgZvnG2RkCzS1NfPM90gQC1oEXf 3ZkKgSGBo9sCBIFisYsC30ELU3czXv9BfXZ00xBYGSy+v7tk5E7u23kQTh6LPVfmsN0s 35yBPzua9BC0cHvW71EGeWp9VFZY+/lFjMTbswRiusyzczWH067Je4DeXvVFblLcJTeO qWFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="mUHskhk/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list. More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- v4 -> v5 * Included RB tag from Conor v3 -> v4 * No change v2 -> v3 * Included RB tag from Geert v1 -> v2 * Included ack from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index ae7963e99225..2bf91829c8de 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,6 +28,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5 From patchwork Fri Oct 28 16:59:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12472 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941111wru; Fri, 28 Oct 2022 10:03:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Nn8orTDTWhJfOSqYt7LIXROFunxY9v7JBfN42z5jXFtFe6IVKf4c1F0xuBEkJxBAAm1t1 X-Received: by 2002:a17:906:dc93:b0:791:95dd:aaf6 with SMTP id cs19-20020a170906dc9300b0079195ddaaf6mr296540ejc.456.1666976610084; Fri, 28 Oct 2022 10:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666976610; cv=none; d=google.com; s=arc-20160816; b=fwYbr0XPTlR6GncIFRz5bn0ExrcMMeOVdFpqmykosrGo+9Ucq+VGVAbT2RkpWgyq5O r0xR+9ujfqNSUNv+Lw8CQED0aAOZJca3UCw8cZKkVlwa1lIG7o6c52BQwzqUOlMbnTns JrnqSiReJ/vP4PGGOPPZow146bhXwAF+PALDVCOnrLPCjjw6njViUVpDfVBdwqHm71Y4 t06Zo0FkC70e88/78OMMOXQMskiCK443JuwyIBMaMUWUkXPjVu8rEXoSgjbJbPkZehxx l94Ad/bngX4nxP22UCkY7s4HeSXWB9q32eK6CtPJbySHOBKgUmA/BfHmo2UrmuVNxQsO as1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Gju3CMb3jhkVvblFFI0iIit6dBsGsDogFez5dmlOa7U=; b=AYfKn64XTagNi7J14KZu9r5ULpj2FmJUzTZK+RvuMz0fNb6ByJGB0BAlwUyXomULBO 6AbB6RL78HvHnpuBuvtmvaXxVcnzn0QslHC1m+1O13EewMhW8uR98OE6mEUsUStEA+Jm vtWR3zoMQ7ndO1ZaTz/PjZ4cxyhBerbQSpbAZxrJ7FcPpwRyW6BlrTBgDe04HNoKVX2r EFLIbdP39fkfrBVDc/7g+GdxjzNf51SNh813D6NTDnSO8NFPYk1SXyIHhKT7nCt7E3K1 ZHQ8tli0dlKljljzMRkdmUgRVbEA292uQUnrr3E2n+YVJRLwVIV1qYQfC244wBIS6jr4 SezA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=OFPb950A; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Reviewed-by: Geert Uytterhoeven --- v4 -> v5 * Sorted as per SoC name * Included RB tag from Conor v3 -> v4 * Dropped SOC_RENESAS_RZFIVE config option * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs under ARCH_RENESAS * Updated commit message * Dropped RB tag * Used riscv instead of RISC-V in subject line v2 -> v3 * Included RB tag from Geert v1 -> v2 * No Change --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..75fb0390d6bd 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,11 @@ config SOC_MICROCHIP_POLARFIRE help This enables support for Microchip PolarFire SoC platforms. +config ARCH_RENESAS + bool "Renesas RISC-V SoCs" + help + This enables support for the RISC-V based Renesas SoCs. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY From patchwork Fri Oct 28 16:59:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12474 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941281wru; Fri, 28 Oct 2022 10:03:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4ctf9cAuMuPyxKveEiiH/u4eLqVbrKXyeNph7xZ7OrbpUJlo3XXf/teoqgRDjFugZqgRQb X-Received: by 2002:a17:907:7805:b0:780:24fd:c4e8 with SMTP id la5-20020a170907780500b0078024fdc4e8mr325395ejc.78.1666976628089; Fri, 28 Oct 2022 10:03:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666976628; cv=none; d=google.com; s=arc-20160816; b=SRBLJYMwj4L4vJOCqHWdxbB7v4nijB/SSrEmJ+cPWLXLRRNQ2B2atOZO1TR1CsFaSv GKsHM2p+yFCz7S/1kwc9Dx2BiUf4J3ChZ7MGiI2bRzGfNVd0W6vJ8BLecXTGoycmoHWj nevDzQgXalJHV8a8v02ycooDriolNlxwOo3Ut7ModYo7SxFMw7nKPPmfALUdQG+cN324 vOLlwf9pLG7fDqLXv7X3LPtiTT4P73psNltbR0Y+a8ruIN53KIVA96gDmUKUQO+QJ1uS kkgmt4utKAYiuw9yG4rw7oTfRYmPulOEc51/Ay+hfwW3miO/m/BQQYl6N82rKBK8D7fw HwXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Uwam57UrMly/7fzbCijndaabO19arvpUZgXGPs6USsk=; b=ypkZ65H6VyoVhlkLhyKqJYGipS0n5SiBiVr1blPm3cOCq9L85aDW8K3w9nX4tJPuQ+ j4d+PZV5COqS4IjFGJ85WuVLPXoY7jqwJHvSZ1Y+c1+wWn6oFEYEH+pSCC0OSYsk2zqY m5yEsGRlhYpkuyNNF2zO09kVYAe+C3dQQ1kvluHqGlxVmATfLlEobx4VY0iqJoLSpqyr XgJy8FG/h/bEqynfeyfrwGt8RcsTYVh44Ve/EgeWhBBZHlylKA1UhxvXEOeIHDGTRint pd8x57zyBTqie7hPs3eX2k6KqhWRYUai+XZIcU05gjMAXbxuiwYjG/Z9oraFaVtX8dbd u4uA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=j3dE9iFZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f7-20020a056402354700b00457f31c1a10si6215915edd.584.2022.10.28.10.03.22; Fri, 28 Oct 2022 10:03:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=j3dE9iFZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231162AbiJ1RAh (ORCPT + 99 others); Fri, 28 Oct 2022 13:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230413AbiJ1Q76 (ORCPT ); Fri, 28 Oct 2022 12:59:58 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFF9213FA3; Fri, 28 Oct 2022 09:59:37 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id y16so7379401wrt.12; Fri, 28 Oct 2022 09:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uwam57UrMly/7fzbCijndaabO19arvpUZgXGPs6USsk=; b=j3dE9iFZN3Q4xHL4MBNM8nTSfEpFB1Jd797KVcPXCUEbjqQv7rSf7t7uxd4Ozl+Qs9 4B/lh3AjjZBXDs7JFchaMSVC/uS0oK36fuRi2jihGh2VY5s8QVGyZKX/0p7GQAIbpnRh lFSmHGTMWjeIyQQRPG/m45xIVo1fHR0cQS1BqJlJN4TmD6E7y78I2TyvVVz+RJMnPRgJ IMR9xHqmGSka2GeRcD85UaooRbjP56w3/jiSDG7MVixTxurH9au3BiRqEOter2XWUZA0 QV13yHKvXniFfJLJwhL+MtzA5SWhiQnkQ13h5Y00lHIRAa9zw5+qoJRTlZt6jphZVsYL aESQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uwam57UrMly/7fzbCijndaabO19arvpUZgXGPs6USsk=; b=2GsXoqHYWJ515GM2e7NPen0+HflUPrq645kHhleXWLOtXhuxdDFd1ehHhv89AYIcss pzocTkAlyy5gyPXWpyYAKbaE2h/b22PL32BgRN46f5UHWPRs+p+Tvw85FPxu4K2UYpp/ RDOs36+D/pUcf6VGFk8n6QhIGEkKRAxaRNMpOa8Kb+wgK3D4dHR1RuUjAQYbn4Ub2C75 kisl67mafZX67eeltkUoRA77/coJxjtYuzOLPcSWlQlEpVILZvVszBrOOpBLwtpKdS20 Ebu2inhNXMZT3DaBfRRoR7PqkG/K+G1f2LqP4tsqyBgTguz80J/UqfBTu0BezPwqXazF pDsw== X-Gm-Message-State: ACrzQf18EEGK3KpW6sN8t9rUqdhF7Yjp3D+q6xt0z3CHMyOuhkvTdnZI 9rsrjtpIvxgbjGHp2cVMT/8= X-Received: by 2002:a5d:47aa:0:b0:236:79cc:6d5f with SMTP id 10-20020a5d47aa000000b0023679cc6d5fmr176258wrb.391.1666976375559; Fri, 28 Oct 2022 09:59:35 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d53b:eaf9:15f:6a8a]) by smtp.gmail.com with ESMTPSA id h2-20020adfe982000000b002322bff5b3bsm4939689wrm.54.2022.10.28.09.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Oct 2022 09:59:34 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm Cc: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Conor Dooley , Guo Ren , Anup Patel , Atish Patra , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Fri, 28 Oct 2022 17:59:18 +0100 Message-Id: <20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747951684629312406?= X-GMAIL-MSGID: =?utf-8?q?1747951684629312406?= From: Lad Prabhakar Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. r9a07g043f.dtsi includes RZ/Five SoC specific blocks. Below are the RZ/Five SoC specific blocks added in the initial DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - PLIC [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v4 -> v5 * Fixed riscv,ndev value (should be 511) * Reworked completely (sort of new patch) v3 -> v4 * No change v2 -> v3 * Fixed clock entry for CPU core * Fixed timebase frequency to 12MHz * Fixed sorting of the nodes * Included RB tags v1 -> v2 * Dropped including makefile change * Updated ndev count --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi new file mode 100644 index 000000000000..50134be548f5 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <12000000>; + + cpu0: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; +}; + +&soc { + interrupt-parent = <&plic>; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <511>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; +}; From patchwork Fri Oct 28 16:59:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12475 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941546wru; Fri, 28 Oct 2022 10:04:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM69uj2JsruZiM0zaex+xsXqa7NIvDAwNTJw0ytBLeZ21tcdJqBppEqtLWD/gAku9CTJSIRd X-Received: by 2002:a17:906:6791:b0:78d:4051:fcf0 with SMTP id q17-20020a170906679100b0078d4051fcf0mr251055ejp.591.1666976653670; Fri, 28 Oct 2022 10:04:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666976653; cv=none; d=google.com; s=arc-20160816; b=DYo0d8IKPj1FNaZ00jiiDiC300noeCIEmtVWswxV7rk45UhxnsAtmibEEXE0tKW6dI /tfzFbtqaOc+1D2g1Slt8w8mcHWkkmgX5HyBcuII5lXcS3GJRFygT17PWbm2hzQ64xRx VM+YrsHr0nkiKOUFVFrUbO8ANKnbiMLbMfP8Q83TLJ1NgsDY5IAEmzFxOLbh6UHFKn/E e97Imr96/tL4vFRaNYB9TkRqQV5gPozr+KyfNLQckEi21LhlDV1po9DVYWjQbTfIR74w 6/1HlZRVsHWzCi7B5kPgbaKBgJY0fyUVpcctid018yzuWFdabrHTscoha0/Jg4a2/90/ Chjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NmXIzlpO0gFQLKDuK9Y+/vStvG2XBv+k8tbLnLpI/QU=; b=roKmSQ87BDoYBMOavmcmkP3kDYNmBzKsTHjwgFZEzw4K0B2XniuPVq/SsumctZiRkz R+5st+FPDQ0+jOP1H3S4I44cqGN4p0QqDbtGzzwoILy1d3GTP1++WPSnociZamOHES9s 7wW7H8+e5BZIh+4FrdMM3lgsnqlJ2xzQ9H5ZZhzL5m6CIycOuB4EM3LgRe8rthva5fro R1xSONefHSm2UzxT7gcR3XxC2EFcXLHfbp/TSS4zFmMQxG8jV1DCisjBq44SbCa9Iv97 f5WzozT1iNlPj6hId7l/4A1qkjeRmBxesDPSTAXjVe88zeCs+jrZhUg4VVxwEwNBAOuQ PIkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NNeyX4eV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v4 -> v5 * Reworked completely (sort of new patch) v3 -> v4 * Dropped deleting place holder nodes * Updated SW1 settings comment * Update commit message v2 -> v3 * Dropped RB tags from Conor and Geert * Now re-using the SoM and carrier board DTS/I from RZ/G2UL v1 -> v2 * New patch --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 58 ++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 91 +++++++++++++++++++ 5 files changed, 179 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..2aa8515451d3 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "r9a07g043f.dtsi" +#include "rzfive-smarc-som.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..45a182fa3b4b --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + chosen { + bootargs = "ignore_loglevel"; + }; + + /delete-node/opp-table-0; + /delete-node/thermal-zones; +}; + +&adc { + status = "disabled"; +}; + +&dmac { + status = "disabled"; +}; + +ð0 { + status = "disabled"; +}; + +ð1 { + status = "disabled"; +}; + +&ostm1 { + status = "disabled"; +}; + +&ostm2 { + status = "disabled"; +}; + +&sdhi0 { + status = "disabled"; +}; + +&tsu { + status = "disabled"; +}; + +&wdt0 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..e64f0e5f8e30 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ i2c0; + /delete-property/ i2c1; + }; +}; + +&canfd { + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; +}; + +&ehci0 { + status = "disabled"; +}; + +&ehci1 { + status = "disabled"; +}; + +&hsusb { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +&ohci0 { + status = "disabled"; +}; + +&ohci1 { + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&sdhi1 { + status = "disabled"; +}; + +&snd_rzg2l { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&ssi1 { + status = "disabled"; +}; + +&usb0_vbus_otg { + status = "disabled"; +}; + +&usb2_phy0 { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&vccq_sdhi1 { + status = "disabled"; +}; From patchwork Fri Oct 28 16:59:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12471 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941080wru; 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Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- v4 -> v5 * Rebased on -next * Included RB tag from Conor v3 -> v4 * Included RB tag from Geert v2 -> v3 * Merged as part of ARM v1 -> v2 * New patch --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6cdc2a74c7a2..0204f106d8c2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2691,7 +2691,7 @@ F: arch/arm/boot/dts/rtd* F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ -ARM/RENESAS ARCHITECTURE +ARM/RISC-V/RENESAS ARCHITECTURE M: Geert Uytterhoeven M: Magnus Damm L: linux-renesas-soc@vger.kernel.org @@ -2713,6 +2713,7 @@ F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ F: arch/arm64/boot/dts/renesas/ F: arch/arm64/configs/renesas_defconfig +F: arch/riscv/boot/dts/renesas/ F: drivers/soc/renesas/ F: include/linux/soc/renesas/ From patchwork Fri Oct 28 16:59:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 12477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp941953wru; Fri, 28 Oct 2022 10:04:52 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Yy27FBp4P4m9TmIsNlLGC25fp2YQTJQP/8oDV1HnO5M3SvUC1ytOAYVjBx6ys4mVT+BfF X-Received: by 2002:a05:6402:2486:b0:460:8f86:1fca with SMTP id q6-20020a056402248600b004608f861fcamr424549eda.70.1666976692147; Fri, 28 Oct 2022 10:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666976692; cv=none; d=google.com; s=arc-20160816; b=dKqWSaGt3LKzxbEXzXyvdzGIcZrWBckYG40tHBkbTmPwwVOurXYdFrhlCfEY/kuYTO K5ardd94yt1ZZMsvVN8tuybhU0wuUnfNxEf1Xi6xTaXyi2+3hDlH57CymsKiZFy0U+xy hYPiCo1YIshOLnnnrZnS96ZQKe687Ei7iRwIer1GruA3vI/uxZ2Fd6Y0kjyvcYl4QeAN LDoQU1JK6o3vTiuFlRQ9zlZflmE8GaYDgv5cP7cG06tfxOYMmozsw8Qsh6e7aHRbY/QD QFuRUVWWyVtfPk6eYPGtTnQEOQPiykG1AlZdDjisDFT58tnZeHP8+9qGBMWu+ORQeRNt CXvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LKcaGbOXyklscEgGaVZeABkCmiJQn+cua48lgHGMfSM=; b=mNb9IR2pIHyLoB1FExzipH4bVp6BQUUdANSFp7qvBj0xhfCYhWtKJW8AmP4CAW9oO5 mB/1G1YPonmrXC6e+HBW6hEHMCk7KG9cmbAFk5zQaDZIVjdxFwa4aHvmm9GICTbKSIKr rD+ErLtrUKdoISNad1KozRRS+JD6yoId1RSdPADq+otZzNARnu1tBs2xRHzFmq3vxPbT CXr1wpmKPyLvn2ytldYWInlS2OS1ihGHuIUJhp4xKoChh84nkQdgiY/JmDA5eHiltjOZ 9DqWzyXc7rZeJ7jLoFQW9qqNFPgGQHSCj/YakFI33X73jmAvC3FSj/BCIcP/RMbPwQ3H bkaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=XktKVyJA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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It allows the default upstream kernel to boot on RZ/Five SMARC EVK board. Alongside enable SERIAL_SH_SCI config so that the serial driver used by RZ/Five SoC is built-in. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Reviewed-by: Guo Ren --- v4 -> v5 * No change v3 -> v4 * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB tags with this change) * Used riscv instead of RISC-V in subject line v2 -> v3 * Included RB tags * Updated commit description v1 -> v2 * New patch --- arch/riscv/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..97fba7884d7a 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_R9A07G043=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y @@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y