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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r187-20020a632bc4000000b005303bf3e14bsi11577951pgr.412.2023.06.29.13.05.51; Thu, 29 Jun 2023 13:06:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=UHoCkA0E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232176AbjF2TY0 (ORCPT + 99 others); Thu, 29 Jun 2023 15:24:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232596AbjF2TXc (ORCPT ); Thu, 29 Jun 2023 15:23:32 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FCF21FD8; Thu, 29 Jun 2023 12:23:31 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35TIhPIW031023; Thu, 29 Jun 2023 19:23:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=ZktDg8+mFfg6IYxOxEraVWv5FLlTc8FfQIF6iFrOYzs=; b=UHoCkA0EL8I26KVuD/tOyj3ESQbrqY57fMEn+WJqOVTLEWFo2skiKYILs5H0kW2VWLl6 CLXNBczrOJzc3Z5Bn3w9EcKrHMFuXASiTuY+93YDWvENl/GD7RFiOEKnC+I0MRqpZ7zR kwqk6LtYgzmKIFooW4Dkw9eDBKmjbt5yMDbtRv3JO+ehspwiIJELcFq7xQavdabWbQQM RkHmvbS2RBAVU7z5VAkudayE6ay/hoiRboUrYhczK5ayDEMUnYTzV/zqcrXhA6ZVx8YK Dx5XSc2GX3bn7q3ZFiq+PUGgusK5TcKPjWpuUD1Fvy2r95c8rp88FOm7S+2apMVi13Ab 2w== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rhfew82q6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Jun 2023 19:23:18 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35TJNHPU028096 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Jun 2023 19:23:17 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.7; Thu, 29 Jun 2023 12:21:49 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , Subject: [PATCH v2 1/3] drm/msm/dpu: re-introduce dpu core revision to the catalog Date: Thu, 29 Jun 2023 12:21:16 -0700 Message-ID: <20230629192121.14008-1-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DtDXSnC-1eK0SnBcewpLN5hZTh1rSVK6 X-Proofpoint-GUID: DtDXSnC-1eK0SnBcewpLN5hZTh1rSVK6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-29_06,2023-06-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306290174 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770068240574798290?= X-GMAIL-MSGID: =?utf-8?q?1770068813403179719?= With [1] dpu core revision was dropped in favor of using the compatible string from the device tree to select the dpu catalog being used in the device. This approach works well however also necessitates adding catalog entries for small register level details as dpu capabilities and/or features bloating the catalog unnecessarily. Examples include but are not limited to data_compress, interrupt register set, widebus etc. Introduce the dpu core revision back as an entry to the catalog so that we can just use dpu revision checks and enable those bits which should be enabled unconditionally and not controlled by a catalog and also simplify the changes to do something like: if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx) enable the bit; Also, add some of the useful macros back to be able to use dpu core revision effectively. [1]: https://patchwork.freedesktop.org/patch/530891/?series=113910&rev=4 changes in v2: - drop DPU step version as features are not changing across steps - add core_major_version / core_minor_version to avoid conflicts Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++++++-- 16 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 7d0d0e74c3b0..a5d486783c3f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -190,6 +190,8 @@ static const struct dpu_perf_cfg msm8998_perf_data = { }; const struct dpu_mdss_cfg dpu_msm8998_cfg = { + .core_major_version = 0x3, + .core_minor_version = 0x0, .caps = &msm8998_dpu_caps, .ubwc = &msm8998_ubwc_cfg, .mdp_count = ARRAY_SIZE(msm8998_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index b6098141bb9b..1fdb89a4b7a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -194,6 +194,8 @@ static const struct dpu_perf_cfg sdm845_perf_data = { }; const struct dpu_mdss_cfg dpu_sdm845_cfg = { + .core_major_version = 0x4, + .core_minor_version = 0x0, .caps = &sdm845_dpu_caps, .ubwc = &sdm845_ubwc_cfg, .mdp_count = ARRAY_SIZE(sdm845_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index b5f751354267..129c62cf450d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -208,6 +208,8 @@ static const struct dpu_perf_cfg sm8150_perf_data = { }; const struct dpu_mdss_cfg dpu_sm8150_cfg = { + .core_major_version = 0x5, + .core_minor_version = 0x0, .caps = &sm8150_dpu_caps, .ubwc = &sm8150_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm8150_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 8ed2b263c5ea..ca037b070f44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -214,6 +214,8 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { }; const struct dpu_mdss_cfg dpu_sc8180x_cfg = { + .core_major_version = 0x5, + .core_minor_version = 0x1, .caps = &sc8180x_dpu_caps, .ubwc = &sc8180x_ubwc_cfg, .mdp_count = ARRAY_SIZE(sc8180x_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index daebd2170041..e446af90767e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -214,6 +214,8 @@ static const struct dpu_perf_cfg sm8250_perf_data = { }; const struct dpu_mdss_cfg dpu_sm8250_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x0, .caps = &sm8250_dpu_caps, .ubwc = &sm8250_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm8250_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 67566b07195a..88288c80b652 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -132,6 +132,8 @@ static const struct dpu_perf_cfg sc7180_perf_data = { }; const struct dpu_mdss_cfg dpu_sc7180_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x2, .caps = &sc7180_dpu_caps, .ubwc = &sc7180_ubwc_cfg, .mdp_count = ARRAY_SIZE(sc7180_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 031fc8dae3c6..93c901502b5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -102,6 +102,8 @@ static const struct dpu_perf_cfg sm6115_perf_data = { }; const struct dpu_mdss_cfg dpu_sm6115_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x3, .caps = &sm6115_dpu_caps, .ubwc = &sm6115_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm6115_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 06eba23b0236..ff7e4b775fd5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -141,6 +141,8 @@ static const struct dpu_perf_cfg sm6350_perf_data = { }; const struct dpu_mdss_cfg dpu_sm6350_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x4, .caps = &sm6350_dpu_caps, .ubwc = &sm6350_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm6350_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index f2808098af39..7bc86aa50e6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -92,6 +92,8 @@ static const struct dpu_perf_cfg qcm2290_perf_data = { }; const struct dpu_mdss_cfg dpu_qcm2290_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x5, .caps = &qcm2290_dpu_caps, .ubwc = &qcm2290_ubwc_cfg, .mdp_count = ARRAY_SIZE(qcm2290_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 241fa6746674..d92890f090d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -107,6 +107,8 @@ static const struct dpu_perf_cfg sm6375_perf_data = { }; const struct dpu_mdss_cfg dpu_sm6375_cfg = { + .core_major_version = 0x6, + .core_minor_version = 0x9, .caps = &sm6375_dpu_caps, .ubwc = &sm6375_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm6375_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 8da424eaee6a..8a2dc56c79f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -213,6 +213,8 @@ static const struct dpu_perf_cfg sm8350_perf_data = { }; const struct dpu_mdss_cfg dpu_sm8350_cfg = { + .core_major_version = 0x7, + .core_minor_version = 0x0, .caps = &sm8350_dpu_caps, .ubwc = &sm8350_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm8350_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 900fee410e11..bba7bdb9bd42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -154,6 +154,8 @@ static const struct dpu_perf_cfg sc7280_perf_data = { }; const struct dpu_mdss_cfg dpu_sc7280_cfg = { + .core_major_version = 0x7, + .core_minor_version = 0x2, .caps = &sc7280_dpu_caps, .ubwc = &sc7280_ubwc_cfg, .mdp_count = ARRAY_SIZE(sc7280_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index f6ce6b090f71..3f51b802b6b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -217,6 +217,8 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = { }; const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { + .core_major_version = 0x8, + .core_minor_version = 0x0, .caps = &sc8280xp_dpu_caps, .ubwc = &sc8280xp_ubwc_cfg, .mdp_count = ARRAY_SIZE(sc8280xp_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 8d13c369213c..20acff9db979 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -221,6 +221,8 @@ static const struct dpu_perf_cfg sm8450_perf_data = { }; const struct dpu_mdss_cfg dpu_sm8450_cfg = { + .core_major_version = 0x8, + .core_minor_version = 0x1, .caps = &sm8450_dpu_caps, .ubwc = &sm8450_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm8450_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index f17b9a7fee85..89fdf334a0aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -225,6 +225,8 @@ static const struct dpu_perf_cfg sm8550_perf_data = { }; const struct dpu_mdss_cfg dpu_sm8550_cfg = { + .core_major_version = 0x9, + .core_minor_version = 0x0, .caps = &sm8550_dpu_caps, .ubwc = &sm8550_ubwc_cfg, .mdp_count = ARRAY_SIZE(sm8550_mdp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b860784ade72..8b900be3ea90 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -796,8 +796,9 @@ struct dpu_perf_cfg { /** * struct dpu_mdss_cfg - information of MDSS HW * This is the main catalog data structure representing - * this HW version. Contains number of instances, - * register offsets, capabilities of the all MDSS HW sub-blocks. + * this HW version. Contains dpu's major and minor versions, + * number of instances, register offsets, capabilities of the + * all MDSS HW sub-blocks. * * @dma_formats Supported formats for dma pipe * @cursor_formats Supported formats for cursor pipe @@ -805,6 +806,9 @@ struct dpu_perf_cfg { * @mdss_irqs: Bitmap with the irqs supported by the target */ struct dpu_mdss_cfg { + u8 core_major_version; + u8 core_minor_version; + const struct dpu_caps *caps; const struct dpu_ubwc_cfg *ubwc; From patchwork Thu Jun 29 19:21:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 114405 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9876262vqr; Thu, 29 Jun 2023 12:56:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGnLs/0pQwKuT9DoLZ33/sfaYfNLUrVByZshUKLCHv0fIzXMGuESuHqluNlzCNC5eEpVqtn X-Received: by 2002:a05:6871:687:b0:1b0:927d:f5e with SMTP id l7-20020a056871068700b001b0927d0f5emr981399oao.53.1688068594996; Thu, 29 Jun 2023 12:56:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688068594; cv=none; d=google.com; s=arc-20160816; b=QTzQ14A+6olL2NS0r27d91diwD55+vK1xR5i1RppB0BREySp6urz1QmTqctwzdrZQ5 dMokJbDMhPfeX65VBj5EumL9LqK8VOwrocFK/MJ47wPQo8rkVx+VOxZ74cztM8KRM1tU MfcrGjl314XyTUtOwmqIos3y6n31twVr6HC67OMgmwYD1+YfToZwqbqra+aSVQBa+t+B m6wRoU0kL/v1jf8NOPaWH/WgQlJTKvxKi4jxA9pXo0JoKkOZUVvViY1yA7tem6k9On3E SrzTO5RDMNKl2T0zTjhxlYl2+FdYj+SMqGNqyl/VPFX+v03rdN4DR/NHAoeJCNCVRX7a xcjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+hWul2nekoDN8xRttv+Z7MLmGJ5cvGp4fmfxDkERFUQ=; fh=r+FpN7If8GWuIi7B8VdUbCtL0rBZiJimtUxfKchadqw=; b=W1FEweWSpyUlAn3e++ALpZzUThnpG8XPCIqULE5ZV0rjnMox6+nnAffyi9HqZMiMsB 6LX2p9koRCR0RdqUMwZOE16NOrsjlTNfFQ2rZaaGT7PiAe6n1Cp/0QkUVhQZwv7ticwt OGry+1NsDqWrKAZvafdb7SsQuCZlWok42gL9yHLu9uzaRmuStvyGk/e49pljtPa9poPG CTqcKn31K6fDQdgSGf3ezF1KpEFk8vCaBCvQWUxB0igOW62JvkHbwP/3ctSgi0hg6Y1N 3Ia5oSrsen5pS18U8AjO/L8CD4wQv/aI9KIrZZ7soeThJqs0h2ny+Qmg1/1u1g7lrbNr gYEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=hd24qcb4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This will avoid defining feature bits for every bit level details of registers. Also, rename the intf's enable_compression() op to program_datapath() and allow it to accept a struct intf_dpu_datapath_cfg to program all the bits at once. This can be re-used by widebus later on as well as it touches the same register. Signed-off-by: Abhinav Kumar --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 +++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 16 ++++++++++++++-- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b856c6286c85..f4e15b4c4cc9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( to_dpu_encoder_phys_cmd(phys_enc); struct dpu_hw_ctl *ctl; struct dpu_hw_intf_cfg intf_cfg = { 0 }; + struct dpu_kms *dpu_kms = phys_enc->dpu_kms; ctl = phys_enc->hw_ctl; if (!ctl->ops.setup_intf_cfg) @@ -68,8 +69,12 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( phys_enc->hw_intf, phys_enc->hw_pp->idx); - if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression) - phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf); + if (intf_cfg.dsc != 0 && dpu_kms->catalog->core_major_version >= 0x7) { + struct intf_dpu_datapath_cfg datapath_cfg = { 0 }; + + datapath_cfg.data_compress = true; + phys_enc->hw_intf->ops.program_datapath(phys_enc->hw_intf, &datapath_cfg); + } } static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 5b0f6627e29b..85333df08fbc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -513,11 +513,13 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, } -static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx) +static void dpu_hw_intf_program_datapath(struct dpu_hw_intf *ctx, + struct intf_dpu_datapath_cfg *datapath_cfg) { u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); - intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + if (datapath_cfg->data_compress) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); } @@ -543,8 +545,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh; } - if (cap & BIT(DPU_INTF_DATA_COMPRESS)) - ops->enable_compression = dpu_hw_intf_enable_compression; + ops->program_datapath = dpu_hw_intf_program_datapath; } struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 99e21c4137f9..f736dca38463 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -48,6 +48,11 @@ struct intf_status { u32 line_count; /* current line count including blanking */ }; +struct intf_dpu_datapath_cfg { + u8 data_compress; /* enable data compress between dpu and dsi */ + /* can be expanded for other programmable bits */ +}; + /** * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions * Assumption is these functions will be called after clocks are enabled @@ -70,7 +75,7 @@ struct intf_status { * @get_autorefresh: Retrieve autorefresh config from hardware * Return: 0 on success, -ETIMEDOUT on timeout * @vsync_sel: Select vsync signal for tear-effect configuration - * @enable_compression: Enable data compression + * @program_datapath: Program the DPU to interface datapath for relevant chipsets */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, @@ -108,7 +113,14 @@ struct dpu_hw_intf_ops { */ void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay); - void (*enable_compression)(struct dpu_hw_intf *intf); + /** + * Program the DPU to intf datapath by specifying + * which of the settings need to be programmed for + * use-cases which need DPU-intf handshake such as + * widebus, compression etc. + */ + void (*program_datapath)(struct dpu_hw_intf *intf, + struct intf_dpu_datapath_cfg *datapath_cfg); }; struct dpu_hw_intf { From patchwork Thu Jun 29 19:21:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 114402 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9875740vqr; Thu, 29 Jun 2023 12:55:24 -0700 (PDT) X-Google-Smtp-Source: APBJJlHvcm4L/Q8s8Pdr7Qimjk+dEKG1tNU4tCLa4FTl/KJHgu1hSxYj3CZrv+fG5rGxxYPMScFd X-Received: by 2002:a17:903:258f:b0:1b8:5541:9d4f with SMTP id jb15-20020a170903258f00b001b855419d4fmr114199plb.59.1688068523996; Thu, 29 Jun 2023 12:55:23 -0700 (PDT) ARC-Seal: i=1; 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Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0de507d4d7b7..35994e676450 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -105,7 +105,7 @@ BIT(DPU_INTF_STATUS_SUPPORTED) | \ BIT(DPU_DATA_HCTL_EN)) -#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)) +#define INTF_SC7280_MASK (INTF_SC7180_MASK) #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 8b900be3ea90..572e618150b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -181,7 +181,6 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register - * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -189,7 +188,6 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, - DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX };