From patchwork Thu Jun 29 07:51:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 114201 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9469762vqr; Thu, 29 Jun 2023 01:01:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4tJPmuwjnG83MxWm5QOoExFLaziw5lkNGuJpHSs6lrWdC7xj1nBYYEs8kRXiqKPdx/BpWC X-Received: by 2002:a05:6a20:8e19:b0:11a:efaa:eb88 with SMTP id y25-20020a056a208e1900b0011aefaaeb88mr46620767pzj.3.1688025711843; Thu, 29 Jun 2023 01:01:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688025711; cv=none; d=google.com; s=arc-20160816; b=w/nXE1kBSsKenLHk++JEPoOipEcrh8tucMlOlfU5x36rrNkSjDwyWlwJrAeJB1knyt uqE62VF5ec87zYXtIBgweT0DhAt0DDMweANVg7GGV+eYQcnEuThV7ORO9rZeGsO3OZHn CxiJJpr70XCPZvewfLr49Xne0oc+C6+RgQiMUH1O7h4WBhlEXNJqUUDoiGbj7afKBxF0 15gBQnvQYaHL0xXgqKZ7vHFgkFZGtPPxZpZnuiYX7vW5g+iviMYeKD0tmbAIeUPfus40 Jw9TjTJx9yiqzbtrWBv1LT2R8208xAfdGG96j3+F7tcHgrGnW+h3cKKOxgf692ZJIAGw joaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=U1AuiOsn2Q1STJ3ktNSQJuRVqppBEkzsGaOOi2TNlRI=; fh=eeODssFzCiLuj4Y2Poz4a1+JaBBLhhwnNU23JWsakRA=; b=M70B0vAuOpIqg7LLN/h9qZyXdL4GkHUhfHP0dEzSg8wUGWqFS2MorY3Hd/wn6niLdl HRxPhl03FroNYIpaYSp+HVG++UYXq50qrMo0sM3UDgXyOmk2nMthEir8UCxwwsjOOllu I13rOAeyxmWXvpjhZ5mFW2gLwUHdiFNnJYhdR37n3LNhycv5n+59Lm/bvHjuy2P5Mz+I xO7Us3UXePz/kc+NIopuARno2m2/X4PzuI/8v7Ea/N98o5sO/gtBeTwjoFPrsLZV5tp7 gS31yzxxHgRYkU845FcNgcS/WNSY3PlcmVgAsF7zoHlFcxNYE1bY2ncSFvF9vhI6D1CK 6UyA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ck9-20020a056a00328900b0066e4ceca38fsi9094759pfb.283.2023.06.29.01.01.29; Thu, 29 Jun 2023 01:01:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232066AbjF2Hx0 (ORCPT + 99 others); Thu, 29 Jun 2023 03:53:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232242AbjF2Hwl (ORCPT ); Thu, 29 Jun 2023 03:52:41 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63DB03AAE; Thu, 29 Jun 2023 00:51:20 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 5B76024E2D3; Thu, 29 Jun 2023 15:51:18 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:18 +0800 Received: from ubuntu.localdomain (183.27.97.206) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:17 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v8 1/5] dt-bindings: phy: Add StarFive JH7110 USB PHY Date: Thu, 29 Jun 2023 15:51:11 +0800 Message-ID: <20230629075115.11934-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com> References: <20230629075115.11934-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.206] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770023248877467715?= X-GMAIL-MSGID: =?utf-8?q?1770023248877467715?= Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Rob Herring Reviewed-by: Roger Quadros --- .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml new file mode 100644 index 000000000000..269e9f9f12b6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 USB 2.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-usb-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY 125m + - description: app 125m + + clock-names: + items: + - const: 125m + - const: app_125m + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x10200000 0x10000>; + clocks = <&syscrg 95>, + <&stgcrg 6>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; From patchwork Thu Jun 29 07:51:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 114200 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9469704vqr; Thu, 29 Jun 2023 01:01:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7RRBf/ksKQMldYZ0D1w3k9IyE1H3imOWA7S7W8rLqA0QqUXmBMM/xtaMy9+loKZGbqFX6/ X-Received: by 2002:a05:6a20:8f04:b0:121:b5af:acbc with SMTP id b4-20020a056a208f0400b00121b5afacbcmr40034113pzk.3.1688025705871; Thu, 29 Jun 2023 01:01:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688025705; cv=none; d=google.com; s=arc-20160816; b=fYaibKW0BhEHdwpA90uFg+amuw0QwH3sFI7r2vTVST7w+vWAUmpQE5Wh/2+G5dbNn6 ogKJAtkYxKefbROGqpgbCffWcH10xTvWO7QDAuu8RtIKIIazz5NnFaJsjvm8SReDQu/K 5PpHLsyd/rM+K4mdY8A5Aii1A2+jVVQvcIJq9tPbS8zdFVUb5Rt07NYPzZpERfWhXhdF OXPXq4ehAgJExhePoEPNlN4+Alam2uVnsxI5BCAVChRIfiXmHe4y2IRGqd3YtcsqZZ4r OgR3Bp6jmnlCxJ38Fbe2OUC8eZ57AiIuwz8baCv3NigNgQcxjnfK3nR9S8wrjKZTFKtJ OOpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=NyVTs5RjPALZKvNkaCYPugtlVkXNS4SU7khN7c9I9BI=; fh=eeODssFzCiLuj4Y2Poz4a1+JaBBLhhwnNU23JWsakRA=; b=Q5K5uP9Ddp4UJiAVJhpsu3z0Ei6XZXBaoKcxUQt+O5Q+LWD484QuQ7Kl0Uua5PMySI qZfCYmHNy2PgzYDoDaoteP27ErifOqwxkGb3OeQtuqtDpOXvvk33cyqQ71i6PNBgjlxu hIVftrG1/zBBWlOS8g8rzdCm08J3j1O3gSrjkm5fVB8mVdBtEaH+4Tkn3IVG2EXC4UWu KJE2BQR8uFxxlBqcImm4oNIA1VmzN8zHNRXRZMKmX/hsIxvxjHXamcTFF5ynsgc/jMFF qpoBl5npZI4JIM8aF91wwlDjV2AWq/ggS6s2DQBt56/DLnl59BcOk+xZz76YXYk/X2oL w3Rw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 34-20020a631662000000b005572b2f6ea2si9964462pgw.272.2023.06.29.01.01.18; Thu, 29 Jun 2023 01:01:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232144AbjF2Hx4 (ORCPT + 99 others); Thu, 29 Jun 2023 03:53:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232286AbjF2Hwn (ORCPT ); Thu, 29 Jun 2023 03:52:43 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEB883AB1; Thu, 29 Jun 2023 00:51:25 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 244F3807D; Thu, 29 Jun 2023 15:51:19 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:19 +0800 Received: from ubuntu.localdomain (183.27.97.206) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:18 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v8 2/5] dt-bindings: phy: Add StarFive JH7110 PCIe PHY Date: Thu, 29 Jun 2023 15:51:12 +0800 Message-ID: <20230629075115.11934-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com> References: <20230629075115.11934-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.206] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770023242179948421?= X-GMAIL-MSGID: =?utf-8?q?1770023242179948421?= Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Rob Herring Reviewed-by: Roger Quadros --- .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml new file mode 100644 index 000000000000..2e83a6164cd1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe 2.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller sys_syscon node. + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. + description: + The phandle to System Register Controller syscon node and the PHY connect offset + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon node. + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset. + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x10210000 0x10000>; + #phy-cells = <0>; + starfive,sys-syscon = <&sys_syscon 0x18>; + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; + }; From patchwork Thu Jun 29 07:51:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 114199 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9469582vqr; Thu, 29 Jun 2023 01:01:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7C6/HdoF99utTqO/6kG7OBCvTYJ5djuQyhs9CgrB5e4glV8mZOWGb1tw9rLxz1MnbasPPk X-Received: by 2002:a05:6602:3997:b0:783:63e8:3bfc with SMTP id bw23-20020a056602399700b0078363e83bfcmr10953903iob.0.1688025696264; Thu, 29 Jun 2023 01:01:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688025696; cv=none; d=google.com; s=arc-20160816; b=QVLD80fUGI5KCg906saMJFx/qt1bWS31HS6b7+zWN3OHJ8upxkxRnje3gKuqkL9CV+ sIqFgwn++GVdiFawXaaUouK72R+B4sgG9V4k5byjziSdd70k4uddHbdmY1gXwT7mHdLp N3/03NVrFaKdbGRqxFRjuLBIdsaZCpSI3nUCQRC3uEt/y8uGQzzJ8k1SNG1JHq7LdSP+ anihG7N4ygQcvl4ybt1oEfCXV/8AGdOGYpaQ0ly1f9f2IM666wYd3nbBupJmDKxVHfmD pyWgQvrBRQTDHAh5qEF/A0BZ/H1WiDGP8m8AmWdVCyu4H05as5g75TBPJr/lHmJVy53h aDhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=7TRKrf1zFdfYVAaGYQ9MPfyKrZSgJKQVxs8ggQojCCQ=; fh=eeODssFzCiLuj4Y2Poz4a1+JaBBLhhwnNU23JWsakRA=; b=zhp8nS+jKGMxTajc9ghDaImR+HRcuCt98IAab16rIaO0WEYvX3sE/qbImUiNYj6Zjy TMLfLOK84db1GCEnu9S6f9WUJiCSa6VMNg3dzulAIgVYYAzPmipZmVV8vuNZ5k9SOeuv bZtUzCkiUvio7Zf+ApTIPJteW87Zz0pdX12FYQt7TCLvwawCeFauvkTDbwoodGYZaMcM Wy/+H7axAlLavP/8Dh8Lx7YqI5HboVfCSaTi0vwUGWJmpwgK4EcDu0UwlDEvwEvV2AQr FiAo0vRhk5o144TM425r/HcvzcCuxnh4LT+F9UPYGYawFgpnDenKgcydPNappUcuuOZh kL1g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 30-20020a17090a001e00b0025eeb3cc4b2si10363741pja.9.2023.06.29.01.01.16; Thu, 29 Jun 2023 01:01:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232277AbjF2Hxn (ORCPT + 99 others); Thu, 29 Jun 2023 03:53:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232268AbjF2Hwm (ORCPT ); Thu, 29 Jun 2023 03:52:42 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14DDB2D7B; Thu, 29 Jun 2023 00:51:23 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id C7AF58082; Thu, 29 Jun 2023 15:51:19 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:19 +0800 Received: from ubuntu.localdomain (183.27.97.206) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:18 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v8 3/5] phy: starfive: Add JH7110 USB 2.0 PHY driver Date: Thu, 29 Jun 2023 15:51:13 +0800 Message-ID: <20230629075115.11934-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com> References: <20230629075115.11934-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.206] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770023232228408876?= X-GMAIL-MSGID: =?utf-8?q?1770023232228408876?= Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen Reviewed-by: Roger Quadros --- MAINTAINERS | 6 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 14 +++ drivers/phy/starfive/Makefile | 2 + drivers/phy/starfive/phy-jh7110-usb.c | 152 ++++++++++++++++++++++++++ 6 files changed, 176 insertions(+) create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c diff --git a/MAINTAINERS b/MAINTAINERS index f794002a192e..d2ce89a8d31c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20174,6 +20174,12 @@ S: Supported F: Documentation/devicetree/bindings/watchdog/starfive* F: drivers/watchdog/starfive-wdt.c +STARFIVE JH71X0 USB PHY DRIVER +M: Minda Chen +S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +F: drivers/phy/starfive/phy-jh7110-usb.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index f46e3148d286..0000149edbc4 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" source "drivers/phy/socionext/Kconfig" source "drivers/phy/st/Kconfig" +source "drivers/phy/starfive/Kconfig" source "drivers/phy/sunplus/Kconfig" source "drivers/phy/tegra/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 54f312c10a40..fb3dc9de6111 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -31,6 +31,7 @@ obj-y += allwinner/ \ samsung/ \ socionext/ \ st/ \ + starfive/ \ sunplus/ \ tegra/ \ ti/ \ diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig new file mode 100644 index 000000000000..65b5f879bbf9 --- /dev/null +++ b/drivers/phy/starfive/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for StarFive platforms +# + +config PHY_STARFIVE_JH7110_USB + tristate "Starfive JH7110 USB 2.0 PHY support" + depends on USB_SUPPORT + select GENERIC_PHY + help + Enable this to support the StarFive USB 2.0 PHY, + used with the Cadence USB controller. + If M is selected, the module will be called + phy-jh7110-usb.ko. diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile new file mode 100644 index 000000000000..52e9a09cc619 --- /dev/null +++ b/drivers/phy/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c new file mode 100644 index 000000000000..633912f8a05d --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-usb.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 USB 2.0 PHY driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_125M_CLK_RATE 125000000 +#define USB_LS_KEEPALIVE_OFF 0x4 +#define USB_LS_KEEPALIVE_ENABLE BIT(4) + +struct jh7110_usb2_phy { + struct phy *phy; + void __iomem *regs; + struct clk *usb_125m_clk; + struct clk *app_125m; + enum phy_mode mode; +}; + +static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) +{ + unsigned int val; + + /* Host mode enable the LS speed keep-alive signal */ + val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); + if (set) + val |= USB_LS_KEEPALIVE_ENABLE; + else + val &= ~USB_LS_KEEPALIVE_ENABLE; + + writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); +} + +static int usb2_phy_set_mode(struct phy *_phy, + enum phy_mode mode, int submode) +{ + struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + break; + default: + return -EINVAL; + } + + if (mode != phy->mode) { + dev_dbg(&_phy->dev, "Changing phy to %d\n", mode); + phy->mode = mode; + usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE)); + } + + return 0; +} + +static int jh7110_usb2_phy_init(struct phy *_phy) +{ + struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); + int ret; + + ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE); + if (ret) + return ret; + + ret = clk_prepare_enable(phy->app_125m); + if (ret) + return ret; + + return 0; +} + +static int jh7110_usb2_phy_exit(struct phy *_phy) +{ + struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); + + clk_disable_unprepare(phy->app_125m); + + return 0; +} + +static const struct phy_ops jh7110_usb2_phy_ops = { + .init = jh7110_usb2_phy_init, + .exit = jh7110_usb2_phy_exit, + .set_mode = usb2_phy_set_mode, + .owner = THIS_MODULE, +}; + +static int jh7110_usb_phy_probe(struct platform_device *pdev) +{ + struct jh7110_usb2_phy *phy; + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->usb_125m_clk = devm_clk_get(dev, "125m"); + if (IS_ERR(phy->usb_125m_clk)) + return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk), + "Failed to get 125m clock\n"); + + phy->app_125m = devm_clk_get(dev, "app_125m"); + if (IS_ERR(phy->app_125m)) + return dev_err_probe(dev, PTR_ERR(phy->app_125m), + "Failed to get app 125m clock\n"); + + phy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return dev_err_probe(dev, PTR_ERR(phy->regs), + "Failed to map phy base\n"); + + phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops); + if (IS_ERR(phy->phy)) + return dev_err_probe(dev, PTR_ERR(phy->phy), + "Failed to create phy\n"); + + phy_set_drvdata(phy->phy, phy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id jh7110_usb_phy_of_match[] = { + { .compatible = "starfive,jh7110-usb-phy" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match); + +static struct platform_driver jh7110_usb_phy_driver = { + .probe = jh7110_usb_phy_probe, + .driver = { + .of_match_table = jh7110_usb_phy_of_match, + .name = "jh7110-usb-phy", + } +}; +module_platform_driver(jh7110_usb_phy_driver); + +MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver"); +MODULE_AUTHOR("Minda Chen "); +MODULE_LICENSE("GPL"); From patchwork Thu Jun 29 07:51:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 114198 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9469569vqr; Thu, 29 Jun 2023 01:01:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ56M+Uv/dTkvKGuQF25cQNWNrPYldqLVBvM+SKb4ktYamZxnmDrNQ1Jc9w995D1w50WXONq X-Received: by 2002:a92:3645:0:b0:32a:eacb:c5d4 with SMTP id d5-20020a923645000000b0032aeacbc5d4mr31487010ilf.0.1688025695463; Thu, 29 Jun 2023 01:01:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688025695; cv=none; d=google.com; s=arc-20160816; b=jOQPnLnHI28PYunrNzcg5m4BRciXwh2o16p6SLqJECxVFGD9gBUbuOaExsZD8tsBYt g4Y4sdi3eWDuuaScIluTmi/hE3ymFnuASpcrbvA3jKm5xnPirNuDd+dBlbA8GW51S75L P/D756hCVn63fkZxQDlEMaehIl4EzL9hQMZdQSPnA4AqJ5qvOxJd7iO+jLPi4AGSxQo2 237q3vO7Se7gfvV3q/rfuC2wgAwWoJvnUA08Dm0ydOYd13VlPU0TgXGoM6mHxAdbOXEY 5D3rI+Yg+UMZ8b9jlTtkO7qUchdN0XQTPSgCwuuuoSfT7luyA0xW0gx00agANXa3joQ6 Bc0g== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g4-20020a636b04000000b005579d6bdf7esi8951366pgc.856.2023.06.29.01.01.18; Thu, 29 Jun 2023 01:01:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232446AbjF2Hxc (ORCPT + 99 others); Thu, 29 Jun 2023 03:53:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232258AbjF2Hwl (ORCPT ); Thu, 29 Jun 2023 03:52:41 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA9302D63; Thu, 29 Jun 2023 00:51:21 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 7B5C324E2D6; Thu, 29 Jun 2023 15:51:20 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:20 +0800 Received: from ubuntu.localdomain (183.27.97.206) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:19 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v8 4/5] phy: starfive: Add JH7110 PCIE 2.0 PHY driver Date: Thu, 29 Jun 2023 15:51:14 +0800 Message-ID: <20230629075115.11934-5-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com> References: <20230629075115.11934-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.206] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770023231679179571?= X-GMAIL-MSGID: =?utf-8?q?1770023231679179571?= Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen Reviewed-by: Roger Quadros --- MAINTAINERS | 4 +- drivers/phy/starfive/Kconfig | 10 ++ drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++++++++++++ 4 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index d2ce89a8d31c..b5d0a9e391bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20174,10 +20174,12 @@ S: Supported F: Documentation/devicetree/bindings/watchdog/starfive* F: drivers/watchdog/starfive-wdt.c -STARFIVE JH71X0 USB PHY DRIVER +STARFIVE JH71X0 PCIE AND USB PHY DRIVER M: Minda Chen S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c STATIC BRANCH/CALL diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index 65b5f879bbf9..da9a98cdf7e3 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -3,6 +3,16 @@ # Phy drivers for StarFive platforms # +config PHY_STARFIVE_JH7110_PCIE + tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" + depends on HAS_IOMEM + select GENERIC_PHY + help + Enable this to support the StarFive PCIe 2.0 PHY, + or used as USB 3.0 PHY. + If M is selected, the module will be called + phy-jh7110-pcie.ko. + config PHY_STARFIVE_JH7110_USB tristate "Starfive JH7110 USB 2.0 PHY support" depends on USB_SUPPORT diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index 52e9a09cc619..1c62d93e3280 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c new file mode 100644 index 000000000000..cbe79c1f59d3 --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-pcie.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 PCIe 2.0 PHY driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIE_KVCO_LEVEL_OFF 0x28 +#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c +#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 +#define PCIE_USB3_PHY_ENABLE BIT(4) +#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc + +#define USB_PDRSTN_SPLIT BIT(17) + +#define PCIE_PHY_MODE BIT(20) +#define PCIE_PHY_MODE_MASK GENMASK(21, 20) +#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) +#define PCIE_USB3_BUS_WIDTH BIT(3) +#define PCIE_USB3_RATE_MASK GENMASK(6, 5) +#define PCIE_USB3_RX_STANDBY_MASK BIT(7) +#define PCIE_USB3_PHY_ENABLE BIT(4) + +struct jh7110_pcie_phy { + struct phy *phy; + struct regmap *stg_syscon; + struct regmap *sys_syscon; + void __iomem *regs; + u32 sys_phy_connect; + u32 stg_pcie_mode; + u32 stg_pcie_usb; + enum phy_mode mode; +}; + +static int phy_usb3_mode_set(struct jh7110_pcie_phy *data) +{ + if (!data->stg_syscon || !data->sys_syscon) { + dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); + return -EINVAL; + } + + regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, + PCIE_PHY_MODE_MASK, PCIE_PHY_MODE); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_BUS_WIDTH_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE); + + /* Connect usb 3.0 phy mode */ + regmap_update_bits(data->sys_syscon, data->sys_phy_connect, + USB_PDRSTN_SPLIT, 0); + + /* Configuare spread-spectrum mode: down-spread-spectrum */ + writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); + + return 0; +} + +static void phy_pcie_mode_set(struct jh7110_pcie_phy *data) +{ + u32 val; + + /* default is PCIe mode */ + if (!data->stg_syscon || !data->sys_syscon) + return; + + regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, + PCIE_PHY_MODE_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_BUS_WIDTH_MASK, + PCIE_USB3_BUS_WIDTH); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_PHY_ENABLE, 0); + + regmap_update_bits(data->sys_syscon, data->sys_phy_connect, + USB_PDRSTN_SPLIT, 0); + + val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); + val &= ~PCIE_USB3_PHY_ENABLE; + writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); +} + +static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) +{ + /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ + writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); + writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); +} + +static int jh7110_pcie_phy_set_mode(struct phy *_phy, + enum phy_mode mode, int submode) +{ + struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy); + int ret; + + if (mode == phy->mode) + return 0; + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + ret = phy_usb3_mode_set(phy); + if (ret) + return ret; + break; + case PHY_MODE_PCIE: + phy_pcie_mode_set(phy); + break; + default: + return -EINVAL; + } + + dev_dbg(&_phy->dev, "Changing phy mode to %d\n", mode); + phy->mode = mode; + + return 0; +} + +static const struct phy_ops jh7110_pcie_phy_ops = { + .set_mode = jh7110_pcie_phy_set_mode, + .owner = THIS_MODULE, +}; + +static int jh7110_pcie_phy_probe(struct platform_device *pdev) +{ + struct jh7110_pcie_phy *phy; + struct device *dev = &pdev->dev; + struct phy_provider *phy_provider; + u32 args[2]; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops); + if (IS_ERR(phy->phy)) + return dev_err_probe(dev, PTR_ERR(phy->regs), + "Failed to map phy base\n"); + + phy->sys_syscon = + syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, + "starfive,sys-syscon", + 1, args); + + if (!IS_ERR_OR_NULL(phy->sys_syscon)) + phy->sys_phy_connect = args[0]; + else + phy->sys_syscon = NULL; + + phy->stg_syscon = + syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, + "starfive,stg-syscon", + 2, args); + + if (!IS_ERR_OR_NULL(phy->stg_syscon)) { + phy->stg_pcie_mode = args[0]; + phy->stg_pcie_usb = args[1]; + } else { + phy->stg_syscon = NULL; + } + + phy_kvco_gain_set(phy); + + phy_set_drvdata(phy->phy, phy); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id jh7110_pcie_phy_of_match[] = { + { .compatible = "starfive,jh7110-pcie-phy" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match); + +static struct platform_driver jh7110_pcie_phy_driver = { + .probe = jh7110_pcie_phy_probe, + .driver = { + .of_match_table = jh7110_pcie_phy_of_match, + .name = "jh7110-pcie-phy", + } +}; +module_platform_driver(jh7110_pcie_phy_driver); + +MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver"); +MODULE_AUTHOR("Minda Chen "); +MODULE_LICENSE("GPL"); From patchwork Thu Jun 29 07:51:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 114197 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9469565vqr; Thu, 29 Jun 2023 01:01:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4tXxBk2Oe4IXA3eeEUknjwJFk+yIMi3HGfyoFrCl/F8pCmfYQXwx1PfZJA8CKTrRfftptS X-Received: by 2002:a05:6a20:8426:b0:11f:7829:6d6c with SMTP id c38-20020a056a20842600b0011f78296d6cmr43280893pzd.3.1688025694813; Thu, 29 Jun 2023 01:01:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688025694; cv=none; d=google.com; s=arc-20160816; b=YRE9mCNHV+exLQhhA1I6Mdbu+LYRYCZ0BBoS9gzfeqq19A/ZTfCJfXSs3vswd/Ruvy RQKLoHXwBdj6S6RS1PzcuXWPNb8Qmjimmn6iogGMUvKHQaARVQXK0gyxNfOzOQl46SYp Is2voZlouvdf7HYLKEIq7FORYE90aqVi/tuY3yN+1m/miqdkK0vaKIPhIC4/amV+xsbI O/s+/dnRY9Rfhp4NwazSmj7uWhnq8/TRtgf1g2CA0mbXW1bLpU1z/MFkklS4YFcI8LrE +4O7yUDdXoHQvG+SWOH+5lljhsYuUZMilOWtAu3fWibYx/MUqVtBH17goYI6DuQ25dgQ ChOg== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id by8-20020a056a00400800b0067a4b6093a8si6059182pfb.29.2023.06.29.01.01.16; Thu, 29 Jun 2023 01:01:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232458AbjF2Hxh (ORCPT + 99 others); Thu, 29 Jun 2023 03:53:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232260AbjF2Hwl (ORCPT ); Thu, 29 Jun 2023 03:52:41 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1EB82D7C; Thu, 29 Jun 2023 00:51:22 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 5C91C24E2D7; Thu, 29 Jun 2023 15:51:21 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:21 +0800 Received: from ubuntu.localdomain (183.27.97.206) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 29 Jun 2023 15:51:20 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Roger Quadros CC: , , , , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Minda Chen , Mason Huo Subject: [PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110 Date: Thu, 29 Jun 2023 15:51:15 +0800 Message-ID: <20230629075115.11934-6-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com> References: <20230629075115.11934-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.206] X-ClientProxiedBy: EXCAS063.cuchost.com (172.16.6.23) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770023231345201748?= X-GMAIL-MSGID: =?utf-8?q?1770023231345201748?= Add PCIe PHY dts configuration for StarFive JH7110 SoC. PCIe0 PHY can be use as USB 3.0 PHY. Signed-off-by: Minda Chen Reviewed-by: Hal Feng --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..7e5c3ae83aa1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -353,6 +353,18 @@ status = "disabled"; }; + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>;