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[8.43.85.97]) by mx.google.com with ESMTPS id t23-20020a170906179700b00982930191b4si6557171eje.546.2023.06.28.19.52.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 19:52:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="CL6/Z3GJ"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 487C43858C2F for ; Thu, 29 Jun 2023 02:52:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 487C43858C2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688007124; bh=EbGZPH6+qexd71uNXD5/cAc/9Q+TXzGXJTb+RKWbE2U=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=CL6/Z3GJ03Q0hhzAJ0kOQPYD96Od748dIxIA8MSSLWPL6sRZwJvkSfMk8ei1iHlyM Z8+zNEO1sC22pBCtZIZBxr9Xfy0as5JGVU5tLPSsRA9AbmMIDgws8SSKayx2KhDo8Q +SE9efAtEE1bWkjcVY6WFgPfl40tbWIEPkC96oVc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 0A3F63858D35 for ; Thu, 29 Jun 2023 02:51:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0A3F63858D35 X-IronPort-AV: E=McAfee;i="6600,9927,10755"; a="448394450" X-IronPort-AV: E=Sophos;i="6.01,167,1684825200"; d="scan'208";a="448394450" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2023 19:51:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10755"; a="694478032" X-IronPort-AV: E=Sophos;i="6.01,167,1684825200"; d="scan'208";a="694478032" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 28 Jun 2023 19:51:06 -0700 Received: from shliclel4214.sh.intel.com (shliclel4214.sh.intel.com [10.239.240.214]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 93AEC1005153; Thu, 29 Jun 2023 10:51:05 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: refactor macros. Date: Thu, 29 Jun 2023 10:51:05 +0800 Message-Id: <20230629025105.1993837-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Hu, Lin1 via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: "Hu, Lin1" Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770003759542339217?= X-GMAIL-MSGID: =?utf-8?q?1770003759542339217?= Hi, all This patch aims to refactor macros in case some other thing is added to AMX_TILE_SET in future. OK for trunk? BRs, Lin gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AMX_INT8_SET): Change OPTION_MASK_ISA2_AMX_TILE to OPTION_MASK_ISA2_AMX_TILE_SET. (OPTION_MASK_ISA2_AMX_FP16_SET): Ditto (OPTION_MASK_ISA2_AMX_COMPLEX_SET): Ditto (OPTION_MASK_ISA_ABM_SET): Change OPTION_MASK_ISA_POPCNT to OPTION_MASK_ISA_POPCNT_SET. --- gcc/common/config/i386/i386-common.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index bf126f14073..4f79afba917 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -107,18 +107,18 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE #define OPTION_MASK_ISA2_AMX_INT8_SET \ - (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8) + (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8) #define OPTION_MASK_ISA2_AMX_BF16_SET \ - (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_BF16) + (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16) #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8 #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD #define OPTION_MASK_ISA2_AMX_FP16_SET \ - (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_FP16) + (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16) #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ - (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX) + (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -143,7 +143,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) #define OPTION_MASK_ISA_ABM_SET \ - (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) + (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET) #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD