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[8.43.85.97]) by mx.google.com with ESMTPS id q25-20020aa7d459000000b00518a604e243si5068336edr.20.2023.06.28.04.57.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 04:57:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C819B3857344 for ; Wed, 28 Jun 2023 11:56:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 0D77C3858D35 for ; Wed, 28 Jun 2023 11:56:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D77C3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1687953363tw54uyza Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 28 Jun 2023 19:56:01 +0800 (CST) X-QQ-SSF: 01400000000000G0S000000A0000000 X-QQ-FEAT: HXiF522FjMiLNZcVO05T26QrpmITftlPH3KniQijOLsLbZ802atsbV4YkTTZ2 S55TG3JlIrrF3SWZorTshbvIXT4TPhgIi+2jVZGXWZByB1YrkuPzR4BKoJLK7lc7vatB6R2 bEOp9J7TTgVqxt+A0Ut7sQJ6Hx1zELyjemsUZXx/+ktREOJBhMHmmVdosA++6I9u66sBau3 IPDvtJOBxnk7Bu3EwTyJT2NHZLWVk1Hc/weKbxVDs0K6vRKXNRMOaIbR2TwoWFsyG0mP4P0 Jb8JVxWtT6VYjmGQB7E08tlZU0TvBUJPBW5NajHenapC+lhDUviuD6h74KuJ3uY9iVJImdH QpDDxlKWyIUgR0JpeajOS4SIib2S6uB14JJFZo+oy8wwbj6tAnwl7CAAZcc1VrK6vbuaUl4 XEYwPtMRPQ9hFrAy8EQkwQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5225500469345516183 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering Date: Wed, 28 Jun 2023 19:55:59 +0800 Message-Id: <20230628115559.116166-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769947456823328947?= X-GMAIL-MSGID: =?utf-8?q?1769947456823328947?= Similar to vfwmacc. Add combine patterns as follows: For vfwnmsac: 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (reg) ))) 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (reg) ))) For vfwmsac: 1. (set (reg) (fma (float_extend (reg)) (float_extend (reg))) (neg (reg)) ))) 2. (set (reg) (fma (float_extend (reg)) (reg) (neg (reg)) ))) For vfwnmacc: 1. (set (reg) (fma (neg (float_extend (reg))) (float_extend (reg))) (neg (reg)) ))) 2. (set (reg) (fma (neg (float_extend (reg))) (reg) (neg (reg)) ))) gcc/ChangeLog: * config/riscv/autovec-opt.md (*double_widen_fnma): New pattern. (*single_widen_fnma): Ditto. (*double_widen_fms): Ditto. (*single_widen_fms): Ditto. (*double_widen_fnms): Ditto. (*single_widen_fnms): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen-10.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: New test. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: New test. --- gcc/config/riscv/autovec-opt.md | 182 ++++++++++++++++++ .../riscv/rvv/autovec/widen/widen-10.c | 22 +++ .../riscv/rvv/autovec/widen/widen-11.c | 22 +++ .../riscv/rvv/autovec/widen/widen-12.c | 22 +++ .../rvv/autovec/widen/widen-complicate-7.c | 27 +++ .../rvv/autovec/widen/widen-complicate-8.c | 27 +++ .../rvv/autovec/widen/widen-complicate-9.c | 27 +++ .../riscv/rvv/autovec/widen/widen_run-10.c | 32 +++ .../riscv/rvv/autovec/widen/widen_run-11.c | 32 +++ .../riscv/rvv/autovec/widen/widen_run-12.c | 32 +++ .../rvv/autovec/widen/widen_run_zvfh-10.c | 32 +++ .../rvv/autovec/widen/widen_run_zvfh-11.c | 32 +++ .../rvv/autovec/widen/widen_run_zvfh-12.c | 32 +++ 13 files changed, 521 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 1a1cef0eaa5..0c0ba685d6b 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -502,3 +502,185 @@ } [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [FP] VFWNMSAC +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfwnmsac.vv +;; ------------------------------------------------------------------------- + +;; Combine ext + ext + fnma ===> widen fnma. +;; Most of circumstantces, LoopVectorizer will generate the following IR: +;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41; +;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36; +;; vect__13.182_33 = .FNMA (vect__11.180_35, vect__8.176_40, vect__4.172_45); +(define_insn_and_split "*double_widen_fnma" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (match_operand:VWEXTF 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul_neg (PLUS, mode), + riscv_vector::RVV_WIDEN_TERNOP, operands); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) + +;; This helps to match ext + fnma. +(define_insn_and_split "*single_widen_fnma" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) + (match_operand:VWEXTF 3 "register_operand") + (match_operand:VWEXTF 1 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_extend (mode); + rtx tmp = gen_reg_rtx (mode); + rtx ext_ops[] = {tmp, operands[2]}; + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops); + + rtx dst = expand_ternary_op (mode, fnma_optab, tmp, operands[3], + operands[1], operands[0], 0); + emit_move_insn (operands[0], dst); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [FP] VFWMSAC +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfwmsac.vv +;; ------------------------------------------------------------------------- + +;; Combine ext + ext + fms ===> widen fms. +;; Most of circumstantces, LoopVectorizer will generate the following IR: +;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41; +;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36; +;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45); +(define_insn_and_split "*double_widen_fms" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul (MINUS, mode), + riscv_vector::RVV_WIDEN_TERNOP, operands); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) + +;; This helps to match ext + fms. +(define_insn_and_split "*single_widen_fms" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (match_operand:VWEXTF 3 "register_operand") + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_extend (mode); + rtx tmp = gen_reg_rtx (mode); + rtx ext_ops[] = {tmp, operands[2]}; + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops); + + rtx dst = expand_ternary_op (mode, fms_optab, tmp, operands[3], + operands[1], operands[0], 0); + emit_move_insn (operands[0], dst); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [FP] VFWNMACC +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfwnmacc.vv +;; ------------------------------------------------------------------------- + +;; Combine ext + ext + fnms ===> widen fnms. +;; Most of circumstantces, LoopVectorizer will generate the following IR: +;; vect__8.176_40 = (vector([2,2]) double) vect__7.175_41; +;; vect__11.180_35 = (vector([2,2]) double) vect__10.179_36; +;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45); +(define_insn_and_split "*double_widen_fnms" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_widen_mul_neg (MINUS, mode), + riscv_vector::RVV_WIDEN_TERNOP, operands); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) + +;; This helps to match ext + fnms. +(define_insn_and_split "*single_widen_fnms" + [(set (match_operand:VWEXTF 0 "register_operand") + (fma:VWEXTF + (neg:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand"))) + (match_operand:VWEXTF 3 "register_operand") + (neg:VWEXTF + (match_operand:VWEXTF 1 "register_operand"))))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_extend (mode); + rtx tmp = gen_reg_rtx (mode); + rtx ext_ops[] = {tmp, operands[2]}; + riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, ext_ops); + + rtx dst = expand_ternary_op (mode, fnms_optab, tmp, operands[3], + operands[1], operands[0], 0); + emit_move_insn (operands[0], dst); + DONE; + } + [(set_attr "type" "vfwmuladd") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c new file mode 100644 index 00000000000..490f1a41068 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \ + TYPE2 *__restrict a, \ + TYPE2 *__restrict b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] += -((TYPE1) a[i] * (TYPE1) b[i]); \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwnmsac\.vv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c new file mode 100644 index 00000000000..4d44a40fed3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \ + TYPE2 *__restrict a, \ + TYPE2 *__restrict b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = (TYPE1) a[i] * (TYPE1) b[i] - dst[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwmsac\.vv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c new file mode 100644 index 00000000000..2cb2a1edebf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwmacc_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \ + TYPE2 *__restrict a, \ + TYPE2 *__restrict b, \ + int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -((TYPE1) a[i] * (TYPE1) b[i]) - dst[i]; \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwnmacc\.vv} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c new file mode 100644 index 00000000000..2e3f6664d93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] += -((TYPE1) a[i] * (TYPE1) b[i]); \ + dst2[i] += -((TYPE1) a2[i] * (TYPE1) b[i]); \ + dst3[i] += -((TYPE1) a2[i] * (TYPE1) a[i]); \ + dst4[i] += -((TYPE1) a[i] * (TYPE1) b2[i]); \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwnmsac\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c new file mode 100644 index 00000000000..2acfbd01c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = (TYPE1) a[i] * (TYPE1) b[i] - dst[i]; \ + dst2[i] = (TYPE1) a2[i] * (TYPE1) b[i] - dst2[i]; \ + dst3[i] = (TYPE1) a2[i] * (TYPE1) a[i] - dst3[i]; \ + dst4[i] = (TYPE1) a[i] * (TYPE1) b2[i] - dst4[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwmsac\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c new file mode 100644 index 00000000000..da7f870c12b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include + +#define TEST_TYPE(TYPE1, TYPE2) \ + __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 ( \ + TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3, \ + TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b, \ + TYPE2 *__restrict a2, TYPE2 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = -((TYPE1) a[i] * (TYPE1) b[i]) - dst[i]; \ + dst2[i] = -((TYPE1) a2[i] * (TYPE1) b[i]) - dst2[i]; \ + dst3[i] = -((TYPE1) a2[i] * (TYPE1) a[i]) - dst3[i]; \ + dst4[i] = -((TYPE1) a[i] * (TYPE1) b2[i]) - dst4[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (float, _Float16) \ + TEST_TYPE (double, float) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvfwnmacc\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c new file mode 100644 index 00000000000..262660c5bcd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-10.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) + dst2##TYPE1[i]); + +#define RUN_ALL() RUN (double, float, -2147483648) + +int +main () +{ + RUN_ALL () +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c new file mode 100644 index 00000000000..246999cab62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-11.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]); + +#define RUN_ALL() RUN (double, float, -2147483648) + +int +main () +{ + RUN_ALL () +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c new file mode 100644 index 00000000000..2a6a03b5b35 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-12.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]); + +#define RUN_ALL() RUN (double, float, -2147483648) + +int +main () +{ + RUN_ALL () +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c new file mode 100644 index 00000000000..f678c35f81f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-10.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) + dst2##TYPE1[i]); + +#define RUN_ALL() RUN (float, _Float16, -32768) + +int +main () +{ + RUN_ALL () +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c new file mode 100644 index 00000000000..294f77dbc46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-11.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]); + +#define RUN_ALL() RUN (float, _Float16, -32768) + +int +main () +{ + RUN_ALL () +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c new file mode 100644 index 00000000000..013291cdc60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c @@ -0,0 +1,32 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ + +#include +#include "widen-12.c" + +#define SZ 512 + +#define RUN(TYPE1, TYPE2, LIMIT) \ + TYPE2 a##TYPE2[SZ]; \ + TYPE2 b##TYPE2[SZ]; \ + TYPE1 dst##TYPE1[SZ]; \ + TYPE1 dst2##TYPE1[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE2[i] = LIMIT + i % 8723; \ + b##TYPE2[i] = LIMIT + i & 1964; \ + dst##TYPE1[i] = LIMIT + i & 628; \ + dst2##TYPE1[i] = LIMIT + i & 628; \ + } \ + vwmacc_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (dst##TYPE1[i] \ + == -((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]) - dst2##TYPE1[i]); + +#define RUN_ALL() RUN (float, _Float16, -32768) + +int +main () +{ + RUN_ALL () +}