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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c190-20020a624ec7000000b005638baac87csi5013504pfb.64.2022.10.28.07.27.47; Fri, 28 Oct 2022 07:28:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vg9UKRm7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbiJ1OYr (ORCPT + 99 others); Fri, 28 Oct 2022 10:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230085AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E346BBEC; Fri, 28 Oct 2022 07:24:28 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOJJH023806; Fri, 28 Oct 2022 09:24:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967059; bh=6va/ClzjFNdP49/d45zL3g3+uNUzFUxFLB8Krcul1fc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vg9UKRm7mTVclNDLCroD9LohrXT/fWJDA9/6mrqKpSuGj7Wr5/pJXQWd3krFzjka/ dKrCq0WmPmytRsJZUAp8I96IZYlPpJMfRB/rT2wN78C9uhQo7sIa66oR45UpvWh9Qx AH8qMZ5vGZKSDh8g0Quyy/eWkQ0pg2qN69wGWuVQ= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOJE8030639 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:19 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:19 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:19 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfQ039275; Fri, 28 Oct 2022 09:24:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 01/11] arm64: dts: ti: k3-am65: Enable UART nodes at the board level Date: Fri, 28 Oct 2022 09:24:07 -0500 Message-ID: <20221028142417.10642-2-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941882888470415?= X-GMAIL-MSGID: =?utf-8?q?1747941882888470415?= UART nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++---- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 11 ++++++----- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 + .../boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ .../dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 4 ---- 7 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 32b7972375811..7b3087c19141c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -360,15 +360,13 @@ &wkup_uart0 { }; &main_uart1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; }; -&main_uart2 { - status = "disabled"; -}; - &mcu_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&arduino_uart_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 4005a73cfea99..ae414f5d83822 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -91,6 +91,7 @@ main_uart0: serial@2800000 { clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -99,6 +100,7 @@ main_uart1: serial@2810000 { interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -107,6 +109,7 @@ main_uart2: serial@2820000 { interrupts = ; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; crypto: crypto@4e00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 8d592bf41d6f1..bb70097693802 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -22,11 +22,12 @@ phy_gmii_sel: phy@4040 { mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + reg = <0x00 0x40a00000 0x00 0x100>; + interrupts = ; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_ram: sram@41c00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index fa11d7142006a..bbe31532f984b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -54,6 +54,7 @@ wkup_uart0: serial@42300000 { clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index 4a9bf7d7c07dc..cd43fd11a5c2c 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -50,6 +50,7 @@ AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */ }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 5850582dd4edf..956e9bc946b5f 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -271,7 +271,13 @@ &wkup_uart0 { status = "reserved"; }; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index d25e8b26187f9..0f67e1ec0fb86 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -50,7 +50,3 @@ &sdhci0 { ti,driver-strength-ohm = <50>; disable-wp; }; - -&main_uart0 { - status = "disabled"; -}; From patchwork Fri Oct 28 14:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12333 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863144wru; Fri, 28 Oct 2022 07:28:17 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5VYhQSCoAzHczseUo4LD9h9WAJbzwyhKN/5LGTUq8aEXPw3pH2jp0bEUXvZUWvLI4rqig1 X-Received: by 2002:a17:90a:7523:b0:213:8a69:c502 with SMTP id q32-20020a17090a752300b002138a69c502mr5029487pjk.153.1666967297129; Fri, 28 Oct 2022 07:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967297; cv=none; d=google.com; s=arc-20160816; b=ZuRT+Y4a5PmXA2srDqsqILU0SAoOFw1ha6hgQBZid3Tej3vikQsKUOcDexWqa47GyX yR+BPb3QWDKoP3qm7fnkqTJe2x13So/tmDBRs5M9Sq6snn2PJCpQ8ZAWBF23QngMsyBq 8rl0hTbzflGI9aYQHSGE/VCjYKKEGA/opnzmXxsr0gmlqYXl3J5X2JG0s2wn6sNvattp UTplJCZwKxC43TCk/9304NB0WRnm615tGL7RbWUk29z25nujZQyJUvL7qQkjttzTr5If 8N9c3V8WbsflsoE2ScM2iYnpKCEgKY9MBv4JBuArEAXHq0axkdwrmVzJ3AzxLDBrSXY/ FanQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id o15-20020a170902d4cf00b00186a2274394si6214196plg.476.2022.10.28.07.28.03; Fri, 28 Oct 2022 07:28:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=psHutzQQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230329AbiJ1OZD (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230175AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7A7BDC1; Fri, 28 Oct 2022 07:24:30 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOKkj023811; Fri, 28 Oct 2022 09:24:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967060; bh=w1yNXTvE43ZaEzGgh6+AWiVcnaERDNW2R/5yEFN79QI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=psHutzQQnE/p+rqh8G8UEvS/zjXpcZTYxEvCOIKCWwhRlcTgS9hv4PfzS3JZAYZS1 m276CPepwGsf1vsdUSG8NenRPMlL1J2mAuiFgVRBR8xU6SEdYl2ZSQJabOJRRwJmqT Sdn5UYZS+oAeeM3U9C/azV4UwUuuV6yA2D2glrSw= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOK9m030642 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:20 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:20 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:20 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfR039275; Fri, 28 Oct 2022 09:24:19 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 02/11] arm64: dts: ti: k3-am65: Enable I2C nodes at the board level Date: Fri, 28 Oct 2022 09:24:08 -0500 Message-ID: <20221028142417.10642-3-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941900645345848?= X-GMAIL-MSGID: =?utf-8?q?1747941900645345848?= I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 9 +++++++++ 5 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 7b3087c19141c..945a8a70332e9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -411,12 +411,14 @@ &db9_com_mode_pins_default }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; }; &mcu_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_i2c0_pins_default>; clock-frequency = <400000>; @@ -476,6 +478,7 @@ pcal9535_3: gpio@25 { }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -493,18 +496,21 @@ eeprom: eeprom@54 { }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ae414f5d83822..feef5fdb46886 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -159,6 +159,7 @@ main_i2c0: i2c@2000000 { clock-names = "fck"; clocks = <&k3_clks 110 1>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -170,6 +171,7 @@ main_i2c1: i2c@2010000 { clock-names = "fck"; clocks = <&k3_clks 111 1>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -181,6 +183,7 @@ main_i2c2: i2c@2020000 { clock-names = "fck"; clocks = <&k3_clks 112 1>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -192,6 +195,7 @@ main_i2c3: i2c@2030000 { clock-names = "fck"; clocks = <&k3_clks 113 1>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; ecap0: pwm@3100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index bb70097693802..dc0f439d2dacb 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -47,6 +47,7 @@ mcu_i2c0: i2c@40b00000 { clock-names = "fck"; clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_spi0: spi@40300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index bbe31532f984b..fd2b998ebddc4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -66,6 +66,7 @@ wkup_i2c0: i2c@42120000 { clock-names = "fck"; clocks = <&k3_clks 115 1>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; intr_wkup_gpio: interrupt-controller@42200000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 956e9bc946b5f..991a8559b4c3b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -284,6 +284,7 @@ &main_uart0 { }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; @@ -302,7 +303,13 @@ pca9554: gpio@39 { }; }; +&mcu_i2c0 { + status = "okay"; + /* Default pinmux */ +}; + &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -316,12 +323,14 @@ pca9555: gpio@21 { }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; From patchwork Fri Oct 28 14:24:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12339 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863284wru; Fri, 28 Oct 2022 07:28:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4Gl1egPhYoBoKWvWV5cZOUzfaKBGIG/JPOBcFgM7l7ORQh6a1s3fwEGqHWaX0O2grUABaN X-Received: by 2002:a17:907:2da6:b0:78d:3cf1:9132 with SMTP id gt38-20020a1709072da600b0078d3cf19132mr47305170ejc.299.1666967315179; Fri, 28 Oct 2022 07:28:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967315; cv=none; d=google.com; s=arc-20160816; b=09q5CcQQzmWlSlrggibjPh1MJGd+W0c4oXuI97TmGIshBDbuu+aYd3X4Qbd7B90TzP 01mrZbmET3eZ7kRcF2xLjmcazxBSz85dNrQbVWo5ONxlK+8Bc2ztaeZ4cD+aMsGUBRPn zMBvHoAd3itE2UMnSzifUFMqq3MFJQyZ+T2ndl/L6nAK0xOuyu+KwtiXVBkXcVQC3Mgz f7dKNG1GbQIiHVxdkc/+/WlYSKU7CzJrGLqJCfbSUcwYDZkMDovxavDb0rTtVeske80d ElS3vEd59Hoonyvnr8/HJqJJH20T0rLoqTrC2cYUmDd6AEilAKsoHmTMLPDvwsFDu0dE rODQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g20-20020a1709061e1400b00783d1a13d69si4074082ejj.231.2022.10.28.07.28.10; Fri, 28 Oct 2022 07:28:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Hq39yu6F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230177AbiJ1OZJ (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230181AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BE9FE41; Fri, 28 Oct 2022 07:24:31 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOLcl023819; Fri, 28 Oct 2022 09:24:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967061; bh=Co7awRy3Xz2XTZgEsm+7R4njsey9lJWTDZmbVB0K4DA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Hq39yu6FLWt48WmQL03y3it86mUiIZ5oyuizWMGPk10c4R3AHKWD9pycONUCF+5rt sYJsnBuVOeLI7pRkQHpUC6wfFei4SxSMXIgJlbD2g3GXFT0415j+0oSEEyS5/3klz+ ffYib+QAO80fnYa51zqlewEsHc3bWolCn2zgDrZ4= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOK6v062524 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:20 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:20 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:20 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfS039275; Fri, 28 Oct 2022 09:24:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 03/11] arm64: dts: ti: k3-am65: Enable SPI nodes at the board level Date: Fri, 28 Oct 2022 09:24:09 -0500 Message-ID: <20221028142417.10642-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941919567239496?= X-GMAIL-MSGID: =?utf-8?q?1747941919567239496?= SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 4 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 945a8a70332e9..fa4b6eb02fa57 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -574,6 +574,7 @@ &usb1 { }; &mcu_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_spi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index feef5fdb46886..74fd807d47396 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -217,6 +217,7 @@ main_spi0: spi@2100000 { #size-cells = <0>; dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@2110000 { @@ -229,6 +230,7 @@ main_spi1: spi@2110000 { #size-cells = <0>; assigned-clocks = <&k3_clks 137 1>; assigned-clock-rates = <48000000>; + status = "disabled"; }; main_spi2: spi@2120000 { @@ -239,6 +241,7 @@ main_spi2: spi@2120000 { power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi3: spi@2130000 { @@ -249,6 +252,7 @@ main_spi3: spi@2130000 { power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi4: spi@2140000 { @@ -259,6 +263,7 @@ main_spi4: spi@2140000 { power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index dc0f439d2dacb..7a11501bad0bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -58,6 +58,7 @@ mcu_spi0: spi@40300000 { power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi1: spi@40310000 { @@ -68,6 +69,7 @@ mcu_spi1: spi@40310000 { power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi2: spi@40320000 { @@ -78,6 +80,7 @@ mcu_spi2: spi@40320000 { power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; tscadc0: tscadc@40200000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 991a8559b4c3b..3f5a5ebfc8f3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -342,6 +342,7 @@ &ecap0 { }; &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; From patchwork Fri Oct 28 14:24:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12337 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863233wru; 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As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the EPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 74fd807d47396..49287f8493aea 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -886,6 +886,7 @@ ehrpwm0: pwm@3000000 { power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm1: pwm@3010000 { @@ -895,6 +896,7 @@ ehrpwm1: pwm@3010000 { power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm2: pwm@3020000 { @@ -904,6 +906,7 @@ ehrpwm2: pwm@3020000 { power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm3: pwm@3030000 { @@ -913,6 +916,7 @@ ehrpwm3: pwm@3030000 { power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm4: pwm@3040000 { @@ -922,6 +926,7 @@ ehrpwm4: pwm@3040000 { power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm5: pwm@3050000 { @@ -931,6 +936,7 @@ ehrpwm5: pwm@3050000 { power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; icssg0: icssg@b000000 { From patchwork Fri Oct 28 14:24:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12336 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863231wru; Fri, 28 Oct 2022 07:28:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6z7I6Hp9HH7OsiX3BgmU7xwBmkqXYkpz2Rji/+YqJ+Z+WykKalsTvNiNcaNm7gYnnGyFy+ X-Received: by 2002:a63:1a07:0:b0:46b:2825:f9cf with SMTP id a7-20020a631a07000000b0046b2825f9cfmr48381290pga.370.1666967306981; Fri, 28 Oct 2022 07:28:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967306; cv=none; d=google.com; s=arc-20160816; b=C0x30tCpaFx9qB6iakuxXx6Jkp7NQfPyy0bGtoh4pFkBSLTmKkPzUuu+0ocVWET1g3 xtA1xlNIKLf0QzQWXALM1ZLMgW5qngYkNlO4abwwKfTxtb8YsOqWM2wFmqb/3Y0N6ojQ tGmmcJMIHECZQRqH2++H2LsNewSzUslsN58kwAsh4EhDSEhHEEvV/4LaO6fKaOQYdPif QckX9v9dkmvSkPind2eB4iEcMllgB4rwSw/YkC/hJtAAewSHV9DjiB9cpEkyySv15AHi ccre0sFi5N9Skvv/7T/6piOJNYB8Nfja9CFqlQa8dSnsSjuF/avQwNc1BNIsKga8fkGa b90A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=We7DGZJnnN+asZSg5VkBuhvEFp1mF0S4GMcmYW01PCA=; b=zHP/Mwf1O94my+m0iyO/a5jhs7xfnbb3lyYnijVOCR60jp0QahjA3VKEdHHk8QWyJA 7ToqnRB/LGvjTkdPm9Mp3XGr9XAnrUwQWg+YRIRzlDK9zASbPiR1da7Q5v9hHLyl7GYx vWi4TjgXImcG25HUYJP4G3FhWuhc2GJ1wYipU/mHFADg4VOzZGoPfuEv4U8CZv59EVyd BtXbn2jqqx3s8kIeDzq+aVc91U68Sdk7q9N3nzv50PZfh0icG9vi0YIYT0QuO46lEelF ChoxrE7GEpymVpY4x17R5Qhmv8ZFuI8tr0H9eZquSGPGEnrP0ATpXRgUCyvvojc+ceG3 +VaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PacDIFXv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ne8-20020a17090b374800b002131407c208si4857953pjb.101.2022.10.28.07.28.13; Fri, 28 Oct 2022 07:28:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PacDIFXv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbiJ1OY6 (ORCPT + 99 others); Fri, 28 Oct 2022 10:24:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2064F19; Fri, 28 Oct 2022 07:24:32 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOMK3112733; Fri, 28 Oct 2022 09:24:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967062; bh=We7DGZJnnN+asZSg5VkBuhvEFp1mF0S4GMcmYW01PCA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PacDIFXvz9xUrvBomuz1seFlpdPav7uvAUG+poan0mXROh1wb8AHSIl6sGVDdjGQm rdzpMqyFc/5pQ6K0Ji3IGY6Bc7XMp8HvlQcdB4FkE/NBTJrfzhd8CQWJ2AvUJ1T/B2 LeH//mqxgtFtZLgj1kGPCI0NvYJ/Y/0reSUJRjTU= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOM37072883 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:22 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:21 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:22 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfU039275; Fri, 28 Oct 2022 09:24:21 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 05/11] arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level Date: Fri, 28 Oct 2022 09:24:11 -0500 Message-ID: <20221028142417.10642-6-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941910672588052?= X-GMAIL-MSGID: =?utf-8?q?1747941910672588052?= ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. (These and the EPWM nodes could be used to trigger internal actions but they are not used like that currently) As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the ECAP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index fa4b6eb02fa57..56562081a8e52 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -550,6 +550,7 @@ &mcu_cpsw { }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 49287f8493aea..fbb631c7664d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -205,6 +205,7 @@ ecap0: pwm@3100000 { power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 39 0>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 3f5a5ebfc8f3c..f4b8747ebaef6 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -337,6 +337,7 @@ &main_i2c2 { }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; From patchwork Fri Oct 28 14:24:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12345 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp864172wru; Fri, 28 Oct 2022 07:30:33 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4UBKkjF4VCkgc8RnCmlKGTLUhDfyM/WcGBy8Aa5Pwd2AyjPkTjpaOyf0/Wyg3QZvUO+cYx X-Received: by 2002:a62:5587:0:b0:56a:fd45:d15c with SMTP id j129-20020a625587000000b0056afd45d15cmr37275748pfb.33.1666967433266; Fri, 28 Oct 2022 07:30:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967433; cv=none; d=google.com; s=arc-20160816; b=Hw9Xel5ynebKl1pspJ1AH2M7lLFlF2k6ohPAwmCLnHnuKky6hBlBxTNg8Oe8TYJ/oS NEWeUCiB8fV7r+N413XY0A05Vv3SwYXz7eOHVMHPVsskQUASh1MXyoYrNjSeTo8Cvhwz dx2+fOGgtwEYyfj0HsojSlAEaZo9VgKg7wGtP/Np/boZ6SnK2mTFn79jNVm2R9I5DN12 ZEZFn1xSClMLRYzgx0GgSrakRyp3MovNIykREA+JX1VHbnU6OVKsJ2o6B8QfbeVe4hZr BXFTil9v+nXxw6YZE4dRIOTfpu7ixfnY0TdmoXYogK5z89kqMztcaPBMMJCXp1lL69Le m4ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/kPqQlZdcsUhjWCP7KPJkrqubvgGKg+hME77pCNOlPM=; b=0NC0YVMnRHGJY+FBhoEa7sqb9B/LGU332LludQwUfkScaLDFKpS1cKrnQDeLcEKixh qhKbl0L6QMDMEe/ZzNwzdWcwq6bLqY6ZTqnJvB/lpwgNG9J1Ke97OQea2ia2XXlJNrNd UrN5C6shM34dfjFKS+gUWV9npT85v3VtBZTs33PWbqhmUJ5OuPg4Hq9NL6HFuwUwJZ1K 73BJhQYbZb4iidv2VKVDw1rcXbnyhwZemT2KA9NH5V0WIpgLhiJrjkVU9l9nFAyvySF1 cRSIqpKiPOje4HoJDiTlrSR0DhuO42MPVqmahQjcJy48yxJOayUhiRPTu969mgpb7LiD eiTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TLrhqLlL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q20-20020a170902e31400b0018701f083b1si462026plc.619.2022.10.28.07.30.19; Fri, 28 Oct 2022 07:30:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TLrhqLlL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230515AbiJ1OZP (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230226AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB775DE6; Fri, 28 Oct 2022 07:24:30 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOMfa023825; Fri, 28 Oct 2022 09:24:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967062; bh=/kPqQlZdcsUhjWCP7KPJkrqubvgGKg+hME77pCNOlPM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TLrhqLlL4XzL7AhYHvKbfGCyZJJ5rrtQP3FBHmI01PzIZIpH8t6nHVyGJEm7eMfKJ 8r2IyPw6EqTiEX0r8gq8/YJbbe1HmsoACbPOJ83exfajd5dUlAB89/YKERYqzBciah 2KgJYvENdyqaow6I4CL1uHT2g1i3SHHVxjECcBkw= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOMBW072889 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:22 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:22 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfV039275; Fri, 28 Oct 2022 09:24:21 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 06/11] arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node Date: Fri, 28 Oct 2022 09:24:12 -0500 Message-ID: <20221028142417.10642-7-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747942043416662916?= X-GMAIL-MSGID: =?utf-8?q?1747942043416662916?= Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be controlled by the MDIO node (so if it was to be disabled for instance, the pinmux state would reflect that). Move the MDIO pins pinmux to the MIDO nodes. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index f4b8747ebaef6..0c63c24941061 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -529,10 +529,13 @@ flash@0 { &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>; }; &davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; From patchwork Fri Oct 28 14:24:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12334 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863206wru; Fri, 28 Oct 2022 07:28:23 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6bnhfzv/qDgEVLpuBxxnX3P4vnQIZ3R0pSbhitQ1mmgXtWX5zK70CGSG1sSf8QKP0H9o6S X-Received: by 2002:a17:90a:d70a:b0:213:8550:730e with SMTP id y10-20020a17090ad70a00b002138550730emr5976445pju.24.1666967303620; Fri, 28 Oct 2022 07:28:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967303; cv=none; d=google.com; s=arc-20160816; b=0uXwTFp08KMxKmaXx+bhW2N8pwMptPIjrQXxE5ROlOU6aoXSG64ZhO0TJlqVBftXrF /2Er9HMWhELWRWVuNk0QNMxCtTcKnYc+ftSGqbtr1P0346lCdDdGVV0Wz9rb5Z+GdMP2 F6wyvNQgEMOuPjGny1OvuxP1ulqb0BoPww1X9n9ySyPUYky2NS9hbeZ1ls+ExvCVJ32G uryaj0F/t8lwRc3SAaxvok/YeeDUNxhAu8d3ruGlxv1AHvzF3ANfJZUNxLyLQG0LrD98 ZT4vcnTwaL3pic7n0yXMK3s/YQcqozvSofg7QGg8mggxMpFvwOovaP6v9ux3r6jukgo3 edZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gZqEQtkesmyNbNaasIHOgX/OyIna1jM9BnRdk48NLkE=; b=b4Kb/dvh6yrdg8Ll4h09tqd5pMTMSC/czEFP4ygjWmM6CjKW/ZAM/uyZKNGkdVCLg5 25HLB0lVMNCfCjPSHU9MKdeZ7XKuOUlXS0c13quG3r4TKpZb7TYqJFQ0NaNdIQkp70zp iS+l4GWl2yUVhkSCPjHdsLJVx0M+RCKMWDRezfsYNvC3Jn4b3XBVbLrTDB1J9gPY7bUD JlAhIdo/9cpGQ2oHdrGdO4g0g8vOA5vVVAw33u93pcWfcu7CLST7V0sOYMFkvT3c16GK p4i03fz+vrNAdlOu0hPkRJMBANZ+7asQ/R31dXfWKvYXC6m7h2NrMUSmBfE9sGFx2QXH DW2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iM8FPHNl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ------------ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 13 +------------ 4 files changed, 5 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 56562081a8e52..35af8798f208e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -732,18 +732,6 @@ &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&icssg2_mdio { - status = "disabled"; -}; - &mcasp0 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fbb631c7664d2..9cdde6e25e7de 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1078,6 +1078,7 @@ icssg0_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1219,6 +1220,7 @@ icssg1_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1360,6 +1362,7 @@ icssg2_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 7a11501bad0bc..22f30174621e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -278,6 +278,7 @@ davinci_mdio: mdio@f00 { clocks = <&k3_clks 5 10>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0c63c24941061..beac2c563e831 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -533,6 +533,7 @@ &mcu_cpsw { }; &davinci_mdio { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mdio_pins_default>; @@ -563,15 +564,3 @@ &mcasp2 { &dss { status = "disabled"; }; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&icssg2_mdio { - status = "disabled"; -}; From patchwork Fri Oct 28 14:24:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12340 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863299wru; Fri, 28 Oct 2022 07:28:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7K9dA29vy7eolUQTugj39QThkvOAtl8dN2SIril3RskC0BERbgeKzo28MwMs6myrLxNid+ X-Received: by 2002:a05:6402:2793:b0:462:39d7:3bbc with SMTP id b19-20020a056402279300b0046239d73bbcmr15959938ede.47.1666967317520; Fri, 28 Oct 2022 07:28:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967317; cv=none; d=google.com; s=arc-20160816; b=ArLq461/J7lo99lyTc7wMlx8K8+oIEUT6P90AJUxAS8ufr9kMIxew53qxmMoGrG01/ RRpAtxCfP29apMv3VJBUe/XMn1zzmPQJVA55NKE7EZTfVx9TyOLbZ/q9jzmsPOHKADeC nvycJoEcxw+F8iCOJS67ddL0Ajp1kP9XYALyqERkjYXJaen/KSs6Bz8g10jlE2PpqjKF FSqjLdWl+YAzHXen7wblIjilXrJ8SyKDTvhkpXCswy+AakUPNWoM2auu84WdOAhXFBds ZSpZ5rzDJ8MNiidvljvbQPhcSzrycRdguoLAhFOo71JuPWaT1wy1FTU6wny2oti9qpH5 bylQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XblxHme2I1/9BjL7cSQ0qB05D+8VlqfedcTr4tTCMV8=; b=sGrCghsx0uUxwakoIMXsftZKD6kPSb3sOMJ91sG88QD55EYZFH486cAZvpeW8oqBoy sQ6hd3RPiuZzNeTJze7Bi+uccO474Mq+TZAo3ALfRYNSeaM0N7jDG0pOo0yUPp3WZV4l sSHrLYEi9Tdy5FkAdlVFLiEe1/DaIJ1/DOLyOVap0wYO6nPwJyI7XB8RB0TDRXBd66sJ 1D2jZGD+mV+VLjBAtumJXxHQUKDCdPo4JywwOt130cRYZRnfXmkyD/KTTVpqHRjdSgnt /JuThicPNNFQRs5PJA3dEHqBeWlf6JAf6cy+Y8E+UZ86V/YkaTTHEX3RquIWbc+4i3jR H+Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vJGA5udZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d7-20020a170906040700b007aa35038c6bsi3821305eja.463.2022.10.28.07.28.13; Fri, 28 Oct 2022 07:28:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vJGA5udZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231150AbiJ1OZU (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230230AbiJ1OYi (ORCPT ); Fri, 28 Oct 2022 10:24:38 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445AFEA9; Fri, 28 Oct 2022 07:24:32 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOO13026566; Fri, 28 Oct 2022 09:24:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967064; bh=XblxHme2I1/9BjL7cSQ0qB05D+8VlqfedcTr4tTCMV8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vJGA5udZVWPDEl0PhgKIpWOyucnnhZUGGvf6RbZlPs5Mkz+15SNEK4ashjtGbah2u ylArqUwAReI6mOd1YGxSBXWzXPdmWkd5n9XGkgsJ1tqj1cR6kp3Ie9gLh5qGo5filK f8+gpHBtJIvGTUsZ4q5V03CI2vD+3/KLeRCHvu5A= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOOqY072899 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:24 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:23 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:23 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfX039275; Fri, 28 Oct 2022 09:24:23 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 08/11] arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level Date: Fri, 28 Oct 2022 09:24:14 -0500 Message-ID: <20221028142417.10642-9-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941921959042267?= X-GMAIL-MSGID: =?utf-8?q?1747941921959042267?= MCAN nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 8 -------- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 -------- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 35af8798f208e..c431d670757ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -650,14 +650,6 @@ &pcie1_rc { reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - &pcie1_ep { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 22f30174621e2..9ceae8a5b7e2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -177,6 +177,7 @@ m_can0: mcan@40528000 { ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; m_can1: mcan@40568000 { @@ -192,6 +193,7 @@ m_can1: mcan@40568000 { ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; fss: fss@47000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index beac2c563e831..bf6a6fe3d7ba3 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -431,14 +431,6 @@ &pcie1_ep { status = "disabled"; }; -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - &mailbox0_cluster0 { interrupts = <436>; From patchwork Fri Oct 28 14:24:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12343 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863874wru; Fri, 28 Oct 2022 07:29:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5CBC/xoAjN9+5lnOzRETrAqnuv9FldihcjRV/E3B52B9C0PqXUYsWd1hEnHiwXaalJMn4v X-Received: by 2002:a17:902:e952:b0:17c:2eee:c0ce with SMTP id b18-20020a170902e95200b0017c2eeec0cemr54935234pll.145.1666967387917; Fri, 28 Oct 2022 07:29:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967387; cv=none; d=google.com; s=arc-20160816; b=SDgDQC95PIq0hDWNIILLjmZv96SD0sEXK0mPl3RsHASdGSAKJh5tWXzDR7YIxMMDxe F6+LPB/RlhWAoJrzRvudI6oBAXwSjmLbDciwD5wZN7QuI4zviQdSLOrjnT18wBhgZNib N/IeaWipSlSqHIOYoady14ZYUoMaA+1poqdSMQ3elynkaQq6RTlMmhMfmHWgX6UDckmK KApdwLz2Y/fBkB8VNMGL1NosnHi6Y8kKRwd8tuZtM2BzH5WWbscH2Fq7WZ3TNolpKvhB NHl2cdEqv1qAUYh3htxQ7zdFOviMsPM7Uew2chhzbno0sXHiaU65BxAkk0RlToyxzNTT 6ubg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=thI8gY7TszK4NMBgRo4Ut9XjHt2FFaPnIVg5c5tAsmU=; b=NzU7Ly+3kAbKaKpVUtfbOpes8DyNPtteIyb6XuMKoKgmLB/5ydw09RvyKvEXbDaC1X oogXAXy4C1b9hTpl6unJ7A80XLWj4DIMI4v5nrf7khHaSNbiHzNiRM3yC9dUYx4YjNje y1SsDXfPjU9aF5ZgJqzeROEkrrtdP70FZ8CoeybJsenI5Gu4iHrf7rvp5DMMF9rT9Frk Xm3h8HHTHiOp9SKnPaYiWTBm/35vGoaPdKCPpm5rhk9+80LtM7tJyzrxHMCIalLviVA7 1XCrS8yoDuZMXZBHmMTw8u3eaNNWvCzPILuWWD1dA38I6doNG/q6RrMekwno0HiF1swY nqjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jAW/ANC/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o5-20020a056a001bc500b00544ce272399si5411611pfw.173.2022.10.28.07.29.34; Fri, 28 Oct 2022 07:29:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="jAW/ANC/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbiJ1OZd (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230238AbiJ1OYj (ORCPT ); Fri, 28 Oct 2022 10:24:39 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CC77F1C; Fri, 28 Oct 2022 07:24:33 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOOR6026570; Fri, 28 Oct 2022 09:24:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967064; bh=thI8gY7TszK4NMBgRo4Ut9XjHt2FFaPnIVg5c5tAsmU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jAW/ANC/7+nwS8jbx3d878PgBXoPxQ4/mykKWVa8QXIA5U9pbsquYRr0XjA4IHwQT Cgm9u0z/ZWniGzxLFfLVCM6mArlEMk0kd2x6dM1OQNIFHY+7LcGfyvX376vnNGjWY/ hvV8KaOEcQjQxnrZkuH3sfpJmVoQsPUX5hoc37gQ= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOOlr062546 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:24 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:24 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:24 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfY039275; Fri, 28 Oct 2022 09:24:23 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 09/11] arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level Date: Fri, 28 Oct 2022 09:24:15 -0500 Message-ID: <20221028142417.10642-10-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941995906800092?= X-GMAIL-MSGID: =?utf-8?q?1747941995906800092?= PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 13 +------------ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ---------------- 3 files changed, 5 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index c431d670757ba..dd7c6aee8c613 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -632,15 +632,8 @@ dpi_out: endpoint { }; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins_default>; @@ -650,10 +643,6 @@ &pcie1_rc { reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&pcie1_ep { - status = "disabled"; -}; - &mailbox0_cluster0 { interrupts = <436>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 9cdde6e25e7de..9081c791a3123 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -720,6 +720,7 @@ pcie0_rc: pcie@5500000 { interrupts = ; msi-map = <0x0 &gic_its 0x0 0x10000>; device_type = "pci"; + status = "disabled"; }; pcie0_ep: pcie-ep@5500000 { @@ -733,6 +734,7 @@ pcie0_ep: pcie-ep@5500000 { max-link-speed = <2>; dma-coherent; interrupts = ; + status = "disabled"; }; pcie1_rc: pcie@5600000 { @@ -753,6 +755,7 @@ pcie1_rc: pcie@5600000 { interrupts = ; msi-map = <0x0 &gic_its 0x10000 0x10000>; device_type = "pci"; + status = "disabled"; }; pcie1_ep: pcie-ep@5600000 { @@ -766,6 +769,7 @@ pcie1_ep: pcie-ep@5600000 { max-link-speed = <2>; dma-coherent; interrupts = ; + status = "disabled"; }; mcasp0: mcasp@2b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index bf6a6fe3d7ba3..a61060c6bc198 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -415,22 +415,6 @@ &serdes1 { status = "disabled"; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - &mailbox0_cluster0 { interrupts = <436>; From patchwork Fri Oct 28 14:24:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 12338 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp863255wru; Fri, 28 Oct 2022 07:28:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6Kiu7vdTEEKP0o3SxZRfVDkTH7a5y2fYsttdZdiNXvo2rJkUSsgGubkwVBfivhTv03nbRt X-Received: by 2002:a17:90b:190f:b0:211:5d2a:ade9 with SMTP id mp15-20020a17090b190f00b002115d2aade9mr17148010pjb.76.1666967310973; Fri, 28 Oct 2022 07:28:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666967310; cv=none; d=google.com; s=arc-20160816; b=bWkTrsahHAzr9tQ94PwSKLWTr+FqR/FWt680gfwaiWSNPgQx1Wso9m6FTzMimmnstd jxrE2+eQR9XM5J/S9vU1qvMA9/0LUqcnodX3UQCIcg64lvvwAzIEpxFbCQdEvRUzGSnj LoY8NvfCD/iFCx74zBzN6M2eTYkHOXvwhpP00ooUf088wRT5FBYDPw0N7f6Gft+2fIT1 Qj6tsPxvnyZzxLjwPBemUnoImBpYH63szC8lPgfiyKEowPvxUNGXAzbMgj5exBdeK1kq 1XSTGFRiExXC+Y44ytrjiQfAgiYQszOPeqx/efCgzvRSqmdPCziM5yA8GzI6CVZAVBXv XviA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2LMWQyP+bgjUmm7WcOjgs5fr29QpsF7kVkLDaI7K+YQ=; b=u374+fbwgvLIZmvvnxyFEoqbLJLb/TiTagqyLz0SayaWLlINqJ3rZa0CW6J+TsoJgF 67xHbD71UfIOCrpHWLM6haMMnPKVyx3PXNh0wR6vB4J2nrTCW/y5xoQQquURiqP/lUe8 yAkbPYLr/1ePMAim1BKK5gsVuRjv54qSSr5GPawTYOrce9zome7/6F4kM+VSFoohLqtR fM1ROOEaxh51UyFoFRv9tmS1kvMdkEgIhQRXq2lEWbGRLbBiGHc9AidzTEsNg9NxFZ/Y /UUceOhO/2XEfqgm0h1q+y1tj3voDvl5p/E65vsfhfdDiRlBofGPajthsBjXpglF1ija R0yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cih8tGxT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 26-20020a63105a000000b0043a20d57b46si5441754pgq.826.2022.10.28.07.28.17; Fri, 28 Oct 2022 07:28:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cih8tGxT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231182AbiJ1OZ3 (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbiJ1OYj (ORCPT ); Fri, 28 Oct 2022 10:24:39 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07246F4A; Fri, 28 Oct 2022 07:24:33 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOPQP112739; Fri, 28 Oct 2022 09:24:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967065; bh=2LMWQyP+bgjUmm7WcOjgs5fr29QpsF7kVkLDaI7K+YQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cih8tGxTRFthtrNp5VVFRR2hECktZ6RmLsO5s0vFW4GC9K50V2PqTWJrRPwDwovSv aIriggGBknPQ5hQz2z0b3QQknDqmSrv4DhT53EV5smIbkeOKbAdeqzAeZD+Z6k/MDB aMlS/wCvJ7+4T8hErIBuvBiXbdeyJT8Rj9E6eceQ= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOP2d045505 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:25 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:25 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfZ039275; Fri, 28 Oct 2022 09:24:24 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 10/11] arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level Date: Fri, 28 Oct 2022 09:24:16 -0500 Message-ID: <20221028142417.10642-11-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747941915227848799?= X-GMAIL-MSGID: =?utf-8?q?1747941915227848799?= Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 42 +------------------ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 ++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 42 +------------------ 3 files changed, 16 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index dd7c6aee8c613..c6c79dde79c52 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -644,6 +644,7 @@ &pcie1_rc { }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -653,6 +654,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -661,46 +663,6 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 9081c791a3123..3dc624a379c5f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -514,6 +514,7 @@ mailbox0_cluster0: mailbox@31f80000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -523,6 +524,7 @@ mailbox0_cluster1: mailbox@31f81000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -532,6 +534,7 @@ mailbox0_cluster2: mailbox@31f82000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -541,6 +544,7 @@ mailbox0_cluster3: mailbox@31f83000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -550,6 +554,7 @@ mailbox0_cluster4: mailbox@31f84000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -559,6 +564,7 @@ mailbox0_cluster5: mailbox@31f85000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -568,6 +574,7 @@ mailbox0_cluster6: mailbox@31f86000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -577,6 +584,7 @@ mailbox0_cluster7: mailbox@31f87000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -586,6 +594,7 @@ mailbox0_cluster8: mailbox@31f88000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -595,6 +604,7 @@ mailbox0_cluster9: mailbox@31f89000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -604,6 +614,7 @@ mailbox0_cluster10: mailbox@31f8a000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -613,6 +624,7 @@ mailbox0_cluster11: mailbox@31f8b000 { ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; ringacc: ringacc@3c000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index a61060c6bc198..d1c8047d96726 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -416,6 +416,7 @@ &serdes1 { }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -425,6 +426,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -433,46 +435,6 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h10-20020a170902f54a00b00186b6a32284si6203070plf.548.2022.10.28.07.30.26; Fri, 28 Oct 2022 07:30:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ykEX2V7t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230454AbiJ1OZi (ORCPT + 99 others); Fri, 28 Oct 2022 10:25:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230241AbiJ1OYj (ORCPT ); Fri, 28 Oct 2022 10:24:39 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A03010B1; Fri, 28 Oct 2022 07:24:36 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOQ1q008177; Fri, 28 Oct 2022 09:24:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666967066; bh=1sNW9NejH8BybzwsPnUBsHJrG4Y80shP3LjdJoV0xME=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ykEX2V7tPwJ31D4VDkp+XiNC+uQ5i3Z1TccnEXqhcAP9suyeEStN9XYHhjezOMht4 Qbs+nRvhKw4JC+37kbCDHR1OOLDRpOgx2V3158yWKD1+t25X19qlq9dXDxiio7O+NP 8dUQ8KXpfUqSoiGcyJZoyiePovPjVQADvSh82HQQ= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29SEOQTO030672 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Oct 2022 09:24:26 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Fri, 28 Oct 2022 09:24:25 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Fri, 28 Oct 2022 09:24:25 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29SEOHfa039275; Fri, 28 Oct 2022 09:24:25 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , Le Jin , Jan Kiszka , CC: , , Andrew Davis Subject: [PATCH 11/11] arm64: dts: ti: k3-am65: Enable McASP nodes at the board level Date: Fri, 28 Oct 2022 09:24:17 -0500 Message-ID: <20221028142417.10642-12-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028142417.10642-1-afd@ti.com> References: <20221028142417.10642-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747942052304524841?= X-GMAIL-MSGID: =?utf-8?q?1747942052304524841?= McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the McASP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ------------ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ------------ 3 files changed, 3 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index c6c79dde79c52..3cced26b520a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -674,15 +674,3 @@ &mcu_r5fss0_core1 { <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; - -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3dc624a379c5f..1930da25d2821 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -799,6 +799,7 @@ mcasp0: mcasp@2b00000 { clocks = <&k3_clks 104 0>; clock-names = "fck"; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -816,6 +817,7 @@ mcasp1: mcasp@2b10000 { clocks = <&k3_clks 105 0>; clock-names = "fck"; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -833,6 +835,7 @@ mcasp2: mcasp@2b20000 { clocks = <&k3_clks 106 0>; clock-names = "fck"; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; cal: cal@6f03000 { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index d1c8047d96726..592ab2b54cb3d 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -487,18 +487,6 @@ &cpsw_port1 { phy-handle = <&phy0>; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; - &dss { status = "disabled"; };