From patchwork Fri Oct 28 13:35:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836818wru; Fri, 28 Oct 2022 06:39:12 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5bvlBpfahhc59UVhuA0BZI5mvmWzxEkxq4n6JHJdaTKNsFCEVykz3GYPJUX77nLEaMBUcu X-Received: by 2002:a17:902:7792:b0:182:9404:f226 with SMTP id o18-20020a170902779200b001829404f226mr55824378pll.76.1666964351987; Fri, 28 Oct 2022 06:39:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964351; cv=none; d=google.com; s=arc-20160816; b=TEGw5qc3aToQExip899MQDix0uLs2tYyvzdXuU6/tTE2i8gT3aelD99U40Ct6OiZCS UWG2Z1qBMPZ8bTgBx+6viYW7zaaB0PtnH46n/+dxziSNkS3DCxH2AqREk6bOnSSfds0F 7d4eH4WY5hPP08WMB9yIVuzMKV6GZ5a2lrKmxuB7yDXQp7r+tZf55pu9YCR+MKCclcEA gfCVQLOyGORSAcuJuQBIHqTYQm25a1ik8EdSPU/0agpd+K5SvZTTLOzO/gWu2W+KfliD t7w0TH2VCmRJSYLt4AG7wcYJnCB1+aobc4/mMh4uIQJsMd0MUY9SjA+SeEHxnd71s4HV btpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P+5kWnCHXH5vfWIzomjZ5girrappos+cwjjryHEuF78=; b=LmSmDIAaTilRppgs1WgBeuRlx6KECbnUataiMOVtCoE81X0jIbyNbMkL3TjkmmjCvg hDs6gLqc+EAQCd02qcvrnkNmebeP5GvMhSkP/ppYW7dbsPxUcorinezto1CoeR/rHzby Jrqz0g6eX4k2g8v0XsMnM2OL12OBVcJeQPpimkGejWYtBbnGqFBYxy+MnhNZDGKo8YdS 1bgMwyN85dHW4T314Bbo68c0RaMa7chzacvfzyWQUhuAce8cyYnQZUG8wTxCA0DPEQCz Yjq/9hihNo209JYIJ1sAuCSCmVeraSEAG6lw0tSKpyxusloRH07HEPCj0WSIU11HN++a xIbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=E2KNDqcy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b5-20020a63d305000000b0046af0960898si5479471pgg.625.2022.10.28.06.38.56; Fri, 28 Oct 2022 06:39:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=E2KNDqcy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231321AbiJ1NiK (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230491AbiJ1Ngy (ORCPT ); Fri, 28 Oct 2022 09:36:54 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C1E51D8F0E; Fri, 28 Oct 2022 06:36:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CB350B82A34; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9B3BC43141; Fri, 28 Oct 2022 13:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=xoxEMrVgUDSA6xW48AZ4Xutg5TwUiPYQloujKm9//yI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E2KNDqcyDaINoPvD+kBZ6YO10CuqOwihKuAA3gXpLcxTgg2ksGpq1N3EAwcG6PgAj YL0CkTwiqFdgpGvAHFf2cKz2no+EXGhIRnOO+ffZE507cBn5vVcvoCvuc/PmSP4s6Q tWe+SsZS2ofWJ9t+uZjet9ciq0bHiVj6pehKuy1BbqG+s0kDvvBX4FFaWGY9/KKXRI GcXGosEGx27lUKIzjzf8/kl2ZufngU3v+T4O9vPovHCftb+YI/l5dRJzjxON2/+hnt btx3NEV7XLyyvxrOQV4ZoFvfSfOnKSxjHW6tXTCmu928i9YRyAN/x+XPEn9pkvGD1c uCn2uHKHJZ2kA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXG-0004qv-TA; Fri, 28 Oct 2022 15:36:34 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 01/16] phy: qcom-qmp-pcie: sort device-id table Date: Fri, 28 Oct 2022 15:35:48 +0200 Message-Id: <20221028133603.18470-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938812005291642?= X-GMAIL-MSGID: =?utf-8?q?1747938812005291642?= Sort the device-id table by compatible string to make it easier to find and add new entries. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7c81667dd968..4e5111d19692 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2282,17 +2282,17 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, static const struct of_device_id qmp_pcie_of_match_table[] = { { - .compatible = "qcom,msm8998-qmp-pcie-phy", - .data = &msm8998_pciephy_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-pcie-phy", - .data = &ipq8074_pciephy_cfg, + .compatible = "qcom,ipq6018-qmp-pcie-phy", + .data = &ipq6018_pciephy_cfg, }, { .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", .data = &ipq8074_pciephy_gen3_cfg, }, { - .compatible = "qcom,ipq6018-qmp-pcie-phy", - .data = &ipq6018_pciephy_cfg, + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,msm8998-qmp-pcie-phy", + .data = &msm8998_pciephy_cfg, }, { .compatible = "qcom,sc8180x-qmp-pcie-phy", .data = &sc8180x_pciephy_cfg, @@ -2302,6 +2302,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sdm845-qmp-pcie-phy", .data = &sdm845_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-pcie-phy", + .data = &sdx55_qmp_pciephy_cfg, }, { .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", .data = &sm8250_qmp_gen3x1_pciephy_cfg, @@ -2311,9 +2314,6 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sm8250-qmp-modem-pcie-phy", .data = &sm8250_qmp_gen3x2_pciephy_cfg, - }, { - .compatible = "qcom,sdx55-qmp-pcie-phy", - .data = &sdx55_qmp_pciephy_cfg, }, { .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", .data = &sm8450_qmp_gen3x1_pciephy_cfg, From patchwork Fri Oct 28 13:35:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836828wru; Fri, 28 Oct 2022 06:39:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5RIN+ZoTXndIqT1sQp+5wPHoMfYf33+VpQ1oOrFP82N8Zuyocht8AGij6AHjPs22XkJP3/ X-Received: by 2002:a17:907:a422:b0:7a6:c4cb:dd42 with SMTP id sg34-20020a170907a42200b007a6c4cbdd42mr24897144ejc.735.1666964353274; Fri, 28 Oct 2022 06:39:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964353; cv=none; d=google.com; s=arc-20160816; b=bGVxBzfSDevfiG+nOKwmaewui3cvG0n36aTtr6DZxvo0eZDW8Y+e6z1nWJD6+ZkYQx FNp8q8nO8XnpKs+Ypvfe0SALN4G7OycShsGxJURYh04hdeymb7PXjYFKG0zv4FCjK5uE 6HZH6QdtFPEieByIRV75MKg1ujXeU/b5J9dOC1az4l3nc4pjWdjYlMmkWsyhAh2soyUp uVQCPI55PeL+T+FtphR3DYsqJmV/h1h5QhEE2mYR69x792A7gu4hmw4mYwe8aL0Poyx2 i/YYapSuaRGqEgZxdPj5hSk6QeBflq92RsvWCWt4ieOQEXtbebgfnSe0TNhAatdYFouB CkVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jzO/eUmVzPwg36y0IJsVzHLhn2TSulOJJeEb4D0oybg=; b=Xz49zYNuEipLSEljs8N4n3tL7PWDC3BvGC/VHJ8kipERP0UY+QpAUt1qJyXJvpprgH iB1hpGEobyg3/uQlLm/6AKNdltH+wHl+qNkg0s5y0rKxqGAuxgphsBatntRJ0onbH3wK gAKDd0WTnTjFVA+6X+lCvjYnlgUTdgx733XXoDUSiiaa0fjNFD5qOc0Xh/242aYFuIFy kLHwosrD3y6ON4SU6KxMKutSmhUwl4DJp0l7KnNo3RGHGsTlz4lb+UqgXHgjDYSR2Cit 2gIKSs9/RqUiAzD8nC6rUBRRxRoTzh4oVjyEd7UXbIJVFHiLEvhA0dlHyqGG0YulRCH0 G1xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="U8ydrud/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 90 ++++++++++++------------ 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 4e5111d19692..e66f6adc404b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2280,51 +2280,6 @@ static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, return 0; } -static const struct of_device_id qmp_pcie_of_match_table[] = { - { - .compatible = "qcom,ipq6018-qmp-pcie-phy", - .data = &ipq6018_pciephy_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", - .data = &ipq8074_pciephy_gen3_cfg, - }, { - .compatible = "qcom,ipq8074-qmp-pcie-phy", - .data = &ipq8074_pciephy_cfg, - }, { - .compatible = "qcom,msm8998-qmp-pcie-phy", - .data = &msm8998_pciephy_cfg, - }, { - .compatible = "qcom,sc8180x-qmp-pcie-phy", - .data = &sc8180x_pciephy_cfg, - }, { - .compatible = "qcom,sdm845-qhp-pcie-phy", - .data = &sdm845_qhp_pciephy_cfg, - }, { - .compatible = "qcom,sdm845-qmp-pcie-phy", - .data = &sdm845_qmp_pciephy_cfg, - }, { - .compatible = "qcom,sdx55-qmp-pcie-phy", - .data = &sdx55_qmp_pciephy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", - .data = &sm8250_qmp_gen3x1_pciephy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", - .data = &sm8250_qmp_gen3x2_pciephy_cfg, - }, { - .compatible = "qcom,sm8250-qmp-modem-pcie-phy", - .data = &sm8250_qmp_gen3x2_pciephy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", - .data = &sm8450_qmp_gen3x1_pciephy_cfg, - }, { - .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", - .data = &sm8450_qmp_gen4x2_pciephy_cfg, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); - static int qmp_pcie_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; @@ -2408,6 +2363,51 @@ static int qmp_pcie_probe(struct platform_device *pdev) return ret; } +static const struct of_device_id qmp_pcie_of_match_table[] = { + { + .compatible = "qcom,ipq6018-qmp-pcie-phy", + .data = &ipq6018_pciephy_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", + .data = &ipq8074_pciephy_gen3_cfg, + }, { + .compatible = "qcom,ipq8074-qmp-pcie-phy", + .data = &ipq8074_pciephy_cfg, + }, { + .compatible = "qcom,msm8998-qmp-pcie-phy", + .data = &msm8998_pciephy_cfg, + }, { + .compatible = "qcom,sc8180x-qmp-pcie-phy", + .data = &sc8180x_pciephy_cfg, + }, { + .compatible = "qcom,sdm845-qhp-pcie-phy", + .data = &sdm845_qhp_pciephy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-pcie-phy", + .data = &sdm845_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sdx55-qmp-pcie-phy", + .data = &sdx55_qmp_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", + .data = &sm8250_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8250-qmp-modem-pcie-phy", + .data = &sm8250_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", + .data = &sm8450_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", + .data = &sm8450_qmp_gen4x2_pciephy_cfg, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); + static struct platform_driver qmp_pcie_driver = { .probe = qmp_pcie_probe, .driver = { From patchwork Fri Oct 28 13:35:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836688wru; Fri, 28 Oct 2022 06:38:53 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6XvpxXvk7lhytguwEcXs7CSaIbtBGAuNy6V240QaiCnQIbzJL/le6LzHe6lKlvRC79QbbI X-Received: by 2002:a05:6a00:22c3:b0:56b:f793:5ad1 with SMTP id f3-20020a056a0022c300b0056bf7935ad1mr23609229pfj.58.1666964333049; Fri, 28 Oct 2022 06:38:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964333; cv=none; d=google.com; s=arc-20160816; b=oM8wEZ+vJg2RIuFxsoq0pbgNOH4uegtdOcOYKcQ/TZgJyjwY7DItHLRKqsP4YMkIoD kROhRrydqwLaFN4bglMhNHKSeKowZvdCVbw4F+DyHMEN6JCV9io0WuvHAXq/tth1brXd JGrCoxVUorxZPLCkRIj01thjM9I6ipIlZhScIgJM6/KoFg7GNxBfUuG8YKpm0yKwGZuY 1M0p66OyPMEYXjFUFwbIVcVbaZdDummfXmanIOX76F+gHo+hvcBkozBjyj7efpT876Gn GJ/v1OQh6/ZlsM9s6Qb04erGUayB8/SCqCdz0WTN6qPwl09h19HGnxWmkFrRBOIS2uU6 JOog== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id bj3-20020a056a02018300b0044b014c9a3asi5283398pgb.300.2022.10.28.06.38.38; Fri, 28 Oct 2022 06:38:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=L0BFDLsd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231303AbiJ1Nh5 (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230431AbiJ1Ngx (ORCPT ); Fri, 28 Oct 2022 09:36:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 995441D8F38; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 397136288B; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8F2BC433D6; Fri, 28 Oct 2022 13:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=TmJEMvQwo+uUmysGKcW+OMz9Z15aw3Ra9DIApzj3kVU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L0BFDLsdDSTe1s2amVCtyTYPmQdfmAOBuwweG4zT0ELfZPHw0P8bFsk+dtqZBrYJM shaRID9vQMg7QukiZT8jDmug0kINv89tEwiNNn+I35BFB2Z782yBWO5VGPU5JFLAV6 yST6Kxdo/L0r5pQDU6US7Akodcaxn88ZCHYBmceySqY845eef+PiEhd/819dNRv2Cl CDY5NeeDdVcyof4jE0UA8zId/qwALSsakHR3DcaVFYcpB2eJ1kOlS8M109fCXMOlxk Cp8ef3AowvjqFyvlv0Q4ujRg1dqDMn2rMrgGl2Oe2QTxNaK9bhgO9IqgUmylyUJQzM x+R37IByQ2+AQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004qz-2n; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 03/16] phy: qcom-qmp-pcie: merge driver data Date: Fri, 28 Oct 2022 15:35:50 +0200 Message-Id: <20221028133603.18470-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938792497565121?= X-GMAIL-MSGID: =?utf-8?q?1747938792497565121?= The PCIe QMP PHY driver only manages a single PHY so merge the old qcom_qmp and qmp_phy structures and drop the PHY array. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 218 +++++++++-------------- 1 file changed, 88 insertions(+), 130 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e66f6adc404b..667a87e7c917 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1365,56 +1365,26 @@ struct qmp_phy_cfg { unsigned long pipe_clock_rate; }; -/** - * struct qmp_phy - per-lane phy descriptor - * - * @phy: generic phy - * @cfg: phy specific configuration - * @serdes: iomapped memory space for phy's serdes (i.e. PLL) - * @tx: iomapped memory space for lane's tx - * @rx: iomapped memory space for lane's rx - * @pcs: iomapped memory space for lane's pcs - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) - * @pcs_misc: iomapped memory space for lane's pcs_misc - * @pipe_clk: pipe clock - * @qmp: QMP phy to which this lane belongs - * @mode: currently selected PHY mode - */ -struct qmp_phy { - struct phy *phy; +struct qmp_pcie { + struct device *dev; + const struct qmp_phy_cfg *cfg; + void __iomem *serdes; + void __iomem *pcs; + void __iomem *pcs_misc; void __iomem *tx; void __iomem *rx; - void __iomem *pcs; void __iomem *tx2; void __iomem *rx2; - void __iomem *pcs_misc; - struct clk *pipe_clk; - struct qcom_qmp *qmp; - int mode; -}; - -/** - * struct qcom_qmp - structure holding QMP phy block attributes - * - * @dev: device - * - * @clks: array of clocks required by phy - * @resets: array of resets required by phy - * @vregs: regulator supplies bulk data - * - * @phys: array of per-lane phy descriptors - */ -struct qcom_qmp { - struct device *dev; + struct clk *pipe_clk; struct clk_bulk_data *clks; struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; - struct qmp_phy **phys; + struct phy *phy; + int mode; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -1850,9 +1820,9 @@ static void qmp_pcie_configure(void __iomem *base, qmp_pcie_configure_lane(base, tbl, num, 0xff); } -static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) { - void __iomem *serdes = qphy->serdes; + void __iomem *serdes = qmp->serdes; if (!tables) return; @@ -1860,11 +1830,11 @@ static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_ qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num); } -static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) { - const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; + const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *tx = qmp->tx; + void __iomem *rx = qmp->rx; if (!tables) return; @@ -1872,17 +1842,17 @@ static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_t qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); if (cfg->lanes >= 2) - qmp_pcie_configure_lane(qphy->tx2, tables->tx, tables->tx_num, 2); + qmp_pcie_configure_lane(qmp->tx2, tables->tx, tables->tx_num, 2); qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); if (cfg->lanes >= 2) - qmp_pcie_configure_lane(qphy->rx2, tables->rx, tables->rx_num, 2); + qmp_pcie_configure_lane(qmp->rx2, tables->rx, tables->rx_num, 2); } -static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) { - void __iomem *pcs = qphy->pcs; - void __iomem *pcs_misc = qphy->pcs_misc; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; if (!tables) return; @@ -1893,9 +1863,8 @@ static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tab static int qmp_pcie_init(struct phy *phy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; + struct qmp_pcie *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; int ret; ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); @@ -1932,9 +1901,8 @@ static int qmp_pcie_init(struct phy *phy) static int qmp_pcie_exit(struct phy *phy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; + struct qmp_pcie *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; reset_control_bulk_assert(cfg->num_resets, qmp->resets); @@ -1947,11 +1915,10 @@ static int qmp_pcie_exit(struct phy *phy) static int qmp_pcie_power_on(struct phy *phy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); - struct qcom_qmp *qmp = qphy->qmp; - const struct qmp_phy_cfg *cfg = qphy->cfg; + struct qmp_pcie *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; const struct qmp_phy_cfg_tables *mode_tables; - void __iomem *pcs = qphy->pcs; + void __iomem *pcs = qmp->pcs; void __iomem *status; unsigned int mask, val; int ret; @@ -1959,26 +1926,26 @@ static int qmp_pcie_power_on(struct phy *phy) qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); - if (qphy->mode == PHY_MODE_PCIE_RC) + if (qmp->mode == PHY_MODE_PCIE_RC) mode_tables = cfg->tables_rc; else mode_tables = cfg->tables_ep; - qmp_pcie_serdes_init(qphy, &cfg->tables); - qmp_pcie_serdes_init(qphy, mode_tables); + qmp_pcie_serdes_init(qmp, &cfg->tables); + qmp_pcie_serdes_init(qmp, mode_tables); - ret = clk_prepare_enable(qphy->pipe_clk); + ret = clk_prepare_enable(qmp->pipe_clk); if (ret) { dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); return ret; } /* Tx, Rx, and PCS configurations */ - qmp_pcie_lanes_init(qphy, &cfg->tables); - qmp_pcie_lanes_init(qphy, mode_tables); + qmp_pcie_lanes_init(qmp, &cfg->tables); + qmp_pcie_lanes_init(qmp, mode_tables); - qmp_pcie_pcs_init(qphy, &cfg->tables); - qmp_pcie_pcs_init(qphy, mode_tables); + qmp_pcie_pcs_init(qmp, &cfg->tables); + qmp_pcie_pcs_init(qmp, mode_tables); /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -2001,27 +1968,27 @@ static int qmp_pcie_power_on(struct phy *phy) return 0; err_disable_pipe_clk: - clk_disable_unprepare(qphy->pipe_clk); + clk_disable_unprepare(qmp->pipe_clk); return ret; } static int qmp_pcie_power_off(struct phy *phy) { - struct qmp_phy *qphy = phy_get_drvdata(phy); - const struct qmp_phy_cfg *cfg = qphy->cfg; + struct qmp_pcie *qmp = phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg = qmp->cfg; - clk_disable_unprepare(qphy->pipe_clk); + clk_disable_unprepare(qmp->pipe_clk); /* PHY reset */ - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); + qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); /* stop SerDes and Phy-Coding-Sublayer */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); /* Put PHY into POWER DOWN state: active low */ - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], + qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); return 0; @@ -2055,12 +2022,12 @@ static int qmp_pcie_disable(struct phy *phy) static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) { - struct qmp_phy *qphy = phy_get_drvdata(phy); + struct qmp_pcie *qmp = phy_get_drvdata(phy); switch (submode) { case PHY_MODE_PCIE_RC: case PHY_MODE_PCIE_EP: - qphy->mode = submode; + qmp->mode = submode; break; default: dev_err(&phy->dev, "Unsupported submode %d\n", submode); @@ -2072,7 +2039,7 @@ static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { - struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_pcie *qmp = dev_get_drvdata(dev); int num = cfg->num_vregs; int i; @@ -2088,7 +2055,7 @@ static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) { - struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_pcie *qmp = dev_get_drvdata(dev); int i; int ret; @@ -2109,7 +2076,7 @@ static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) { - struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_pcie *qmp = dev_get_drvdata(dev); int num = cfg->num_clks; int i; @@ -2146,7 +2113,7 @@ static void phy_clk_release_provider(void *res) * clk | +-------+ | +-----+ * +---------------+ */ -static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) +static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) { struct clk_fixed_rate *fixed; struct clk_init_data init = { }; @@ -2168,8 +2135,8 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) * Controllers using QMP PHY-s use 125MHz pipe clock interface * unless other frequency is specified in the PHY config. */ - if (qmp->phys[0]->cfg->pipe_clock_rate) - fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; + if (qmp->cfg->pipe_clock_rate) + fixed->fixed_rate = qmp->cfg->pipe_clock_rate; else fixed->fixed_rate = 125000000; @@ -2197,97 +2164,92 @@ static const struct phy_ops qmp_pcie_ops = { .owner = THIS_MODULE, }; -static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, +static int qmp_pcie_create(struct device *dev, struct device_node *np, void __iomem *serdes, const struct qmp_phy_cfg *cfg) { - struct qcom_qmp *qmp = dev_get_drvdata(dev); + struct qmp_pcie *qmp = dev_get_drvdata(dev); struct phy *generic_phy; - struct qmp_phy *qphy; int ret; - qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); - if (!qphy) - return -ENOMEM; + qmp->mode = PHY_MODE_PCIE_RC; - qphy->mode = PHY_MODE_PCIE_RC; + qmp->cfg = cfg; + qmp->serdes = serdes; - qphy->cfg = cfg; - qphy->serdes = serdes; /* * Get memory resources for the PHY: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 * For single lane PHYs: pcs_misc (optional) -> 3. */ - qphy->tx = devm_of_iomap(dev, np, 0, NULL); - if (IS_ERR(qphy->tx)) - return PTR_ERR(qphy->tx); + qmp->tx = devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qmp->tx)) + return PTR_ERR(qmp->tx); if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) - qphy->rx = qphy->tx; + qmp->rx = qmp->tx; else - qphy->rx = devm_of_iomap(dev, np, 1, NULL); - if (IS_ERR(qphy->rx)) - return PTR_ERR(qphy->rx); + qmp->rx = devm_of_iomap(dev, np, 1, NULL); + if (IS_ERR(qmp->rx)) + return PTR_ERR(qmp->rx); - qphy->pcs = devm_of_iomap(dev, np, 2, NULL); - if (IS_ERR(qphy->pcs)) - return PTR_ERR(qphy->pcs); + qmp->pcs = devm_of_iomap(dev, np, 2, NULL); + if (IS_ERR(qmp->pcs)) + return PTR_ERR(qmp->pcs); if (cfg->lanes >= 2) { - qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); - if (IS_ERR(qphy->tx2)) - return PTR_ERR(qphy->tx2); + qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); + if (IS_ERR(qmp->tx2)) + return PTR_ERR(qmp->tx2); - qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); - if (IS_ERR(qphy->rx2)) - return PTR_ERR(qphy->rx2); + qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); + if (IS_ERR(qmp->rx2)) + return PTR_ERR(qmp->rx2); - qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); + qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); } else { - qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); + qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); } - if (IS_ERR(qphy->pcs_misc) && + if (IS_ERR(qmp->pcs_misc) && of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) - qphy->pcs_misc = qphy->pcs + 0x400; + qmp->pcs_misc = qmp->pcs + 0x400; - if (IS_ERR(qphy->pcs_misc)) { + if (IS_ERR(qmp->pcs_misc)) { if (cfg->tables.pcs_misc || (cfg->tables_rc && cfg->tables_rc->pcs_misc) || - (cfg->tables_ep && cfg->tables_ep->pcs_misc)) - return PTR_ERR(qphy->pcs_misc); + (cfg->tables_ep && cfg->tables_ep->pcs_misc)) { + return PTR_ERR(qmp->pcs_misc); + } } - qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); - if (IS_ERR(qphy->pipe_clk)) { - return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), - "failed to get lane%d pipe clock\n", id); + qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(qmp->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + "failed to get pipe clock\n"); } generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); - dev_err(dev, "failed to create qphy %d\n", ret); + dev_err(dev, "failed to create PHY: %d\n", ret); return ret; } - qphy->phy = generic_phy; - qphy->qmp = qmp; - qmp->phys[id] = qphy; - phy_set_drvdata(generic_phy, qphy); + qmp->phy = generic_phy; + phy_set_drvdata(generic_phy, qmp); return 0; } static int qmp_pcie_probe(struct platform_device *pdev) { - struct qcom_qmp *qmp; struct device *dev = &pdev->dev; struct device_node *child; struct phy_provider *phy_provider; void __iomem *serdes; const struct qmp_phy_cfg *cfg = NULL; + struct qmp_pcie *qmp; int num, id; int ret; @@ -2326,14 +2288,10 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (num > 1) return -EINVAL; - qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); - if (!qmp->phys) - return -ENOMEM; - id = 0; for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ - ret = qmp_pcie_create(dev, child, id, serdes, cfg); + ret = qmp_pcie_create(dev, child, serdes, cfg); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", id, ret); From patchwork Fri Oct 28 13:35:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836393wru; Fri, 28 Oct 2022 06:38:15 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6U4vw414VnTwC0SDT+chISL58s7a+hoLeMa8LG6BRCCJWNGqy8iJ46frNa3B2xD52YVgpr X-Received: by 2002:a17:902:8e84:b0:178:57e4:805b with SMTP id bg4-20020a1709028e8400b0017857e4805bmr54427793plb.144.1666964295171; Fri, 28 Oct 2022 06:38:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964295; cv=none; d=google.com; s=arc-20160816; b=pmj60XdR3SzkhM7l/WbYNP0eySl1cvg21LWmO9uZxsWOisMDl6vUe2q/bvQYNbxqtI cmNRSFpoPzbcMtiky+P6o2XwvKE63Wn/9Vd+Uabx6xfMrApJH14aanq4BIKx4KT+YQlr 7svaBY6ZCjTwSu/3mtqwk2JTy4Co1Nyw6ZtL35ICsZGBYb2c4oTcd7q4c9VPdLbxrbF6 PPx/jUA3X1gH/Rs6+6q1ltApEAfA4TVsaNPCnpncxCdQ0rwuAiuFS7aEThGfXj2Nx10y Mc53CuBpAeH3j0Y5nNTOtYSgiJYsCGjD1CWnRNaLTc/xijBEh4dHuBSSxsFxDZsgkDb0 MSVw== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id pc15-20020a17090b3b8f00b001fe1c9436b1si6809561pjb.86.2022.10.28.06.37.59; Fri, 28 Oct 2022 06:38:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=R2wDTLBe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231201AbiJ1NhT (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230371AbiJ1Ngv (ORCPT ); Fri, 28 Oct 2022 09:36:51 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5F91D8F03; Fri, 28 Oct 2022 06:36:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A04E262886; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD7B2C43470; Fri, 28 Oct 2022 13:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964208; bh=3R9BPW6QSUhhXBNcO5z3mLwkQgvqyw63TThHmZ5QLXM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R2wDTLBefPKWZu1r7cjfbTWE5jvgEbEvuMgfOU2viChfnBuJsfqUsx+C4Yx+Ex2jN T057xObRhaCEhMyWALpPBvQpaQng0VxmoZS798kyiglzf2JPlJrKhzFtS2qEIooFPK v34xY4VOLhfm77VnzlsHRSVJXGuNjD2mLW666xbdNFLREfX39+SRctd1RYfswAK0Gg eq3k4Djf9XIQUCLsLuK1SkXFsxg2+TVHb8mtIfjhY4VRv+RADQ0PI5Tz54DAiVD5gx 67pOdTaLnCW5ykLV+uyaC9d+i4iZb5mtgdGvz9nxJWqpRJ4LxN/yQ9M/k/JeAfAGXz GjT9DU8bJ4lig== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004r1-5H; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 04/16] phy: qcom-qmp-pcie: clean up device-tree parsing Date: Fri, 28 Oct 2022 15:35:51 +0200 Message-Id: <20221028133603.18470-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938752309484979?= X-GMAIL-MSGID: =?utf-8?q?1747938752309484979?= Since the QMP driver split there will be at most a single child node so drop the obsolete iteration construct. While at it, drop the verbose error logging that would have been printed also on probe deferrals. Note that there's no need to check if there are additional child nodes (the kernel is not a devicetree validator), but let's return an error if there are no child nodes at all for now. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 34 +++++++----------------- 1 file changed, 9 insertions(+), 25 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 667a87e7c917..bc96518ad6b0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2250,7 +2250,6 @@ static int qmp_pcie_probe(struct platform_device *pdev) void __iomem *serdes; const struct qmp_phy_cfg *cfg = NULL; struct qmp_pcie *qmp; - int num, id; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -2283,34 +2282,19 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (ret) return ret; - num = of_get_available_child_count(dev->of_node); - /* do we have a rogue child node ? */ - if (num > 1) + child = of_get_next_available_child(dev->of_node, NULL); + if (!child) return -EINVAL; - id = 0; - for_each_available_child_of_node(dev->of_node, child) { - /* Create per-lane phy */ - ret = qmp_pcie_create(dev, child, serdes, cfg); - if (ret) { - dev_err(dev, "failed to create lane%d phy, %d\n", - id, ret); - goto err_node_put; - } + ret = qmp_pcie_create(dev, child, serdes, cfg); + if (ret) + goto err_node_put; - /* - * Register the pipe clock provided by phy. - * See function description to see details of this pipe clock. - */ - ret = phy_pipe_clk_register(qmp, child); - if (ret) { - dev_err(qmp->dev, - "failed to register pipe clock source\n"); - goto err_node_put; - } + ret = phy_pipe_clk_register(qmp, child); + if (ret) + goto err_node_put; - id++; - } + of_node_put(child); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); From patchwork Fri Oct 28 13:35:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12287 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836958wru; Fri, 28 Oct 2022 06:39:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4VlAK4kg6EjLxoHvEsAR36PAgy5P0EQK/tcQSNdH386yQ5SNQvUg+KucpAQuiqAjUgQECS X-Received: by 2002:a17:90b:1a88:b0:20d:8df0:ac64 with SMTP id ng8-20020a17090b1a8800b0020d8df0ac64mr16107691pjb.140.1666964371932; Fri, 28 Oct 2022 06:39:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964371; cv=none; d=google.com; s=arc-20160816; b=kbHQ27laJSrMkg+0h9HMjat/srzmpS0cYCnQJ4q5Pa6NhSMSa6UfVc2wkdKWBrPWPw xmvjZRatPdwvVe0OZuaBCz5ILjyVpRFDymN9hM1JeIt9gukpbxOF941CFX3lHk8ynLtv +ihWsK2j5WvmXnSrjINwxPI7Cab/SAaG1eXNYyzPipCfkkI6VwU7Sk4Jt5ICQjQbu2Hp Xvb9+IsyexbH4+8b/rvno2fXqYah/dw1FIZkceAmqafj2W6o4IyC2xlOBm5M4goJrYcQ DUA0kqJ/sxNrFCGpAoUtmw/EjcauN1l2W1UIwnBD6QicZ+Wu2bIltExixgzBUiTddrW8 7Zng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Olnv1q2Lt69gkt4lsJLecrUtj2PC4er7yhuHCyoKYiY=; b=BHKWEodGRG2G5SJ1JPwmtzLwNMzFlZujX9830geL/CCVQc/dq8QI06ERd3CjZClzSc KHWF+hwcCKfhjNb6WmRfv1ZD+51Wkb7FBbJ0K7fIjz78nidMQI5BZ8GqjmwcCiGiQUlI hKmlAvy1GmyQzgnbcrRjTJU+kKufMbgMdu9KPpqEJk+Rl5AsMIzMFE2aEHzgXbZYuDIj fml4CCYCznVetRWqtfrnlfIrhxomr8yDhonPDydfXxoBVnWIvqwfzpDbWvbA5O8IZNSd pHtaULEwP5m/JWW5IjuEkkCNtOi64eaJNerRWGBek8mp4HU8pokIlXNcssldmakTh+gR mY5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=mf3smrWU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 +++++++++++------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index bc96518ad6b0..e30cbc94cbf6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2037,9 +2037,10 @@ static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) return 0; } -static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) { - struct qmp_pcie *qmp = dev_get_drvdata(dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + struct device *dev = qmp->dev; int num = cfg->num_vregs; int i; @@ -2053,9 +2054,10 @@ static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) return devm_regulator_bulk_get(dev, num, qmp->vregs); } -static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_reset_init(struct qmp_pcie *qmp) { - struct qmp_pcie *qmp = dev_get_drvdata(dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + struct device *dev = qmp->dev; int i; int ret; @@ -2074,9 +2076,10 @@ static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg return 0; } -static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_clk_init(struct qmp_pcie *qmp) { - struct qmp_pcie *qmp = dev_get_drvdata(dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + struct device *dev = qmp->dev; int num = cfg->num_clks; int i; @@ -2164,18 +2167,15 @@ static const struct phy_ops qmp_pcie_ops = { .owner = THIS_MODULE, }; -static int qmp_pcie_create(struct device *dev, struct device_node *np, - void __iomem *serdes, const struct qmp_phy_cfg *cfg) +static int qmp_pcie_create(struct qmp_pcie *qmp, struct device_node *np) { - struct qmp_pcie *qmp = dev_get_drvdata(dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + struct device *dev = qmp->dev; struct phy *generic_phy; int ret; qmp->mode = PHY_MODE_PCIE_RC; - qmp->cfg = cfg; - qmp->serdes = serdes; - /* * Get memory resources for the PHY: * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. @@ -2247,8 +2247,6 @@ static int qmp_pcie_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *child; struct phy_provider *phy_provider; - void __iomem *serdes; - const struct qmp_phy_cfg *cfg = NULL; struct qmp_pcie *qmp; int ret; @@ -2257,28 +2255,27 @@ static int qmp_pcie_probe(struct platform_device *pdev) return -ENOMEM; qmp->dev = dev; - dev_set_drvdata(dev, qmp); - cfg = of_device_get_match_data(dev); - if (!cfg) + qmp->cfg = of_device_get_match_data(dev); + if (!qmp->cfg) return -EINVAL; - WARN_ON_ONCE(!cfg->pwrdn_ctrl); - WARN_ON_ONCE(!cfg->phy_status); + WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); + WARN_ON_ONCE(!qmp->cfg->phy_status); - serdes = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(serdes)) - return PTR_ERR(serdes); + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qmp->serdes)) + return PTR_ERR(qmp->serdes); - ret = qmp_pcie_clk_init(dev, cfg); + ret = qmp_pcie_clk_init(qmp); if (ret) return ret; - ret = qmp_pcie_reset_init(dev, cfg); + ret = qmp_pcie_reset_init(qmp); if (ret) return ret; - ret = qmp_pcie_vreg_init(dev, cfg); + ret = qmp_pcie_vreg_init(qmp); if (ret) return ret; @@ -2286,7 +2283,7 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (!child) return -EINVAL; - ret = qmp_pcie_create(dev, child, serdes, cfg); + ret = qmp_pcie_create(qmp, child); if (ret) goto err_node_put; From patchwork Fri Oct 28 13:35:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836639wru; Fri, 28 Oct 2022 06:38:44 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4wqmqsNzlsSYx3TuuIwVDlhkpv7Mq8khBjqn6JrATfBMW/wB6RCZYMj5bbZ3CKup1gJ/Vx X-Received: by 2002:a17:902:c952:b0:184:ba4f:af39 with SMTP id i18-20020a170902c95200b00184ba4faf39mr55174715pla.58.1666964313826; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r14-20020a63e50e000000b0046edc0aba77si5166247pgh.345.2022.10.28.06.38.18; Fri, 28 Oct 2022 06:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HD38pomS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231226AbiJ1Nh3 (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231204AbiJ1Ngv (ORCPT ); Fri, 28 Oct 2022 09:36:51 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 872341D462D; Fri, 28 Oct 2022 06:36:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 164BF62889; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DB055C43140; Fri, 28 Oct 2022 13:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964208; bh=4E2fvLi9nlZHK7y/46TS4Ev1h53IKCCPR/zjWddiSwE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HD38pomSyKrD3oNQhJNUUrcp14pj+aWczBSM4dw4KpBHpPn6rWzWb7dLyyZvcY51e ZFduRjn3Z/CNJ/QftYD0jB1OhQwKskb6YVzzpWUME39Z4fWhNxGloz0dkYbLwUK8XX irijnb7EltbG+2EcgFav6K/GL3pdheE0b20nnmWsR3wE0AGIbWJNoNQRhYZANoDSfN qzmjT9RJ49sbiRvWm/DHB9BUBIUbqg3en1QXSlxEIuZQgxrdzzBySdtpcwgBqmSHBs cDUXgHetxZm0wkaN+FxPj05+oHrxBSiiD9cRRwPVhXg/hJjE64PR3J2Lgc0+IzglNa AtUdIDDt6qoRw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004r7-AF; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 06/16] phy: qcom-qmp-pcie: rename PHY ops structure Date: Fri, 28 Oct 2022 15:35:53 +0200 Message-Id: <20221028133603.18470-7-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938772115900437?= X-GMAIL-MSGID: =?utf-8?q?1747938772115900437?= Rename the PHY operation structure so that it has a "phy_ops" suffix and move it next to the implementation. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e30cbc94cbf6..bd946438e3c3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2037,6 +2037,13 @@ static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) return 0; } +static const struct phy_ops qmp_pcie_phy_ops = { + .power_on = qmp_pcie_enable, + .power_off = qmp_pcie_disable, + .set_mode = qmp_pcie_set_mode, + .owner = THIS_MODULE, +}; + static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -2160,13 +2167,6 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static const struct phy_ops qmp_pcie_ops = { - .power_on = qmp_pcie_enable, - .power_off = qmp_pcie_disable, - .set_mode = qmp_pcie_set_mode, - .owner = THIS_MODULE, -}; - static int qmp_pcie_create(struct qmp_pcie *qmp, struct device_node *np) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -2229,7 +2229,7 @@ static int qmp_pcie_create(struct qmp_pcie *qmp, struct device_node *np) "failed to get pipe clock\n"); } - generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); + generic_phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); if (IS_ERR(generic_phy)) { ret = PTR_ERR(generic_phy); dev_err(dev, "failed to create PHY: %d\n", ret); From patchwork Fri Oct 28 13:35:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12291 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp837014wru; Fri, 28 Oct 2022 06:39:40 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7WvF10Qfp87im1lnTZPhZPMzPW3rzhwd7muAGj8Ruyl1IqzppONQLYgMH2A+QTUz65IV7e X-Received: by 2002:a17:902:e812:b0:187:2ab:7d6f with SMTP id u18-20020a170902e81200b0018702ab7d6fmr655809plg.137.1666964380527; Fri, 28 Oct 2022 06:39:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964380; cv=none; d=google.com; s=arc-20160816; b=XI7MWRxZJf7mMtMy9AJ/KhH4cW9ImEuGazKTG0MHCuqrKmG/Eg/zyrevFq4drAvIzh 39Ym+GsFzfpY/PYKg49Nxlf51BiViCVbGQwv/lfIJKE5s+yh4g3j9gq81+Yb0iW3+P8m 2xPGxvPQO/MjJiTghGOh30ZcQLWTCKKgB/lVOScdh9A83bXA1ejnfIFYY2uN3ztQqlrx qAhwzZBRMbLgoBFPClqibp8UYolrmetYos4E8B2506Zi/Q0hB8VysDdN2W7+TxrGfHpB z2NEdILvyq/LmXynQOM5uiJF+cnhawY857Tbk3/AX8Gdpx05VAqS33tJcIwQFXToxyrH Dp7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yaihhjhhAs15DOKk2Fwx/x3s/+QJ7XK1popHUyiMAe4=; b=kepjDI+IwqepuRKaGVhxvhmb5iwTof4Xgxa71fvpUTgIz/9HUhXQMxx8Nz4S3eHRdL Z6eqUyyaDextqXTfbC637jdb8bw2S6JzeY5HUXHckb+dhNq+4UfOgWKvMQxyyfUTWQdV I6APRkQNfEGSf/MWjdMRwqPA9CQu3cRpobbByfBwl+MOzIDbxWa8GQRiFY9CQCf1JvNs WyprlJPjRYEB3e3bazWYHbqENXvaEE6JbwjTv5zUEZIMdwuTNUS0kumfqj/X86tyE6kr oJeXPdpjU9h51W12RIbI6U4Bu8cOs8PSAa/StYb9TAnCc5AAoPv6K7ldB3SMlWSss9Jm acRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=TiaWdPFE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n3-20020a170903110300b00176b7b8cf2esi6307994plh.586.2022.10.28.06.39.27; Fri, 28 Oct 2022 06:39:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=TiaWdPFE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230458AbiJ1Nhp (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230472AbiJ1Ngx (ORCPT ); Fri, 28 Oct 2022 09:36:53 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 994DC1D79B2; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 42B49B82A30; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2B11C433C1; Fri, 28 Oct 2022 13:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964208; bh=kHWHx6aJI0QiHRqoX6LC3zrlO/UEm3YyvB3PCvEOuoI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TiaWdPFE0mD+v9D+PG1hQ8efNATegjr1QYQBhZwUtWqjm7nhuTReTDxUzGpvBet7s nv++7gmWAG0wRmtXdcCYIS8ti0tj4awoWg622BxWt3EpBWELRpE48nzXr47cSTM4Yo r6Y9neMTCbdjWHMEtBuU42CxLvClBV6i0pU5nS0cZX6T+M9Yw51qWwRyGfGhYI8k1i C2JUU2LjzbZUTbPavm+XdtFs48AJd6RNK7eiqoGIj0+IMQazRQ8910BG9Cy0V7z5ub ksrcbmzWa7wpFvPr+P/4DFrFgM8WopBbGUJnMpP4NWOoTfcFRhfEoYC0DArTGYOvX4 O0YdmhcdTZWbA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rA-DD; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 07/16] phy: qcom-qmp-pcie: clean up PHY lane init Date: Fri, 28 Oct 2022 15:35:54 +0200 Message-Id: <20221028133603.18470-8-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938842274591120?= X-GMAIL-MSGID: =?utf-8?q?1747938842274591120?= Clean up the PHY lane initialisation somewhat by adding further temporary variables and programming both tx and rx for the second lane after the first lane. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index bd946438e3c3..dd7e72424fc0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1835,18 +1835,19 @@ static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_t const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *tx = qmp->tx; void __iomem *rx = qmp->rx; + void __iomem *tx2 = qmp->tx2; + void __iomem *rx2 = qmp->rx2; if (!tables) return; qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); - - if (cfg->lanes >= 2) - qmp_pcie_configure_lane(qmp->tx2, tables->tx, tables->tx_num, 2); - qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); - if (cfg->lanes >= 2) - qmp_pcie_configure_lane(qmp->rx2, tables->rx, tables->rx_num, 2); + + if (cfg->lanes >= 2) { + qmp_pcie_configure_lane(tx2, tables->tx, tables->tx_num, 2); + qmp_pcie_configure_lane(rx2, tables->rx, tables->rx_num, 2); + } } static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) From patchwork Fri Oct 28 13:35:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836569wru; Fri, 28 Oct 2022 06:38:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6pIadHIKKoq/AawcJ8gPWk1WYi342pqV8QPy1gBpj+1azHsphGAEyXf9LixntMmMUJXPei X-Received: by 2002:a17:902:ef95:b0:186:8376:2084 with SMTP id iz21-20020a170902ef9500b0018683762084mr36334389plb.48.1666964316880; Fri, 28 Oct 2022 06:38:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964316; cv=none; d=google.com; s=arc-20160816; b=jeR1raTktwOu+hX37noEXUODK/SzE3TW2uoP2IuQG40vrwFYd/x/BTglJTY1KYsVOv KKOus/k0oVnVcy20eOyWkV0c0WJa3ckrYz04vspv6ZwyiNfAdoCdk4bqwmx9X00YpXc5 nXHORyZ9BNVpVMZGiAddYCr8s2WtdCR7Ea94D4sfZNX763oFnB2Dwq4QBgCQ57bcd16I A1eaUzzOuk5IRzoOGgZGC091MnP2bVulMu60TGOYSGO71xJoPcBkT/c8N1w2ej/AofWF 1fJRadGYjlSDw+4GZKj5Eb38UbtXWWG3pkltIRcxFNb1I4i2FEnp3o7I2M5dAqA4U3cb S+GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mrd/xiCb/t7qSwVr1emeXvl1HLXCPei4vTbVs2rCZ+o=; b=gEFdtiiFl02JaYVnegg7xaYIBJLSfPQWUooWzYVbrwxDMrbGzZEu/7v24ASWGAPIIh l722Dg4PfOtswtTUBkk7+w1PlKD1IhjHKWm3JD/YCPwVrIBFcNMNk6vtezsLrgoYansM gYXW4k0Eg7YoC+fCl/LNpBYILDxStBL47P/FwAZ7n38YZOpD7wcDJA/iuzD8NfxxW8tq 1HExOpqrUug9G2qU8N7QvgWxXp3SluUKhNWiWZeWMk+cpLLnupALf/EKc3dDxjqwgtPe dLJYcVxZkEAXgGolWQ9STWqJ8sKS97uapgAqzEwbWNn1oz4fGzRt9tg5bYd7cZ0XYAOx xngw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Ja3AI9+j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o24-20020a170902779800b00186b46df624si4764653pll.424.2022.10.28.06.38.22; Fri, 28 Oct 2022 06:38:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Ja3AI9+j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231254AbiJ1Nhf (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231205AbiJ1Ngw (ORCPT ); Fri, 28 Oct 2022 09:36:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A00801D8F37; Fri, 28 Oct 2022 06:36:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 38FDE6288A; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1AA0DC4315F; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=26imd+sl0seyuSbPupXyYoSoRd+tpK1kS727ftQaczA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ja3AI9+js8nh25+LAwo9KFAkyEMR0Cl8XB5NN1K6Jmwtjh3SVEMTo5rJqT3CDQTFf 7G27I/VoKzt0cBW3Ncht9rwxUwEn3EwuPOze2+jGKC5SnDYhf2dnC/VtW2W0qNixap ThJSg8YRC0X9hWYW0Dpetvg8K15QSy1kYLv/memEnmcJea/QvLqBoWPuik1nWNuVF4 0gULgQTIy9ECITGFOxyXjTHhzpl7mrJvT648adPtwCHobAMFA3uJgPMZTKxbfnRy6V vEEqQthhOwHuYnjAHEpOVMFyv6MF1syRxFCpYq+8Czd5j1LzKvxhxpFEg1xZ2soZlP AdYQDTXxOTl9g== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rD-Fe; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 08/16] phy: qcom-qmp-pcie: use shorter tables identifier Date: Fri, 28 Oct 2022 15:35:55 +0200 Message-Id: <20221028133603.18470-9-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938775398161328?= X-GMAIL-MSGID: =?utf-8?q?1747938775398161328?= In preparation for adding a new helper function that initialises all the registers in one place, use a shorter name for the configuration-tables pointer so that it becomes easier to see which table is being processed. Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 ++++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index dd7e72424fc0..791ed7ef0eab 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1820,17 +1820,17 @@ static void qmp_pcie_configure(void __iomem *base, qmp_pcie_configure_lane(base, tbl, num, 0xff); } -static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) { void __iomem *serdes = qmp->serdes; - if (!tables) + if (!tbls) return; - qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num); + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); } -static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; void __iomem *tx = qmp->tx; @@ -1838,28 +1838,28 @@ static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_t void __iomem *tx2 = qmp->tx2; void __iomem *rx2 = qmp->rx2; - if (!tables) + if (!tbls) return; - qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); - qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); if (cfg->lanes >= 2) { - qmp_pcie_configure_lane(tx2, tables->tx, tables->tx_num, 2); - qmp_pcie_configure_lane(rx2, tables->rx, tables->rx_num, 2); + qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); + qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); } } -static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tables) +static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) { void __iomem *pcs = qmp->pcs; void __iomem *pcs_misc = qmp->pcs_misc; - if (!tables) + if (!tbls) return; - qmp_pcie_configure(pcs, tables->pcs, tables->pcs_num); - qmp_pcie_configure(pcs_misc, tables->pcs_misc, tables->pcs_misc_num); + qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); + qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); } static int qmp_pcie_init(struct phy *phy) From patchwork Fri Oct 28 13:35:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12288 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836989wru; Fri, 28 Oct 2022 06:39:37 -0700 (PDT) X-Google-Smtp-Source: AMsMyM482q62SK/frEOziHIt/1ceYQfc7zXkpv8dfRbskq3moiYeHL4SM2YHxNrfmzwDJv46/ugB X-Received: by 2002:a17:90b:4b0b:b0:213:227d:149e with SMTP id lx11-20020a17090b4b0b00b00213227d149emr16193648pjb.145.1666964376772; Fri, 28 Oct 2022 06:39:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964376; cv=none; d=google.com; s=arc-20160816; b=ktT6f7w9wfoYbcFCAA8C79WP6B4D91JToEbv8Cl7ehlLbMVr1rJbmD6CLQu8POqTO3 2ThkCe0CkDFWP1i8h1kgwZwR/N36btqzprFp9Y0uhZ4E5otgSoHjDG1Gxa/2BHEK9APy kaYp6dNImC9Gtrgu9kx7qLBH1IeTfgETlr4wk8gHalQTPix61fDADocfpC8kLOcVHBrz WQwGMB2L1ITA6YwJGFJv4MspWdHA00Si0i0xVZ+QMIO5XyZubk/0MI7stz4oAlZQGJZB OMDcpQCFQ1X/ZMVM9kCR+hAKGo3qqo5UoYSJMZuzhtC07yQzwanZv8m58QKfxj7UFQKL KePQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lSkJgo2AhGcUvXPxPJBb0jP/pO99MhXnpCDi4Fl4/Cg=; b=wlylMTxSwrlFezledXlyu8eKJCs9JH1UmTCKgl6G9N7IyRJz6p7FkAodWd7KmwlFvk +JXNMEXfoUmh6UReLppNJPWrEb6t7W9yEva7Nxx/7v6S+xWg2FSZekGW2ctq9DhqOYjb InFUa5MH63tHKyRxfAvGx/ko40VIWAEFJrs4oeZzNh9oNub7iDzyEdCMeM/d6xXS2nTh aQJ2Q+d5KwiHnTEqgHh2jTuSenQ1NIUMH5FJ3IZH2tJEHnY2bJux/FYF+vflkLfKrDwD yylA1TzqX2W90ySZGmeDtlbTLw93AhfljzOeIKIlQ2rzs0DLjQXcrOkvqczJzy92VL0V 5cHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=NGwjL6BU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v7-20020a654607000000b0043c8455a044si5602368pgq.150.2022.10.28.06.39.22; Fri, 28 Oct 2022 06:39:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=NGwjL6BU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230480AbiJ1NiO (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231124AbiJ1Ngy (ORCPT ); Fri, 28 Oct 2022 09:36:54 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36A151D8F33; Fri, 28 Oct 2022 06:36:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E2F04B82A33; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C96FC43151; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=zRz+xGr3qfzBHmqhYcHtUOAO+a77B5PUV9OisEOT424=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NGwjL6BUqzf4qmUkH5RKP2HzYrjJv+TeCLW0MnsOPLlWz8BcrM7/qzpl90OjOoPnr 3KmQGEfbkHOh4x341ygFqo14frXR4VD/rFF+f3CBqxKWgHLi6lty6eCugeOBEb+vLW Zvb3FVE+EcnNWnwvBfVvIWcN7+hLiQhMVvj/bT7XkTw2NOcu6H/Pwvwkl6IjRdr+T1 BXHPddWl2wPREB1TZi41kLvK47s7oQOA0CpYyxYdRls2adqEM6dhw1N8tGrtleghOf Yhi3HNR3Njl5h4G5hqQpCc7xyLCK6cXXrDv4E8DECLnf+oe24SnYa3JcCQW9rNfFib qO6cPomTiBsLg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rG-Hw; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 09/16] phy: qcom-qmp-pcie: add register init helper Date: Fri, 28 Oct 2022 15:35:56 +0200 Message-Id: <20221028133603.18470-10-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938838384102123?= X-GMAIL-MSGID: =?utf-8?q?1747938838384102123?= Generalise the serdes initialisation helper so that it can be used to initialise all the PHY registers (e.g. serdes, tx, rx, pcs). Note that this defers the ungating of the PIPE clock somewhat, which is fine as it isn't needed until starting the PHY. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 37 +++++------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 791ed7ef0eab..f57d10f20277 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1820,27 +1820,22 @@ static void qmp_pcie_configure(void __iomem *base, qmp_pcie_configure_lane(base, tbl, num, 0xff); } -static void qmp_pcie_serdes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) -{ - void __iomem *serdes = qmp->serdes; - - if (!tbls) - return; - - qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); -} - -static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) +static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; + void __iomem *serdes = qmp->serdes; void __iomem *tx = qmp->tx; void __iomem *rx = qmp->rx; void __iomem *tx2 = qmp->tx2; void __iomem *rx2 = qmp->rx2; + void __iomem *pcs = qmp->pcs; + void __iomem *pcs_misc = qmp->pcs_misc; if (!tbls) return; + qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); + qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); @@ -1848,15 +1843,6 @@ static void qmp_pcie_lanes_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_t qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); } -} - -static void qmp_pcie_pcs_init(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) -{ - void __iomem *pcs = qmp->pcs; - void __iomem *pcs_misc = qmp->pcs_misc; - - if (!tbls) - return; qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); @@ -1932,8 +1918,8 @@ static int qmp_pcie_power_on(struct phy *phy) else mode_tables = cfg->tables_ep; - qmp_pcie_serdes_init(qmp, &cfg->tables); - qmp_pcie_serdes_init(qmp, mode_tables); + qmp_pcie_init_registers(qmp, &cfg->tables); + qmp_pcie_init_registers(qmp, mode_tables); ret = clk_prepare_enable(qmp->pipe_clk); if (ret) { @@ -1941,13 +1927,6 @@ static int qmp_pcie_power_on(struct phy *phy) return ret; } - /* Tx, Rx, and PCS configurations */ - qmp_pcie_lanes_init(qmp, &cfg->tables); - qmp_pcie_lanes_init(qmp, mode_tables); - - qmp_pcie_pcs_init(qmp, &cfg->tables); - qmp_pcie_pcs_init(qmp, mode_tables); - /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); From patchwork Fri Oct 28 13:35:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12296 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp838264wru; Fri, 28 Oct 2022 06:42:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5j3ogH0g1X0erlxQE7OiYFeO6HSebxwSly4MootdbQp/R03SpmE2uP4tZ7j9QB9+TcRJaM X-Received: by 2002:a17:907:7d8e:b0:78d:ed30:643b with SMTP id oz14-20020a1709077d8e00b0078ded30643bmr46428099ejc.253.1666964551439; Fri, 28 Oct 2022 06:42:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964551; cv=none; d=google.com; s=arc-20160816; b=pXzNHTAIAoHGt/Fok7sOGw9VzuuE0kd1TnrcXyO95Vq7KBJ00WpwlFvQOZY+ha3VRk 0msybnhO/gcHzKCVQYDPWp9Yz3Y0QTPyzSxcyGxmdi4WQQOb6adMG0McYXLN+cx8ZWD5 FMItXIeTWu8Fgsqk8l1dwGFPwkS732br7qo75K3um3OZ1iYJK76xkWi1F2TQPLsZ6B0L JGcK1lIFDpP+OrDwnbRM1YyHeMVgOaVlJ0mMq4fY2vV/LPRodExlEGdxPXOfvBJWpvOH BRg3aWt194u+T589Ha6TZsCLIWeboxJ5LGxYqg5gNLZ7Nxzb6DFHMufJBTuH50OkSQuP qcdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ui2lN8+tFz3KUwMIVt4vMRAGaGuObvmSq0QcOqAfEb4=; b=ie9DxwDnAo2LxNojZGmpMZ39njrw+3IjEgcoLypU/EyeQnC0hhV28+Z5c2g/hfRV64 pXZo2rsdZ1aCT4V/mnCGbgL9nHYDAZWxeIEFIeG4yqYaAft4ZJvTeb2/Aps9RYmCv+Oa wzxG+f0KM2qB7V0rnMcoreOYn5xLY3FKzmkhGzC/49TPA99CXmtSH5CeXB1DnXYWwp9d qSmmm6wVkSWaJtezWzarVM+PegmmadTUp+ti0JcHmTqCgxnBKQKowM2eDWZMZ/YfPFP0 Xh4EJBIkpJ6XVPNdzDrF+4Tp82v7no7tXkWLJudbzj61G5UyXi1gr+hsdiYnkXyToEPu PQvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=aRpCQcxN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i20-20020a170906699400b007aa3373e7fesi3542732ejr.520.2022.10.28.06.42.06; Fri, 28 Oct 2022 06:42:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=aRpCQcxN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231329AbiJ1NiS (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbiJ1Ngy (ORCPT ); Fri, 28 Oct 2022 09:36:54 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C3DB1D8F3F; Fri, 28 Oct 2022 06:36:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 05C01B82A2E; Fri, 28 Oct 2022 13:36:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31A4BC4167D; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=GiJmZNg8T5O5/fCxOI/o4taQRIeOyB6kSPSO4qZDxu8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aRpCQcxNqO65X3OEJS41fQwz+ntOGgwekh4xk4UKWvPyMxse0kGdvIm4RjiP5elXj /l046r4Mr0Jo/OFXscUmDhLGR4dcXFPxSu3nEsOpzOHRkfjz0svusUt/Q+ICKHZAHz qT8s8lGsM6U+rUoWs/7YWynNd9pURNFIHteC9RhhvmbsOwH4HBdcolF/d8SrI7tkN+ lvgBUlUhU69mAC8lEOekm960V8h/58F1APPxP+OtNiK2VuF93KKeCO96RhqcO5hH1Z b55t9NQ4QCsJ3bjGFqz2uj0W+dSNXQxmeomd2u06FNJ1OKOIeualFDDF9F8pPjkRXF 1GAeFpwdveT4A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rK-KR; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v4 10/16] dt-bindings: phy: qcom,qmp-pcie: rename current bindings Date: Fri, 28 Oct 2022 15:35:57 +0200 Message-Id: <20221028133603.18470-11-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747939021275682149?= X-GMAIL-MSGID: =?utf-8?q?1747939021275682149?= The current QMP PCIe PHY bindings are based on the original MSM8996 binding which provided multiple PHYs per IP block and these in turn were described by child nodes. Later QMP PCIe PHY blocks only provide a single PHY and the remnant child node does not really reflect the hardware. The original MSM8996 binding also ended up describing the individual register blocks as belonging to either the wrapper node or the PHY child nodes. This is an unnecessary level of detail which has lead to problems when later IP blocks using different register layouts have been forced to fit the original mould rather than updating the binding. The bindings are arguable also incomplete as they only the describe register blocks used by the current Linux drivers (e.g. does not include the per lane PCS registers). In preparation for adding new bindings for SC8280XP which further bindings can be based on, rename the current schema file after IPQ8074, which was the first SoC added to the bindings after MSM8996 (which has already been split out), and add a reference to the SC8280XP bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold --- ...om,qmp-pcie-phy.yaml => qcom,ipq8074-qmp-pcie-phy.yaml} | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/phy/{qcom,qmp-pcie-phy.yaml => qcom,ipq8074-qmp-pcie-phy.yaml} (96%) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml similarity index 96% rename from Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml rename to Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 324ad7d03a38..62045dcfb20c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml# +$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm QMP PHY controller (PCIe) +title: Qualcomm QMP PHY controller (PCIe, IPQ8074) maintainers: - Vinod Koul @@ -13,6 +13,9 @@ description: QMP PHY controller supports physical layer functionality for a number of controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see + qcom,sc8280xp-qmp-pcie-phy.yaml. + properties: compatible: enum: From patchwork Fri Oct 28 13:35:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp837684wru; Fri, 28 Oct 2022 06:41:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7q7Zxu/+FlD0SbjSQv2gEUf5FMVRqzKv5wCK2ymAjlmidcMK+HvUJqLrUBpgia9K3DsoaN X-Received: by 2002:a63:7909:0:b0:458:1ba6:ec80 with SMTP id u9-20020a637909000000b004581ba6ec80mr47688535pgc.414.1666964473919; Fri, 28 Oct 2022 06:41:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964473; cv=none; d=google.com; s=arc-20160816; b=c1DiLOaCyOpzw6d/7ViomUFH/BvG9q4ytEbvVoRqizQCUDyyNsHGxZpPWkbL7VJPQr g1BFVsue+r1860kOPrQnQWVFkv7X2hCQtwTN6l4oxdMQZ0U94sspnAKHAck6FNoubljf x7mZIIA7tCPAjMginIteaonjOaNU25KSKLi2RDcQuo4Gxm1/Hw42T00N+/cA1Kx9K6xb aTgxiF2vcbpMEWzcZsHt5AtWwBnhdBLbTuAoj7Zqm+aEbg6N0stBfTP+cM4zIhqakxUS ZgBk5ydJZuoUNnVv65cDvmyegZQWfH0LxMwVyw2wI/eGsyJSwk5lazsWBfZCgVQjiZsA kLZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7obINjSQm0JNiLyQYhOupM7ARrAGUDW0/OUAPEHt4Ec=; b=zi2XCDEDgM4cQzj5Miu2DkAbJZjopDcTvlVr7DlpGNpB9JSGwTxmDsq43VcVgfMo7X T7nHRAmWFSVgvlMBeATfo0yKK42GNZ2IvF4Oq0B+PHisS8azxVvu+km3xP00ZVaOFwR1 CLbdI+ol0P0LzI4L0Ypt4if5v4zeZpN7kan7gWrG/yn2oFW/mclD7UrMMi9pEExDvifV sAimXwdNMOBV4ybzakJHEUhpRvfyZkYDk6UX2rEZR/ricuvtxG4v4udmWaSBxlRu3v+o /FqWqiV5ar9vyM3j2c1bsKeWS4KESvJvHKoaSK4MZEx0rn8KbtR2SJOEY3QcgSJmkGKF oEow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Ts0wMsSb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v14-20020a65460e000000b0046ec3bd90bbsi5687648pgq.60.2022.10.28.06.41.00; Fri, 28 Oct 2022 06:41:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Ts0wMsSb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231339AbiJ1NiZ (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231164AbiJ1Ng4 (ORCPT ); Fri, 28 Oct 2022 09:36:56 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD7C11D81A7; Fri, 28 Oct 2022 06:36:54 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5E830B82A3B; Fri, 28 Oct 2022 13:36:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5709AC4FF08; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=mYIbphH61ygAshc0/AeTkkmyeoct/Novzft8mwHEBDU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ts0wMsSbijgMNoPwccyMviMwaXjukyT4SUPruUjedLnOqNlKOfzO0dumIADDEW7/n OQWd8Xqv06KsZCYZauASvzKxxarhvcXWe4o1kSheaMVCZ56qVVjAtUXD539BTeZxrl Za6bnsq2hWUWrIoQ66EY4t9GkDGkh38memcdWD8gZkoG5m/Zt+54jO4PbOQaaJ17hE pMwaF7ewQWDyGj0lxFLHNbMr1wRdJTrjHpNOaxPIR1NW4EOQhyvgZiY3FQXUZce+Zu gTO+QuI/X3o8Bsbjs4FhbXmjVUzr95ELVPJ95vfOHPZ4KB67zwO/8gGYVdV3GoQR4c iUcnkg3JGxpsQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rN-NM; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v4 11/16] dt-bindings: phy: qcom,qmp-pcie: add sc8280xp bindings Date: Fri, 28 Oct 2022 15:35:58 +0200 Message-Id: <20221028133603.18470-12-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938940391788305?= X-GMAIL-MSGID: =?utf-8?q?1747938940391788305?= Add bindings for the PCIe QMP PHYs found on SC8280XP. The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as PCIe2A and PCIe2B). The configuration for a specific system can be read from a TCSR register. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 165 ++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml new file mode 100644 index 000000000000..80aa8d2507fb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (PCIe, SC8280XP) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,sc8280xp-qmp-gen3x1-pcie-phy + - qcom,sc8280xp-qmp-gen3x2-pcie-phy + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 6 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + items: + - const: phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + qcom,4ln-config-sel: + description: PCIe 4-lane configuration + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of PCIe 4-lane configuration register + - description: offset of configuration bit for this PHY + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + then: + properties: + reg: + items: + - description: port a + - description: port b + required: + - qcom,4ln-config-sel + else: + properties: + reg: + maxItems: 1 + +examples: + - | + #include + + pcie2b_phy: phy@1c18000 { + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; + reg = <0x01c18000 0x2000>; + + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2B_PIPE_CLK>, + <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + power-domains = <&gcc PCIE_2B_GDSC>; + + resets = <&gcc GCC_PCIE_2B_PHY_BCR>; + reset-names = "phy"; + + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + #clock-cells = <0>; + clock-output-names = "pcie_2b_pipe_clk"; + + #phy-cells = <0>; + }; + + pcie2a_phy: phy@1c24000 { + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; + reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; + + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, + <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2A_PIPE_CLK>, + <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "pipediv2"; + + power-domains = <&gcc PCIE_2A_GDSC>; + + resets = <&gcc GCC_PCIE_2A_PHY_BCR>; + reset-names = "phy"; + + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + qcom,4ln-config-sel = <&tcsr 0xa044 0>; + + #clock-cells = <0>; + clock-output-names = "pcie_2a_pipe_clk"; + + #phy-cells = <0>; + }; From patchwork Fri Oct 28 13:35:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12280 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836539wru; Fri, 28 Oct 2022 06:38:34 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6rR0d+0w5cLpvGaD5w371XnwTuk200h2/YdZ5VB5veVZi5SsLX40p0ReL4j5yYkuZxgwgK X-Received: by 2002:a17:902:e74f:b0:186:a962:8f92 with SMTP id p15-20020a170902e74f00b00186a9628f92mr27032182plf.41.1666964313824; Fri, 28 Oct 2022 06:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964313; cv=none; d=google.com; s=arc-20160816; b=sDb67Bo0WkigpgFPWba54SD4vTh/Fj/tTrUFTRUsGQXa1rYYC+TFwJXiJtxcvVeq77 RVurOndEEqaJB4PMRgdcWX38ESg2NlF7WIYXwsRAaTfaTD3FPH+05823KpGFkaBj0oZ/ j0XkkRX0zaeCN3ZVCj/+y1E01kio5CSiA1vlawDpWfUBORiIWslkowZmxKb0jVqxtqlz 9VsLGZVP82J8T3tTaCKeZEJ/eZ9Y/3YQA7NTtgSASgcvQWq4JaD41Fa9sqQNSk4aFvgo yKoWekpw1aOGEmsPuCPcbm0ZMWe3ccY1si5j98RPiV3d6MDs4WjGXZVOmHYP+6AGF64E l9ww== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f3-20020a170902f38300b0017f83500442si4423136ple.491.2022.10.28.06.38.19; Fri, 28 Oct 2022 06:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="r/iO+1K2"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231253AbiJ1Nhc (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231232AbiJ1Ngw (ORCPT ); Fri, 28 Oct 2022 09:36:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 992DC6450; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 448DE6288F; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 570C6C4FF0E; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=3KMG8nKUfsK556dcluPR1X8C5si2ibVB5wsNOm4GQn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r/iO+1K2aXBr2bXXJPoXqoTanWnaZElOnzumzASiVmlylL8LSpSqmSiQodvmmNzra D13AgpgjvvQ+NLK1TplQ9uC+Ix276nO/Ut9cthhCA1UxS0LGsB0H68XvnO8hvIEbWO 8FjJ3EWJulDE5tZrwMaBPeQvmrMRUlRfkUb2/s7wVKiyOvWPvmu2h+6Q6pguMiGhcG v/yl+7k6Yz6AJvq3zt5gmv/+IwudTJo+rz0oo6L5Vbb4tCSrBtloxrQ3HzcbTVoWFY CZElUErN4WDDqvGiKrNIHOYjK6O6OCo9iwZclpapqRJtSwM3g766h/eY20NktxF0o0 IZ8i8z2nA4Bjw== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rQ-Qc; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 12/16] phy: qcom-qmp-pcie: restructure PHY creation Date: Fri, 28 Oct 2022 15:35:59 +0200 Message-Id: <20221028133603.18470-13-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938772297464251?= X-GMAIL-MSGID: =?utf-8?q?1747938772297464251?= In preparation for supporting devicetree bindings which do not use a child node, move the PHY creation to probe() proper and parse the serdes resource in what is now the legacy devicetree helper. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 36 +++++++++++------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index f57d10f20277..2f4bdef73395 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2147,14 +2147,15 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); } -static int qmp_pcie_create(struct qmp_pcie *qmp, struct device_node *np) +static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) { + struct platform_device *pdev = to_platform_device(qmp->dev); const struct qmp_phy_cfg *cfg = qmp->cfg; struct device *dev = qmp->dev; - struct phy *generic_phy; - int ret; - qmp->mode = PHY_MODE_PCIE_RC; + qmp->serdes = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qmp->serdes)) + return PTR_ERR(qmp->serdes); /* * Get memory resources for the PHY: @@ -2209,16 +2210,6 @@ static int qmp_pcie_create(struct qmp_pcie *qmp, struct device_node *np) "failed to get pipe clock\n"); } - generic_phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); - if (IS_ERR(generic_phy)) { - ret = PTR_ERR(generic_phy); - dev_err(dev, "failed to create PHY: %d\n", ret); - return ret; - } - - qmp->phy = generic_phy; - phy_set_drvdata(generic_phy, qmp); - return 0; } @@ -2243,10 +2234,6 @@ static int qmp_pcie_probe(struct platform_device *pdev) WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); WARN_ON_ONCE(!qmp->cfg->phy_status); - qmp->serdes = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(qmp->serdes)) - return PTR_ERR(qmp->serdes); - ret = qmp_pcie_clk_init(qmp); if (ret) return ret; @@ -2263,7 +2250,7 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (!child) return -EINVAL; - ret = qmp_pcie_create(qmp, child); + ret = qmp_pcie_parse_dt_legacy(qmp, child); if (ret) goto err_node_put; @@ -2271,6 +2258,17 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (ret) goto err_node_put; + qmp->mode = PHY_MODE_PCIE_RC; + + qmp->phy = devm_phy_create(dev, child, &qmp_pcie_phy_ops); + if (IS_ERR(qmp->phy)) { + ret = PTR_ERR(qmp->phy); + dev_err(dev, "failed to create PHY: %d\n", ret); + goto err_node_put; + } + + phy_set_drvdata(qmp->phy, qmp); + of_node_put(child); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); From patchwork Fri Oct 28 13:36:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp837404wru; Fri, 28 Oct 2022 06:40:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5uNxfrGZoHbxDr/Vf7zKrT9i1javk573iw8fvUmHLl+ipeRxj3NMZO4aseJ8Q/NRHoQH/M X-Received: by 2002:a17:90a:f2cb:b0:213:9afa:d13a with SMTP id gt11-20020a17090af2cb00b002139afad13amr1706290pjb.180.1666964431946; Fri, 28 Oct 2022 06:40:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964431; cv=none; d=google.com; s=arc-20160816; b=RwJ6fzcjnlSP4lGKZ77LjZX5qxBOcjbdEN6iBkFA6cV8doI8WgSHk6OxWHIur7x5pp +1gRUES6M8hOhXXyaUZn1elz/6KOTIjUvrBFgOPMKMqGbMJdgh/d6U76CbYt8P0K99Ip 5kT+2eHEKVWxDnkJ6rwySrRX0icH16w2T+HARxf/8IuRi4FHT2AXUtKmcV7LEYhvat12 CIUaEWLN0P6OYfX5KAKrLTT8EzZJHVaoLR+2MQmPBMgyrxzB8WyLP30Pu+Jw4noDCG7y cg9FYj7ISwFYMWpZeU12UZB/Us2kng0pLYIbCuJpDwVvE/sKzEeEOzrICy5zUO2Z4IJT OYbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=S2aZ10XddYViPMvP2wnRw0b7CFM1AgqB3O1GuYKD30k=; b=yXCuiFqKj8v/xYeZtvg5boWCdk6PHwZBIgDlW0zvI9eG75fneKSCigG3QCm3MFgMg/ 208oARMc62Ukb71583e+SdInz/nHhXas3RmZvhAADDijuoUP7kAvKkpEgcVVMeY5WDjz iCa9a/IfC31w5IiVb8K4ViYg7c9IVH+R5tMURlwuPL7oTv3M95Mjx9EuMv8xHRpQoZx/ 7TTlRzIV3reHCti8DHTCJODPuWJqA7Ysge3vvEOV+WiMPq2pMhY6rLs5Q34Qfjea9f7D H+R5MjanoWtM2bL1D92jSmBearfm1Ozp5q9msmWWMQ/y2FLPJw6GeEDQyYNF4JY6szYH oZtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=sk4uPyCT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b3-20020a63d303000000b0046ec3853223si5828991pgg.1.2022.10.28.06.40.16; Fri, 28 Oct 2022 06:40:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=sk4uPyCT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231334AbiJ1NiU (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231160AbiJ1Ngz (ORCPT ); Fri, 28 Oct 2022 09:36:55 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB0B0132EB7; Fri, 28 Oct 2022 06:36:54 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 98CD8B82A3F; Fri, 28 Oct 2022 13:36:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7706FC4FF15; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=4mnICkBWbb6C7gqpfuGXYvIo4Kc1xOnaotX3R6uU03c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sk4uPyCTXTh5o+YLVTb0WPJGpz+bDOcphYNAJBKB0ahD2ukoIK5gUhYRuhtWrP9Eo VXc6gN5hcZZedXm/W1W22E4lDfRreT3LO3QZ65R2F9vZQfWV65pT5bWe6jcJNyruzA TL6wDSkyyJ5EqU6Qx0gTg+2udrxgxUdFAiW828shHmp1ZmKMtezkEk8xmNeyPj2yDg xYhW6eIPpoz1mhBqa2UJMAhK8cd+VpXsthyz+wqSw0Dv7VWQyq1x8bV5rCcP+HqCfY f4AbDskb2txOmALbvr+tKM93K/GBBFq4ufsecfaFotrIwZhZcnTAI6X7BcVD99S3RI wcGaxDce6SLgQ== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXH-0004rT-Tk; Fri, 28 Oct 2022 15:36:35 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 13/16] phy: qcom-qmp-pcie: fix initialisation reset Date: Fri, 28 Oct 2022 15:36:00 +0200 Message-Id: <20221028133603.18470-14-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938896387115533?= X-GMAIL-MSGID: =?utf-8?q?1747938896387115533?= Add the missing delay after asserting reset. This is specifically needed for the reset to have any effect on SC8280XP. The vendor driver uses a 1 ms delay, but that seems a bit excessive. Instead use a 200 us delay which appears to be more than enough and also matches the UFS reset delay added by commit 870b1279c7a0 ("scsi: ufs-qcom: Add reset control support for host controller"). Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2f4bdef73395..9c8e009033f1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1866,6 +1866,8 @@ static int qmp_pcie_init(struct phy *phy) goto err_disable_regulators; } + usleep_range(200, 300); + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); if (ret) { dev_err(qmp->dev, "reset deassert failed\n"); From patchwork Fri Oct 28 13:36:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836998wru; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM79M5G3HksO8ZmBpjAuCMlCI908+oL+/+csiyol25sJ5OyX/dztIhWLjAmLWiX4NtTZnjRI X-Received: by 2002:a17:902:cccc:b0:178:a9b3:43e6 with SMTP id z12-20020a170902cccc00b00178a9b343e6mr54138483ple.92.1666964378583; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964378; cv=none; d=google.com; s=arc-20160816; b=brDpfFT5f7m5m7TlHVymZ7QmALty6+sbbfDigCNW/xCvkjYGwQ0bC3IKvGsgZyEmQ+ YICVpVbRgPr5zaGtWUXidKoo9LMPUGOWRYnh5aF0gEyAXRK3Euynb+nTAANu8/kmk1Sv QHNZNsMslbluXe3y2Bb4Yz289j4fzeohV8comRs6x0OA3BFXYr/JPosayrol7OApewkA WgxYEOlZ4jM32pbUHMLRiwe+Hb0gRTKKX5NQ9E573psRRDcoirWBYzfxbT/g7kqL06X3 k5lx0QicyqxWwTSId6i90dT40Kc4rH1V9foAvndcziTDqU8Q+ovvd1RLFVLmQHz5jUWS 5DyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kRTgSbbdyP9DMYlPZLDEDiLP8xa21UgIEBBSVlncjFE=; b=LYl1j3o1+iLFcpn1CMdUQon4+Or2J3LG+qpAfScZrabjNRPyH8anJN54Brz+v9rMg+ aUEf+5598nSjKyebdpVuZW7lRyXj1XQUXu9ytjZ7ZaPA0ydhcjnSCsp9VO2zoGmHDX8J HDReD4MEZ0WfY0u/XcwGG57PO5vYDhu9wasEaFR3ofDkika49xdnfefuTtmWT6P/xH3+ 9cub6SsSUy4n8LPXmgvhCGd6Qzcs52wczO2zYbgZLxkVjXb4AiGhVQxOGVWlJ6wRteko SxOsRbKFD2qAA5XTjfJiLQWb2pWZVfbH/BTnoQXS0KX2ES0laVFTiN8paJ6RQG5KfMb7 Ax9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=UoiDpFJL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o5-20020a056a001bc500b00544ce272399si5298908pfw.173.2022.10.28.06.39.24; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=UoiDpFJL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231194AbiJ1Nhi (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231234AbiJ1Ngw (ORCPT ); Fri, 28 Oct 2022 09:36:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9937A16DC3C; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 671DC62888; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76CBEC4FF0F; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=2Jgp4ZieairTWItDvMt6Il3O/PFk+wuEeuWg97cDLZQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UoiDpFJLUFYer1+IhdwQNXcrkYWWZuZJZ4N5cVMye3enhFWVQ1dJAHrX71KpW8MyY LWDkTsmWpMzBTWBDF8IeRwxYmuV/Lcphzp2qk8NEjPRZOMOlEiI8AvEUPTTKsyvFA4 QMMDI5R0SCSDKKjEERcRmtEK76PgWebx24+YTlfDAUupocwOoYrVWP8tRbwUbXQgxy Jf8nxjpcxcuVifWDQjxgDshg0ZQtydytnNFOwTMVSiTrE3DUt72DMkqMn1V0nVC2Cv 9dVWCutgLhGZhDJNaBjycudVb3vfUAEAEHxA++LtLL0X3Jr7cFzRId9K77hTaBwY27 9gKkKRBo/t85w== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXI-0004rW-0T; Fri, 28 Oct 2022 15:36:36 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 14/16] phy: qcom-qmp-pcie: add support for pipediv2 clock Date: Fri, 28 Oct 2022 15:36:01 +0200 Message-Id: <20221028133603.18470-15-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938839968188165?= X-GMAIL-MSGID: =?utf-8?q?1747938839968188165?= Some QMP PHYs have a second fixed-divider pipe clock that needs to be enabled along with the pipe clock. Add support for an optional "pipediv2" clock. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 25 ++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9c8e009033f1..758457943f2b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1378,8 +1378,10 @@ struct qmp_pcie { void __iomem *tx2; void __iomem *rx2; - struct clk *pipe_clk; struct clk_bulk_data *clks; + struct clk_bulk_data pipe_clks[2]; + int num_pipe_clks; + struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; @@ -1923,11 +1925,9 @@ static int qmp_pcie_power_on(struct phy *phy) qmp_pcie_init_registers(qmp, &cfg->tables); qmp_pcie_init_registers(qmp, mode_tables); - ret = clk_prepare_enable(qmp->pipe_clk); - if (ret) { - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); + ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); + if (ret) return ret; - } /* Pull PHY out of reset state */ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -1950,7 +1950,7 @@ static int qmp_pcie_power_on(struct phy *phy) return 0; err_disable_pipe_clk: - clk_disable_unprepare(qmp->pipe_clk); + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); return ret; } @@ -1960,7 +1960,7 @@ static int qmp_pcie_power_off(struct phy *phy) struct qmp_pcie *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; - clk_disable_unprepare(qmp->pipe_clk); + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); /* PHY reset */ qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); @@ -2154,6 +2154,7 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np struct platform_device *pdev = to_platform_device(qmp->dev); const struct qmp_phy_cfg *cfg = qmp->cfg; struct device *dev = qmp->dev; + struct clk *clk; qmp->serdes = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(qmp->serdes)) @@ -2206,12 +2207,16 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np } } - qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); - if (IS_ERR(qmp->pipe_clk)) { - return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + clk = devm_get_clk_from_child(dev, np, NULL); + if (IS_ERR(clk)) { + return dev_err_probe(dev, PTR_ERR(clk), "failed to get pipe clock\n"); } + qmp->num_pipe_clks = 1; + qmp->pipe_clks[0].id = "pipe"; + qmp->pipe_clks[0].clk = clk; + return 0; } From patchwork Fri Oct 28 13:36:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 12290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp836997wru; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6FPKsVyV5dkKVLjesKW/ejihsbkyIYd3iO0mrEirLNy38tPV5NHa7cGP4rOnBFPODO92eV X-Received: by 2002:a17:902:f546:b0:186:c6d7:6556 with SMTP id h6-20020a170902f54600b00186c6d76556mr18119888plf.109.1666964378360; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666964378; cv=none; d=google.com; s=arc-20160816; b=05d+fPqFGchirByaqx0evd9HlvgQFQV7I8Ycn1+4eD8rQ4ywgAuw0AX3IGGzy5P36j McSJQXhhGwX/qpmjNcZeV03M4Xd0kGG437WhJsyrLU4jBweg4lahUiBU3xrE+ZZLV98F JdTJ1w+5F7p7epn405r40rZ1TYY0tBqN1vvVJXZ833ZlnuW1xwpLG9lUcn5P5rSemHGp xOWDvftDl+XGBx79EntrRdYpCvctoJOqMgx5U2Cq1+I3j4uQNGOT7g+5t+v9qOzNYtmx jlYJb5KatPvdn57ssJ1OUHOX41ZpnfAmACjVGVjB8emtlGBK48PGsDpqZKs+EkuyRkKQ Km3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0XD1VLpBpwsruCyoCRXP9xXzM/BbeiqBPlEnaHEw7ek=; b=g9gTt5KiulrLZ/DESYZn9t3g2fvesDwV/Alr61O44/iwHBrY2PECQZCz9EIIJY69Ga MBb68c3L/BTuiFVtQa/PGE+echKXRI87gw4lf3rBOYQPLRcl9zLG5PgdfrUNpaOORg0V Odr13B0D9UOZszJjdSQjZepZAlN6LdcWDtC3NhnkpYG/Pqm99Tejw13zvD1BJDaVjygl iVzz3+3mvIs5NxJ8HUidF8HOMrgJgeIAxG5GIidC7TKkTM+IO7cLbGzc8Nt1XN5qgz4q PanECfIqe0aA3+fsOQkRPbdPAvpxQPO3fmxnFdSWdbuQeiuX7y8oiZ30pp4mp/EcZXB0 9PKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=em9zwbCQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i4-20020aa79084000000b005614fb190e4si4921541pfa.193.2022.10.28.06.39.24; Fri, 28 Oct 2022 06:39:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=em9zwbCQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231272AbiJ1Nhm (ORCPT + 99 others); Fri, 28 Oct 2022 09:37:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231235AbiJ1Ngw (ORCPT ); Fri, 28 Oct 2022 09:36:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 998A11D8F3D; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 77FB96288D; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB664C4FF40; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964210; bh=1DOLRpBCXMsC1CLNbbIY7iZuk8xMt+gnpUh7sFM8oiw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=em9zwbCQ1hevIv2lQwrXWFMoKKsp373j5apm7QEOvXntlBlIvle89bUdeHCtM/13u l6jeGxBKRkBWeVjaRi3BgaQbJuu8Yui15QPvoA64TKgWf9yBZIvsHvZ99GcqIEAXVW fOyTureTeTtckrfW8Nzmj2s9GDgjfRs+yDFCWzYwyrItnBBE/ieXrCZq2UAZ7+/yEj OPPC/hSgFvGrKM1ym6Esh06KN5tbJepCZ6R4dERQUFyKXEn/rFBHudss/vLAGWTu+I wj6RPLnfC+dMuiq0FEVVYCeXxFt6Ug/hZl+7dZNxXKGkgCrLAH44OKCQEyAYvTjYVn Jy549K4yW3P2A== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXI-0004rZ-3O; Fri, 28 Oct 2022 15:36:36 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 15/16] phy: qcom-qmp-pcie: add support for sc8280xp Date: Fri, 28 Oct 2022 15:36:02 +0200 Message-Id: <20221028133603.18470-16-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938761907115894?= X-GMAIL-MSGID: =?utf-8?q?1747938839834283017?= Add support for the single and dual-lane PHYs found on SC8280XP. Note that the SC8280XP binding does not try to describe every register subregion and instead the driver holds the corresponding offsets. Signed-off-by: Johan Hovold Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 299 +++++++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 2 + 2 files changed, 291 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 758457943f2b..2ba57b230342 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -834,6 +834,143 @@ static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; +static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), + QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), +}; + +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), @@ -1313,6 +1450,16 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), }; +struct qmp_pcie_offsets { + u16 serdes; + u16 pcs; + u16 pcs_misc; + u16 tx; + u16 rx; + u16 tx2; + u16 rx2; +}; + struct qmp_phy_cfg_tables { const struct qmp_phy_init_tbl *serdes; int serdes_num; @@ -1330,6 +1477,8 @@ struct qmp_phy_cfg_tables { struct qmp_phy_cfg { int lanes; + const struct qmp_pcie_offsets *offsets; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tables tables; /* @@ -1422,6 +1571,9 @@ static const char * const msm8996_phy_clk_l[] = { "aux", "cfg_ahb", "ref", }; +static const char * const sc8280xp_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "rchng", +}; static const char * const sdm845_pciephy_clk_l[] = { "aux", "cfg_ahb", "ref", "refgen", @@ -1441,6 +1593,16 @@ static const char * const sdm845_pciephy_reset_l[] = { "phy", }; +static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { + .serdes = 0, + .pcs = 0x0200, + .pcs_misc = 0x0600, + .tx = 0x0e00, + .rx = 0x1000, + .tx2 = 0x1600, + .rx2 = 0x1800, +}; + static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .lanes = 1, @@ -1700,6 +1862,76 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { + .lanes = 1, + + .offsets = &qmp_pcie_offsets_v5, + + .tables = { + .serdes = sc8280xp_qmp_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), + .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), + .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), + .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), + .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), + }, + + .tables_rc = &(const struct qmp_phy_cfg_tables) { + .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), + }, + + .clk_list = sc8280xp_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + +static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { + .lanes = 2, + + .offsets = &qmp_pcie_offsets_v5, + + .tables = { + .serdes = sc8280xp_qmp_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), + .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), + .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), + .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + + .tables_rc = &(const struct qmp_phy_cfg_tables) { + .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), + }, + + .clk_list = sc8280xp_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .lanes = 2, @@ -2220,11 +2452,49 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np return 0; } +static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) +{ + struct platform_device *pdev = to_platform_device(qmp->dev); + const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_pcie_offsets *offs = cfg->offsets; + struct device *dev = qmp->dev; + void __iomem *base; + int ret; + + if (!offs) + return -EINVAL; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + qmp->serdes = base + offs->serdes; + qmp->pcs = base + offs->pcs; + qmp->pcs_misc = base + offs->pcs_misc; + qmp->tx = base + offs->tx; + qmp->rx = base + offs->rx; + + if (cfg->lanes >= 2) { + qmp->tx2 = base + offs->tx2; + qmp->rx2 = base + offs->rx2; + } + + qmp->num_pipe_clks = 2; + qmp->pipe_clks[0].id = "pipe"; + qmp->pipe_clks[1].id = "pipediv2"; + + ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); + if (ret) + return ret; + + return 0; +} + static int qmp_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *child; struct phy_provider *phy_provider; + struct device_node *np; struct qmp_pcie *qmp; int ret; @@ -2253,21 +2523,24 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (ret) return ret; - child = of_get_next_available_child(dev->of_node, NULL); - if (!child) - return -EINVAL; - - ret = qmp_pcie_parse_dt_legacy(qmp, child); + /* Check for legacy binding with child node. */ + np = of_get_next_available_child(dev->of_node, NULL); + if (np) { + ret = qmp_pcie_parse_dt_legacy(qmp, np); + } else { + np = of_node_get(dev->of_node); + ret = qmp_pcie_parse_dt(qmp); + } if (ret) goto err_node_put; - ret = phy_pipe_clk_register(qmp, child); + ret = phy_pipe_clk_register(qmp, np); if (ret) goto err_node_put; qmp->mode = PHY_MODE_PCIE_RC; - qmp->phy = devm_phy_create(dev, child, &qmp_pcie_phy_ops); + qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); if (IS_ERR(qmp->phy)) { ret = PTR_ERR(qmp->phy); dev_err(dev, "failed to create PHY: %d\n", ret); @@ -2276,14 +2549,14 @@ static int qmp_pcie_probe(struct platform_device *pdev) phy_set_drvdata(qmp->phy, qmp); - of_node_put(child); + of_node_put(np); phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); return PTR_ERR_OR_ZERO(phy_provider); err_node_put: - of_node_put(child); + of_node_put(np); return ret; } @@ -2303,6 +2576,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sc8180x-qmp-pcie-phy", .data = &sc8180x_pciephy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", + .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", + .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, }, { .compatible = "qcom,sdm845-qhp-pcie-phy", .data = &sdm845_qhp_pciephy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h index 2e19fb3f051e..a469ae2a10a1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -8,6 +8,8 @@ #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ /* Only for QMP V5 PHY - PCS_PCIE registers */ +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 From patchwork Fri Oct 28 13:36:03 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p2-20020a17090a2c4200b0020d65f31df8si8739796pjm.143.2022.10.28.06.38.55; Fri, 28 Oct 2022 06:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=OCdJX9ti; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231314AbiJ1NiF (ORCPT + 99 others); Fri, 28 Oct 2022 09:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230473AbiJ1Ngx (ORCPT ); Fri, 28 Oct 2022 09:36:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 996EA1D8F39; Fri, 28 Oct 2022 06:36:51 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 72A8B62893; Fri, 28 Oct 2022 13:36:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB69FC4FF44; Fri, 28 Oct 2022 13:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666964209; bh=SyN+Tar5QxF3fPxzvOG67m8Mtp2DczSUPcNYJXgQv7U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OCdJX9tia7t7c2Qw7z36qY9RQh9RwCYzSPMxsq7MNYzKEjgHXCePm6L+NkXcelIfv HkhTCLLkDYwikkrFlu9kT8P5pLwpVS6YyFMTM29m6px6f+GKj1znfnP4KLQDfPXzdI 4Lf6qqlA5phOpMOJs4imaWCUXP2XDnikObdQNapbrBWbAivF+p924rhaHX8N2dXh1J VSekU2ZNA06DM2stVPfqp8EDnJsm6Vcb/DJG/50gDOGNjhunALJJpPm8QKEWw3OQcd Wql0WAP8UPdCsVRc4jJr6dxWnKq2lPtSkUvaLpxDBbY7ce00/EU+ZVdBuW1QZdL9Qv 0TjQ3CmbDdpZg== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ooPXI-0004rd-6b; Fri, 28 Oct 2022 15:36:36 +0200 From: Johan Hovold To: Vinod Koul Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 16/16] phy: qcom-qmp-pcie: add support for sc8280xp 4-lane PHYs Date: Fri, 28 Oct 2022 15:36:03 +0200 Message-Id: <20221028133603.18470-17-johan+linaro@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221028133603.18470-1-johan+linaro@kernel.org> References: <20221028133603.18470-1-johan+linaro@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747938811015843381?= X-GMAIL-MSGID: =?utf-8?q?1747938811015843381?= The PCIe2 and PCIe3 controllers and PHYs on SC8280XP can be used in 4-lane mode or as separate controllers and PHYs in 2-lane mode (e.g. as PCIe2A and PCIe2B). Add support for fetching the 4-lane configuration from the TCSR and programming the lane registers of the second port when in 4-lane mode. Reviewed-by: Dmitry Baryshkov Signed-off-by: Johan Hovold --- drivers/phy/qualcomm/Kconfig | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 117 +++++++++++++++++++++++ 2 files changed, 118 insertions(+) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 5c98850f5a36..eb9ddc685b38 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -54,6 +54,7 @@ config PHY_QCOM_QMP tristate "Qualcomm QMP PHY Driver" depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST) select GENERIC_PHY + select MFD_SYSCON help Enable this to support the QMP PHY transceiver that is used with controllers such as PCIe, UFS, and USB on Qualcomm chips. diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 2ba57b230342..1425bdba68e7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -886,6 +888,10 @@ static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), }; +static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), +}; + static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), @@ -1491,6 +1497,9 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tables *tables_rc; const struct qmp_phy_cfg_tables *tables_ep; + const struct qmp_phy_init_tbl *serdes_4ln_tbl; + int serdes_4ln_num; + /* clock ids to be requested */ const char * const *clk_list; int num_clks; @@ -1518,6 +1527,7 @@ struct qmp_pcie { struct device *dev; const struct qmp_phy_cfg *cfg; + bool tcsr_4ln_config; void __iomem *serdes; void __iomem *pcs; @@ -1527,6 +1537,8 @@ struct qmp_pcie { void __iomem *tx2; void __iomem *rx2; + void __iomem *port_b; + struct clk_bulk_data *clks; struct clk_bulk_data pipe_clks[2]; int num_pipe_clks; @@ -1932,6 +1944,44 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { + .lanes = 4, + + .offsets = &qmp_pcie_offsets_v5, + + .tables = { + .serdes = sc8280xp_qmp_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), + .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), + .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), + .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + + .tables_rc = &(const struct qmp_phy_cfg_tables) { + .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, + .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), + }, + + .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, + .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), + + .clk_list = sc8280xp_pciephy_clk_l, + .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8250_pcie_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .lanes = 2, @@ -2054,6 +2104,24 @@ static void qmp_pcie_configure(void __iomem *base, qmp_pcie_configure_lane(base, tbl, num, 0xff); } +static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) +{ + const struct qmp_phy_cfg *cfg = qmp->cfg; + const struct qmp_pcie_offsets *offs = cfg->offsets; + void __iomem *tx3, *rx3, *tx4, *rx4; + + tx3 = qmp->port_b + offs->tx; + rx3 = qmp->port_b + offs->rx; + tx4 = qmp->port_b + offs->tx2; + rx4 = qmp->port_b + offs->rx2; + + qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); + qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); + + qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); + qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); +} + static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tables *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -2080,6 +2148,11 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + + if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { + qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); + qmp_pcie_init_port_b(qmp, tbls); + } } static int qmp_pcie_init(struct phy *phy) @@ -2452,6 +2525,37 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np return 0; } +static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) +{ + struct regmap *tcsr; + unsigned int args[2]; + int ret; + + tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, + "qcom,4ln-config-sel", + ARRAY_SIZE(args), args); + if (IS_ERR(tcsr)) { + ret = PTR_ERR(tcsr); + if (ret == -ENOENT) + return 0; + + dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); + return ret; + } + + ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); + if (ret < 0) { + dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); + return ret; + } + + qmp->tcsr_4ln_config = ret; + + dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); + + return 0; +} + static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) { struct platform_device *pdev = to_platform_device(qmp->dev); @@ -2464,6 +2568,10 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) if (!offs) return -EINVAL; + ret = qmp_pcie_get_4ln_config(qmp); + if (ret) + return ret; + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -2479,6 +2587,12 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->rx2 = base + offs->rx2; } + if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { + qmp->port_b = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->port_b)) + return PTR_ERR(qmp->port_b); + } + qmp->num_pipe_clks = 2; qmp->pipe_clks[0].id = "pipe"; qmp->pipe_clks[1].id = "pipediv2"; @@ -2582,6 +2696,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, + }, { + .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", + .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, }, { .compatible = "qcom,sdm845-qhp-pcie-phy", .data = &sdm845_qhp_pciephy_cfg,