From patchwork Mon Jun 26 11:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112881 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7412887vqr; Mon, 26 Jun 2023 04:36:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6VQUMlei1NLEqDkyGoK7hdNOYvM6HIb9IUl+Bmi2yoo4MApoDo0ja49wAug1MWfRMRpTHS X-Received: by 2002:a17:906:9b88:b0:988:98a3:fd44 with SMTP id dd8-20020a1709069b8800b0098898a3fd44mr20210410ejc.28.1687779366815; Mon, 26 Jun 2023 04:36:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779366; cv=none; d=google.com; s=arc-20160816; b=zkc545jhYJMdtk07+8c3Zwwt6sR0h/npDhoNlcGjXBxxN1QqqSQHVEQE7kz9Rq+QJ2 HWu+FjHlvmk5qvqR4DOrmEwDG96SFMclbYUHUEsJ/rTIQ/MzYMu5xezZFAKmbBYS9LDJ gNV/VAJ/cLNQHgjt2S8greYNA/UmOMh+19EqnIYDZDg6+O7WFkQpZLyv6ZSCGmJmmhvp MZ6equW98on/A+P6QNC7AV3JMQH+sM5X0DzAvL2O3t9S0zO3RZP5WnCTnYMzAHqov1iY H9a2WvJqYX+PjRuFhpBmTSHekLi+/wmxoOH/CJHyJ3/V8tiarr56UsNPEKK987ZSBhLi i4MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8OZmO8EQ4qgbFmtKj5ZzMjCQ/pk3oPAHrCY5XROnR2o=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=r2taYJKFqspRXKtxnh2yoHE/ZdA0F8dYh3W4JGE+knQEFnwc1jIXjIX1mSDzvlQae3 tAl9GW/5mlSmQwqU9xI9ud5rFGqjt16zqwAIIyQZbovhNAPq9/vX3n8FZHFjFTFI6RJR 0/mmIBDUNrzOlMvid81hHW0BiBYretA9BPCNetWGADwoNigGlElaG2yWAUKugU4WDmCP OXig38QIOo/+/qTh9EeVxqjKm19x+rWBzhHt+T7VMl78gpoqRhCsQGjnTkDV79BnRZtU mgDJCaofOz00uxkT7mdaync4U7Ms9NoXYuLzdq5y3yHRSQB0WVGIzhNJ6F9Ix71lt1pp wgOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="RS3M/voF"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qw3-20020a170906fca300b0098dfa5abc0bsi2181267ejb.88.2023.06.26.04.35.41; Mon, 26 Jun 2023 04:36:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="RS3M/voF"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbjFZLU4 (ORCPT + 99 others); Mon, 26 Jun 2023 07:20:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230164AbjFZLUx (ORCPT ); Mon, 26 Jun 2023 07:20:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1854FFF; Mon, 26 Jun 2023 04:20:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778450; x=1719314450; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mu+g58nhjsHPstxLBmB5/V/xzpUyBi/njYK6W3OCzlM=; b=RS3M/voFSpsuqh5KRfsnkmkUUqO2jVFsyRiaiqS+H10NhSyZ0VoJ/SbO JmiRZfbeHHQCIBTdxrUD1wup+OwUgjBIE67E0DxBDRKXaV23rwoO2eMpK t8lVlSRxFI3JFZPPwRyqGOXfGINfX9zOAeRUPr+zSTXum+xiCPOg7YPho ZiplFxYY9Zh5n2y8yK+vGu8H221tWPm+mahA3/1cffPO9dh1hGLWvXE17 qM5R6xGitLn4tcNH+gYc+bPfGJUmsG96zZDdmTluR0bseB/PHmqyj+PiH EcMKbSzIGboO23+zP+V0YEKr/sheeSRgZncpsp1/VGyY5dxtftPolPDZn Q==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="232170762" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:49 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:45 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Date: Mon, 26 Jun 2023 12:19:39 +0100 Message-ID: <20230626-silk-colonize-824390303994@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Zp2OijcNG2QSKXKrNz/jnk7bkS3lWHsdOCwgyctpfpk=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS3yV91hPUsrLUjn8U36bqs73+S/0OJyXVuhk5uSevTAp eKNbRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZy1pmRYWb8nHMvymR93EJYDRm2Ky 8q7dW8JPXC2lDym4nJi9//hRl+Mm7JDLa73Xc+8GGy2YJd9ywm9AssWMA/9ckcw1P5qrv1WAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764937114601495?= X-GMAIL-MSGID: =?utf-8?q?1769764937114601495?= From: Heiko Stuebner When filling hwcap the kernel already expects the isa string to start with rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT. So when recreating the runtime isa-string we can also just go the other way to get the correct starting point for it. Signed-off-by: Heiko Stuebner Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..742bb42e7e86 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -253,13 +253,16 @@ static void print_isa_ext(struct seq_file *f) */ static const char base_riscv_exts[13] = "imafdqcbkjpvh"; -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { int i; seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); + if (IS_ENABLED(CONFIG_32BIT)) + seq_write(f, "rv32", 4); + else + seq_write(f, "rv64", 4); + for (i = 0; i < sizeof(base_riscv_exts); i++) { if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) /* Print only enabled the base ISA extensions */ @@ -316,15 +319,14 @@ static int c_show(struct seq_file *m, void *v) unsigned long cpu_id = (unsigned long)v - 1; struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); struct device_node *node; - const char *compat, *isa; + const char *compat; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); + print_isa(m); if (acpi_disabled) { node = of_get_cpu_node(cpu_id, NULL); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && @@ -333,8 +335,6 @@ static int c_show(struct seq_file *m, void *v) of_node_put(node); } else { - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) - print_isa(m, isa); print_mmu(m); } From patchwork Mon Jun 26 11:19:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112879 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7412635vqr; Mon, 26 Jun 2023 04:35:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6DP/2YiS/n1AjBwzydzDJadt7XQlCDw5VMz7MWhS/z+fUX4mmiTzsrvDKglWAgHWfyvbG8 X-Received: by 2002:a05:6808:120d:b0:3a1:b9d7:3821 with SMTP id a13-20020a056808120d00b003a1b9d73821mr9154170oil.37.1687779343704; Mon, 26 Jun 2023 04:35:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779343; cv=none; d=google.com; s=arc-20160816; b=eCAb2dSh8ok+0c+VNOmq1enbPUN6tM/Yxwesa0YeFwE12267Pa+EaQaLdqgG6MGdO+ XJSsS0YoLOVillNMPNj9PmrL185r3p/W1hM8rJIeXw5mol5k6E/jdsrCu5T3VuT+nAI9 o3kHpGVR0P02OIjCIi89a4QsWmw/JW8KYWfw/iU4f19sDYn1jpTb5Txv8u2ERpBVWtah 8X2dz0MdvOe5eTlFaxiUcj1AMUU+n7ES7kCT+NN3Zh9iD7EWwDZykm4rqkGrol9DZc7p h+qwWYgfoU2psHEcD90xvw7+NJYPwRwjTn6NfluYusXpLd4daYReMktE/QKtb5TSqj25 0S1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pjbRQTj3/shGhEQNCzhOP4ATDodEOI10UsFTo44LWPI=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=r1l5Pclh6fnVUn7JuBjjJWaT/4MK5BLSjoygIkX839o+gb1O1iYDGy/gLVi1jZFfOc BLopYoI+1F1WyrebGuMoHtAWOY2PnPu5inAjnuEKngLqwAt0Us5Ro9RYC5PQIGGQ3RAs PMQcCqKOWXaPKEgYdbZiT5E0KZLtAS3mo4RcOEoRAHic6T5344TX61+REs/Qqzsq2JZR m+TJ91afmBAbFjUZqHwla3KV+/1rsMtJS0RdtJ6y27X9Z4yWZOkatARu9t2QdgISH548 499wES2nfZ7szQuLxEFXZLyg7xFa1NMGFN3elhWgZmXdJc7ejGfflxi/87GHdwIcwu5p qPRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=teoQKccp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 28-20020a630c5c000000b0055757030059si4830594pgm.3.2023.06.26.04.35.30; Mon, 26 Jun 2023 04:35:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=teoQKccp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbjFZLVA (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230175AbjFZLUx (ORCPT ); Mon, 26 Jun 2023 07:20:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE6DB10F; Mon, 26 Jun 2023 04:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778452; x=1719314452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=W1hk6ucl8KNm2U0fXh/wXmuimq2rclUouXAdbjBH3TA=; b=teoQKccpY6WOzG56JwUxFZ4v/3VIav/QRUU50tghDE+nHddM0tsP5vqG ybdWT2tajp0qNrkKzHY8pYTIVM9nC3AP5GdXdjYye79wSMQbblirZTauO xYNaW6FYlXbe3jzqFYciyBWaO9GhQOHOnxNsHwubEBQskfAVW53msfmKy Oy5frttUcP/Gh1n4xgZLOEdZytgss6616ik5WYebhIxbSA3zBRZgjYo/i i0zBJ0r1sOjGFAcO7ZswUSEZLaCuhB5XsUHUXrJtxkiaXDaE8ihct2q30 S2MMcVv0d/21RsSYb8YPk/FzkAeII8qYpFEpVPL4AsEBNdndkthRC9EF4 Q==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="220501420" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:48 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Date: Mon, 26 Jun 2023 12:19:40 +0100 Message-ID: <20230626-skydiver-frown-659b982a43ad@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=737; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=W1hk6ucl8KNm2U0fXh/wXmuimq2rclUouXAdbjBH3TA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS3zbNKQ3J0nbH6lftSZ2Rnpt8ivbm0VXvk5y+luhUXH4 k/7njlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExkzzdGhpmXL7yX/Km0bOKzqUo5Va ssct7t8czb1rt3rp6Jmsi55gcMf/gOCC7dLrsr2ElpSpft1TnRzJYmoTfWtsj/r/m2sk1IhwkA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764912851547224?= X-GMAIL-MSGID: =?utf-8?q?1769764912851547224?= isa_ext_arr cannot be empty, as some of the extensions within it are always built into the kernel. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 742bb42e7e86..01f7e5c62997 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -233,10 +233,6 @@ static void print_isa_ext(struct seq_file *f) arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - /* No extension support available */ - if (arr_sz <= 0) - return; - for (i = 0; i <= arr_sz; i++) { edata = &isa_ext_arr[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) From patchwork Mon Jun 26 11:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112880 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7412822vqr; Mon, 26 Jun 2023 04:35:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6G+l7Jvw0yQqTB1MQ8xIlHZP4AtYGT/DkeMcxBDY6BB9Tuac7ZercFpbx3FCKR01LMYkvc X-Received: by 2002:a05:6a00:2d94:b0:668:9658:2242 with SMTP id fb20-20020a056a002d9400b0066896582242mr22125544pfb.26.1687779359441; Mon, 26 Jun 2023 04:35:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779359; cv=none; d=google.com; s=arc-20160816; b=DmoY4UFy+0mhx3elyVJort+Y4vfHSrKr/CrsPv2jb0v1AIWutl1KnZ9213AERLKSfu 9sDMEOsju2gEICYUqeqXRhZc5+8BFBLHdFYZ7Km9qp7Oi5VRyIVcDZXsBNwOjaINNNBR WOQumx1KnHdUWWZ2nRJhlmbQqKQi99UHXhrbcLHvsKEqc0p5dqrCVUDSfmSlv2JgPvGP owmoxq5MZruRhlMhYPqw3wuzIxfeU07geNul0o5f+3eXmgBGhjBCrb+D01K1cL6o0aHI XZT4rm2wPWpxLk0UWye56SKPRFxM6lJ0xjt/ND8Q9kAQUM51DfSTuixID//7uACq1u6z 6iTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TiiLC52dgZuDSAqAqJFxkE+65PeJaNhh3V9b6zCCwXc=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=vm3CbAovDFjKfmhVnaUMsH6a1dyEBu52Fe6qqEMs4YZ3geXqUIsM/eVw9bQWqZKueA n2LR4eQKzJ3SO/Wb6kQ1g/w3+QDyt31ozrKhrq7ogOwrPx7l+dx07fj4ruBT/64qRwRj YeNzBOKSQ05nKbJP6dHPCKyywoxXiPIcj9EzvGhQSO2tcPed5PN9OCNubItjduriDFQM N2a5rnU1z0zJziP9KGWN/axDSUCHA3C/8fzG2QSJYdnH6bN+T+/ppbcvtU4LbGoAaOJA FpXve9xz9jO1tYr4KXXJ6axoMOhOYL5uNorquFyWsRHAx+SfoFNftJF7ZN4jOpncyTva Ii8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Liscz7bO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v10-20020a63f20a000000b0052c87a89084si4941172pgh.374.2023.06.26.04.35.46; Mon, 26 Jun 2023 04:35:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Liscz7bO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbjFZLVC (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230241AbjFZLU4 (ORCPT ); Mon, 26 Jun 2023 07:20:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64888FD; Mon, 26 Jun 2023 04:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778454; x=1719314454; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GzlNWSg0xDPHyhC9BUJXzvFuSqFJWq3a7gm62UBaiWE=; b=Liscz7bOs/VaRxL52umXtJjAITgui9exdh7VrE7lDtQnaJKmyxyzkIqs uEB+EL0iUa8QA7nhsLRoVGQLpXRaJZ5rhTAR9qnaD9RhsNV1IfNFDrsFZ 1zyfL1+v3rj/IQ2DydKmIHoBBY2V0NfFq8Wq6oBYTHLltx2FiljyGHhgK 4mCMB/biS08S50TwyL/74PReKxrBnECqBy6f9w9Z7ReXlK9hPVBDg9aJy /uvDSfEE56DOb1/lAYjsbMmTaeKzbrogW2WJ0hyhDJ7lQLEBEByr/KrMo vFpt85B1mn/i9pTg7ffRBHZSkaiRSxpYtUhimHU0846m/nrpOFydzUMT6 A==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="232170772" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:53 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:51 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Date: Mon, 26 Jun 2023 12:19:41 +0100 Message-ID: <20230626-endowment-crave-d72f9423c5b3@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8465; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GzlNWSg0xDPHyhC9BUJXzvFuSqFJWq3a7gm62UBaiWE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS3y311YYWCn0rfm58uG9udUaPsW7zx1fHpukde/Ywkfu zto9HaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjI912MDEvUOgyM6gMnXzn8kf9l0B 3WQw0pQisUc59sObZ0cWVvkQ4jQ0fjwj8607dFXijmzdz9TTiF5+OFk6XBPwJPM+z+4zVBmhEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764929394935885?= X-GMAIL-MSGID: =?utf-8?q?1769764929394935885?= To facilitate using one struct to define extensions, rather than having several, shunt isa_ext_arr to cpufeature.c, where it will be used for probing extension presence also. As that scope of the array as widened, prefix it with riscv & drop the type from the variable name. Since the new array is const, print_isa() needs a wee bit of cleanup to avoid complaints about losing the const qualifier. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 3 ++ arch/riscv/kernel/cpu.c | 75 +--------------------------------- arch/riscv/kernel/cpufeature.c | 68 ++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 73 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..7a57e6109aef 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,9 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; +extern const struct riscv_isa_ext_data riscv_isa_ext[]; +extern const size_t riscv_isa_ext_count; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 01f7e5c62997..61fb92e7d524 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -160,81 +160,10 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted after - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be listed - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be listed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed, they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described above. - */ -static struct riscv_isa_ext_data isa_ext_arr[] = { - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), - __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), - __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; - int i = 0, arr_sz; - - arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; - - for (i = 0; i <= arr_sz; i++) { - edata = &isa_ext_arr[i]; + for (int i = 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) continue; seq_printf(f, "_%s", edata->uprop); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..f0ae310006de 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,6 +99,74 @@ static bool riscv_isa_extension_check(int id) return true; } +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop = #UPROP, \ + .isa_ext_id = EXTID, \ + } + +/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + * + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. + */ +const struct riscv_isa_ext_data riscv_isa_ext[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), +}; + +const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); + void __init riscv_fill_hwcap(void) { struct device_node *node; From patchwork Mon Jun 26 11:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112874 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7408283vqr; Mon, 26 Jun 2023 04:28:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6EjB7CiPF40sIr1ZpWT3e9+Vx8fKI0olB0UaJuNvk3hfEv3GYrBhdW5NhWW9JiRAZSlQfJ X-Received: by 2002:a05:6a00:8cc:b0:666:ae6b:c484 with SMTP id s12-20020a056a0008cc00b00666ae6bc484mr35904854pfu.13.1687778921022; Mon, 26 Jun 2023 04:28:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687778921; cv=none; d=google.com; s=arc-20160816; b=QgiQLRGdk8MaRuhOUDETxHri8gxCFIQPr39Fo0fOZDscm7cPPchktCndX9CcL3SGGw EbzPHqpOjvSX53BgXz0/8iGeI6JsMyZIHJiuq58D5+FIHGzEtZJpooQPXWplbLbi2071 XszRhgmJq4lnreVVttDL0/qwRXczAhkWLUC3D7evqhA5+v3hsA1C97TWY+u2k052mzzf c65BfLFITuW3Bs+TwX0HniYktNr/CkKiMnu49grCGgtbW7mcpqvqLCmMQR6JQm9mQReI rbx91RUMVBNchsKvjeDzycPhsKmjwOi6C0SwI6v9nkWDans5rk1UMJLEoyJlhm3UQWNY wBoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Iu0oIKQaNCiyZc9EFyINu4/dMS547r+wcjiUlpQ391Y=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=ZYsvU/WImqr3WKqYGlYszPCzHBhqdxxP6PLzaqt6DynTkUlyCFKiG+h1M8YIriTgk1 miZViTWUtRTQ4b4BCnBh4sO0cS2g8RDNDgv7LDwjtfKH6Ec0c2TW6yt99WHBN5YsnYMN GDMPiBn1eX56eC3MF+s2NmwhG6687k4gewH1vXPD1dONaRaYoo06H7RQS/n1Bz2FJihX swDS9lLZRmlJpuV9TOos8X1yWV9oRTaGfFju4PNOlgsgMSRgAjAVVISZGr/W3yb6yIkG Z0Ad+KpKa4tUe9sf5icUtx7quBqiq1aKe6fBZ8f6Pm35w2Z1Z5Tksqqq8ALsVA128Ixf gyRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=NzPJj8J5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u70-20020a627949000000b00672ad8f037esi2964960pfc.231.2023.06.26.04.28.28; Mon, 26 Jun 2023 04:28:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=NzPJj8J5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230497AbjFZLVM (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230359AbjFZLVH (ORCPT ); Mon, 26 Jun 2023 07:21:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EE9D119; Mon, 26 Jun 2023 04:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778458; x=1719314458; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EVl3YYff+bNDCeEIAFYAaLo4NmZDjHChTG2zsWTb6SY=; b=NzPJj8J5Jw0LvTiEo8yuJmGwL7A1WtkSraZwFQUc4Mh48FZRz+DUPZJQ lfwQ0vyhZxa8vh0ON4D4MJ2lUf8+TqlPjQDvthsaFv2OMQBddxh1JTpMD 0qcwMw+4zBaf7Tl1Vg7Ab4tAgiwVOtpCa3AO32e4YUgdlN/nBk07Uht0R ryubOlQgzfyHpPdPJUflaEZJdhl2zP/mbay86a020EsJQfNjeXq8qslEu 7jPndsCAcALffzVItPzt7w77AHdEwNrzsG0KGtzMNM3FbGe3GGBygmC3v 42cUnpbyB0PO7PFJe129JpXXdiAaFqtE5qkzjAw3wlGZN+iP+bxPI/5yV w==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="220501431" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:57 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:53 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Date: Mon, 26 Jun 2023 12:19:42 +0100 Message-ID: <20230626-thieving-jockstrap-d35d20b535c5@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3378; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=EVl3YYff+bNDCeEIAFYAaLo4NmZDjHChTG2zsWTb6SY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/xOHvARZg/f8YlLI9BKZOvsxbtEVnyNvPPa8OTs1nOC uU//dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiS6UY/hlMYgidF17//8BOu2M95s kC8543Oka+Pn0wUDbz6aT4NW0M/xNFHrouDuHn6tGzLj2UOu9zZ+2k1IrISZGVqwv9bH5u5wAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764470305052280?= X-GMAIL-MSGID: =?utf-8?q?1769764470305052280?= In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather than duplicating the list of extensions with individual SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious comments from the struct, rename uprop to something more suitable for its new use & constify the members. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 6 ++---- arch/riscv/kernel/cpu.c | 5 +++-- arch/riscv/kernel/cpufeature.c | 26 +++++++------------------- 3 files changed, 12 insertions(+), 25 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7a57e6109aef..36f46dfd2b87 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -70,10 +70,8 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; + const unsigned int id; + const char *name; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 61fb92e7d524..beb8b16bbf87 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,9 +164,10 @@ static void print_isa_ext(struct seq_file *f) { for (int i = 0; i < riscv_isa_ext_count; i++) { const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + if (!__riscv_isa_extension_available(NULL, edata->id)) continue; - seq_printf(f, "_%s", edata->uprop); + + seq_printf(f, "_%s", edata->name); } } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f0ae310006de..b5e23506c4f0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id) return true; } -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } +#define __RISCV_ISA_EXT_DATA(_name, _id) { \ + .name = #_name, \ + .id = _id, \ +} /* * The canonical order of ISA extension names in the ISA string is defined in @@ -367,20 +366,9 @@ void __init riscv_fill_hwcap(void) set_bit(nr, isainfo->isa); } } else { - /* sorted alphabetically */ - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); } #undef SET_ISA_EXT_MAP } From patchwork Mon Jun 26 11:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112875 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7408748vqr; Mon, 26 Jun 2023 04:29:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6pDZ5/ZHiXaPiturasRyIWhRu2CAKSLDllqLSgoSxc9KNzU9I3R7PpkWcyciiMyzckm3l3 X-Received: by 2002:a17:90b:1943:b0:262:ff86:ac2d with SMTP id nk3-20020a17090b194300b00262ff86ac2dmr902923pjb.46.1687778973087; Mon, 26 Jun 2023 04:29:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687778973; cv=none; d=google.com; s=arc-20160816; b=F8iCjhwdmh1wdHM5zhli6H8cDryDd3lrxwJY74Ff3c2AWxnUg0nftfw+1ZvCIY6qby bg0/0WAQclKk8mQl2uHPlprvHCr56zz8pSWkpMCgDngt5u7Fcr6Rfof24M/DRuBU0jmm hZkh9qc/v8+E1oLftc13TIUABuVRMlS/yd/p3b7vkRzE3JuTdb4ZneZnF+8tHuK0AlmI gcUwL4KEiAVohy8ivj8I6lkl2hyRZsDWHx/jhuQg4afSNV0iov/WIDm/P6yYC853vWDd JbI1XyweTFgGD4aQCMJK+eyPeK84Iam9iMvGEZfflnmXQOF6GCEvaNvzNlwAI6tVhLdL QSlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bZcGGdg3NgUiG6AWwmwYW4LbE3NRje6IgMvCFC3aU20=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=vLaB3f+DfzuF4GI/griJyW1Rk8R0xL8sRsiD6WOpIyo9EfwIYTCqRLX/eFE8dF0R25 9B8lNU1QXlh5jjeOlB+fy+T8DcpkBDkd/PDLdwWR3f4ByFA1Pr8s75XWg5qOYXSJdIAU l6zPcxwkKyhyDlXRnEtuTri5EYK8sJVUpicIQSojw3C2VeyLsrzLMmX4dLo+AXXVNTZq t0KE6XWRJ4R8v255uW7hRrQJ9Mxa0oI+uImFf0Z7/sdJtS+rio8WPbS3SSl2Qqv+AKua M2+BrR8IuoYakiJl4uF3R9+lRANwVtNAozRHwOPR0CfkPINTPIOh9OJmyeXAt27NnYp5 BXFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cHILVaRV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 190-20020a6308c7000000b0054ffec23b91si4811783pgi.153.2023.06.26.04.29.19; Mon, 26 Jun 2023 04:29:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=cHILVaRV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230474AbjFZLVP (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230290AbjFZLVJ (ORCPT ); Mon, 26 Jun 2023 07:21:09 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98795E7A; Mon, 26 Jun 2023 04:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778459; x=1719314459; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7P2ZuLVh/mHZ6Q4BNnYCrGzK8DdnxNYlyk5flnLKkc8=; b=cHILVaRVQrQNiHDtUFoF03bPU/H0ALPdH5ddPJeHTTAINhey0zBrvHPW jndP+ArScGVRvef+FSgBu5UV7rrhiJPv+94TlJPu3UmGJZPKgwfCQ8jsZ n61JFO8BOxEuxr2OAPE96dWdOkMZI27X24VzjE1q/37zkKy7c6p5IkhmI xVO0nLJ+c2cVPko7yfazIPhMOzf0PHFsXyXGVTfTzr7NxB5wOeFrnooE0 fyeL3crlOc3H6ULV7rNqZH6rBZ27KQuT35NGotXDUTHPfHXjoV8ZLAlYH kUuTfD/8jkdvL+uDF8wbRwCpFftqOEqQzHufy9r0sJRtAFcb6XtKmyLeb g==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="232170783" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:20:59 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:20:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:56 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Date: Mon, 26 Jun 2023 12:19:43 +0100 Message-ID: <20230626-possible-poet-ae4afce0a525@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1151; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=7P2ZuLVh/mHZ6Q4BNnYCrGzK8DdnxNYlyk5flnLKkc8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/xE6xX23F074e9rMbcVQp8tu+YXyBy/sSt3+qSI3okt tbITOkpZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjAR//MM/yNNa9dwJvmkacy1rj2x/n MTq7zVA7vpn1OurJVwNg59fIORYWPFuu+zBZZ/uTYx+h7/2avbjWesEnSN/tA/+ZyoyxqzcywA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764524191916714?= X-GMAIL-MSGID: =?utf-8?q?1769764524191916714?= To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 36f46dfd2b87..a35bee219dd7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a') From patchwork Mon Jun 26 11:19:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112878 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7411845vqr; Mon, 26 Jun 2023 04:34:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5NFYgoL+mEyjokcpSmRPshgIMVLA8YFWynpklS73D+DGlRK9rokVZ+pTn5tMERL9UUeScQ X-Received: by 2002:a05:6a00:3994:b0:66c:6678:3776 with SMTP id fi20-20020a056a00399400b0066c66783776mr8412529pfb.7.1687779267475; Mon, 26 Jun 2023 04:34:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779267; cv=none; d=google.com; s=arc-20160816; b=YFm0ATx+93rfmlAUeu6nsQeMUI+exqvdPEIigkDZzMA/iyQoRPb5zLKhSobc94i7ul VgyU1a9nTKb/rTKPD1T2SqjRGpVt8PPm5P3gvaRYP06y9YCMZCpjxuleaBcepHVk0dCV Pv+OADQFKV14jJLUPhRa3EnuRPfgdHLs/xBnnMWy5ci7Ro0KWd0HG9KyO3GIPXd/DCax 7RlK6m8A1QhMCaT5dFBHXUOEDD7bxqBlbIbIm3tpTXerWEERhVLiUy8PBwdcUq1odsgM NvJ42ggnnl4pCn0SISsZnR1Nz6MJ4si/pMntB5vpI/upXRxvsXz44rLZLjgZhnCsBKqw MxCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=l8jynxRIGmmL5m8JZLeMHRF9k5b1YE4X7MUtSESR4Bo=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=aLWmuQBRVyiOiAf2FG5Q/V4O2gZvPCCzI23v29b40Idg2/+XD8/PLzN9WBOem/8i61 BsgPzlNxl3vu1R+ddyEf1OzGM704dfkHDID/8cvZDgLWQ0boWxXx8/kM3pzHJn/KpAcr 2ozW4aDGWD5lzUyUOlgxA18hReQiWUhnOYvlE2fvaCUCYkfPvbxNcJii4LVfw+doTHqY AlXOBoLcf3q6jtzS5YctwhM7FS42ovAsrY0EUFoCO9KEW/pMTp5eZOi4+EUcueBq6/e4 dIA6+9jIqevAxqduqfCe281o4bo7fb2dtnvZjUm4Ipj/IMvQprDtFGUmvDNXhFCSQ5J4 ACKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BVLMMBRX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f30-20020a631f1e000000b005348202cac1si5042295pgf.5.2023.06.26.04.34.14; Mon, 26 Jun 2023 04:34:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BVLMMBRX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231152AbjFZLVX (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230363AbjFZLVM (ORCPT ); Mon, 26 Jun 2023 07:21:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49CC110E3; Mon, 26 Jun 2023 04:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778462; x=1719314462; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yZJX1ZKwzL2BmVRGCEvc/ExPgwhg69uUVieSVE8JLtg=; b=BVLMMBRXxkhpUdBLjjAjZAyIuyLj2YUUrL/eseznkqaxx8fHdG+EgU9s aNIXP1M9JMdHou+v52/bdBhybHA80vlAqW3Kuzkk3CZPu+JU6p3cnrnTY 4lmXDfb7paF/bPUYEFUMvyj/S7mxqv8oFzS03AVMRgu5Nf6zPCpSDuMKd e/Q+zI+7mZHdEzwP1vXv9FA9rPIZHC5slZ4yuiCjF+9pOU8rxUpJuf7e7 m5tUUjMFGnxF735s+PqRQyKS+CiupoW6zTjjnELYKVtfT4VYvMzALUGRy yXP7yV2vy9Fdlba0+PSNsgNqhwHclikeP0ZEzpIvI09Qfddqyn6AayQOJ w==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="232170788" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:21:01 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:21:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:20:59 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Date: Mon, 26 Jun 2023 12:19:44 +0100 Message-ID: <20230626-sensuous-clothing-124f7ae0aedf@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6462; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=yZJX1ZKwzL2BmVRGCEvc/ExPgwhg69uUVieSVE8JLtg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/yW8r6JkLbgmygTkrXKqNBg4cZLb/YzO3w5yMRg/Igz qeRrRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbisIzhf3Je0+MTcaUqHzNu5zhlSZ jVzc5cXBrNW1+9mIGpcmrKL4b/MdIxC7xD/zF31W88aXNGui49Rneh2w0Bhg8ZNhZ/i/6yAAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764833236292226?= X-GMAIL-MSGID: =?utf-8?q?1769764833236292226?= So that riscv_fill_hwcap() can use riscv_isa_ext to probe for single letter extensions, add them to it. riscv_isa_ext_data grows a new member, signifying whether an extension is multi-letter & thus requiring special handling. As a result, what gets spat out in /proc/cpuinfo will become borked, as single letter extensions will be printed as part of the base extensions and while printing from riscv_isa_arr. Take the opportunity to unify the printing of the isa string, using the new member of riscv_isa_ext_data in the process. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 36 ++++++---------------- arch/riscv/kernel/cpufeature.c | 56 +++++++++++++++++++++------------- 3 files changed, 46 insertions(+), 47 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a35bee219dd7..6ad896dc4342 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -77,6 +77,7 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { const unsigned int id; const char *name; + const bool multi_letter; }; extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index beb8b16bbf87..046d9d3dac16 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -160,41 +160,25 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS -static void print_isa_ext(struct seq_file *f) -{ - for (int i = 0; i < riscv_isa_ext_count; i++) { - const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->id)) - continue; - - seq_printf(f, "_%s", edata->name); - } -} - -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - static void print_isa(struct seq_file *f) { - int i; - seq_puts(f, "isa\t\t: "); + if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); else seq_write(f, "rv64", 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + continue; + + if (riscv_isa_ext[i].multi_letter) + seq_puts(f, "_"); + + seq_printf(f, "%s", riscv_isa_ext[i].name); } - print_isa_ext(f); + seq_puts(f, "\n"); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b5e23506c4f0..5405d8a58537 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,9 +99,10 @@ static bool riscv_isa_extension_check(int id) return true; } -#define __RISCV_ISA_EXT_DATA(_name, _id) { \ - .name = #_name, \ - .id = _id, \ +#define __RISCV_ISA_EXT_DATA(_name, _id, _multi) { \ + .name = #_name, \ + .id = _id, \ + .multi_letter = _multi, \ } /* @@ -144,24 +145,37 @@ static bool riscv_isa_extension_check(int id) * New entries to this struct should follow the ordering rules described above. */ const struct riscv_isa_ext_data riscv_isa_ext[] = { - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), - __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), - __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i, false), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m, false), + __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a, false), + __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f, false), + __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d, false), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q, false), + __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c, false), + __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b, false), + __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k, false), + __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j, false), + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p, false), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v, false), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h, false), + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM, true), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ, true), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR, true), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR, true), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI, true), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE, true), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM, true), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA, true), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB, true), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS, true), + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA, true), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA, true), + __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF, true), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC, true), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL, true), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT, true), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT, true), + __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX, true), }; const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); From patchwork Mon Jun 26 11:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112876 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7409954vqr; Mon, 26 Jun 2023 04:31:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4i3vF6ixwlpOH4hqb+JDfhTVm27+YraS+JJoPfC9SFRFc48N45en6Fm4IsVQGZd48aMf2m X-Received: by 2002:a05:6358:514e:b0:12f:2573:45b4 with SMTP id 14-20020a056358514e00b0012f257345b4mr18377809rwj.26.1687779084956; Mon, 26 Jun 2023 04:31:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779084; cv=none; d=google.com; s=arc-20160816; b=REou2c/cBjTWeZa6lJ9ijlkzmn/GzutCIz2/6TYISP+GH9ZA/T8rpT2n7D2sORdCUm Tga0CZxgOmyPLMBlai2lK6ABYEkhkvga0KXlqkjLsyK7TY42BhSbhG5rBAuj82oFfGT/ cTCOiO3FzWzsrmri0X9ZGGMeZ1LR7HnIFGTLN6TEdjLWOn4ri8dcYG9Bg7CoNFJpQlm9 +AoXh1/jxVyDiU0zeqTg+MqeX9dJymMO4umG5GxhV4SH/epaCT7ZjivJ5yzdlOxBvV3k YHeG2RCTjSIEQXXBBo1BQZ9arXAOv7E1YdlsVq3iX4LKHMZbLKkIo3cP/dyUsriefHYX ZS7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nqD9V+5Qhf3bazWvRliyShc+Rt1eWZ2YSTjkr8w3i3c=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=x5Y4CgpDOJxYj5OaZKC2aTbOCGsPfgJUmGO6nujwg8Zsinu5gcvjsYtIBUnH6UuYIA 1oM26tf7WIrGLbDzizdF5xcabT87lcgZtAy1piEhDR4acA9HBTHi7NL6BV44NHoQ2Hp3 aHTTjLa2fPHqhv0Vq9qztqIEXz6oZ5+xXCb26b7XCbQFkgsL1a2mNKn9OvXVU3tZ05kI 42vYXvrMJ0VFvLpnmEJ3OJh2AHI/rJwohvo/Si8pcS38/1CPxfJJG2gKJF5UdI303Jpy 9Bgz51EcsAJF8Ikd3n3UUeZGr82P2p9f1vNL/pe/g1WjUhCta9kW9UqLvlVoHmdZ1uzJ UScg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=jEEGocZm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k5-20020a63f005000000b0054fdfd26dfesi5066338pgh.308.2023.06.26.04.31.11; Mon, 26 Jun 2023 04:31:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=jEEGocZm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230513AbjFZLV2 (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230514AbjFZLVO (ORCPT ); Mon, 26 Jun 2023 07:21:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED5AB1709; Mon, 26 Jun 2023 04:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778464; x=1719314464; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B8TDhvFs2NMM5D/MoWXi2C5U9+P2WwesVheXFF9nLYI=; b=jEEGocZm16PzeHSAp9ETQzLtIp+nd54XImyZvReTn9FSPWp0lsYVfJjM IGdF0RHcT6qfmUxa6ALHW1i9T/zsx/DkPP7e4dBoUJH4uAHUHT2p0v81Q YZM8ui4P+xasvBhWhxBXvWFKBdxMB1kltmRcRsJ4E4S7FPJ8Jan/ihCno d4INYS/D41mhyAtdKTeujRpYNbZoiy6FGsbMtTCeLv9E2gu0eG008BmJy wLELt6Ce5ztG4LVj95lRKu8ZhAkxSn87Uyja5PLjWP5nW3r/OfJLK9+ue EYiEuhngFfQ8XnTVus5gkWWpUZQ7g6Pq9hH8GJzKRfNDFM16zAR7yJN41 A==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="219824762" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:21:04 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:21:03 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:21:01 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Date: Mon, 26 Jun 2023 12:19:45 +0100 Message-ID: <20230626-prevalent-heaviness-e35188de1225@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12001; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=B8TDhvFs2NMM5D/MoWXi2C5U9+P2WwesVheXFF9nLYI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/wvBjVMZ5oWL6hspLb1cn2uUVFZucqabQd23yo+VOpy Tf1QRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYyo4WRYdrCHMNsc4HPsxhTzxXriZ 7xkbb9ID71dWTXxEavzk0nzjIyPHmRuuxnhZXJBHH16Hm79M/p5O4UD767+81BR4e6pVo6HAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764642063911427?= X-GMAIL-MSGID: =?utf-8?q?1769764642063911427?= Before adding more complexity to it, split riscv_fill_hwcap() into 3 distinct sections: - riscv_fill_hwcap() still is the top level function, into which the additional complexity will be added. - riscv_fill_hwcap_from_isa_string() handles getting the information from the riscv,isa/ACPI equivalent across harts & the various quirks there - riscv_parse_isa_string() does what it says on the tin. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 350 +++++++++++++++++---------------- 1 file changed, 182 insertions(+), 168 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5405d8a58537..366477ba1eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -180,29 +180,172 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); -void __init riscv_fill_hwcap(void) +static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct riscv_isainfo *isainfo, + unsigned long *isa2hwcap, const char *isa) +{ + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ + isa += 4; + + while (*isa) { + const char *ext = isa++; + const char *ext_end = isa; + bool ext_long = false, ext_err = false; + + switch (*ext) { + case 's': + /* + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] != '_' && ext[1] == 'u') { + ++isa; + ext_err = true; + break; + } + fallthrough; + case 'S': + case 'x': + case 'X': + case 'z': + case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ + ext_long = true; + for (; *isa && *isa != '_'; ++isa) + if (unlikely(!isalnum(*isa))) + ext_err = true; + + ext_end = isa; + if (unlikely(ext_err)) + break; + + if (!isdigit(ext_end[-1])) + break; + + while (isdigit(*--ext_end)) + ; + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { + ++ext_end; + break; + } + + while (isdigit(*--ext_end)) + ; + + ++ext_end; + break; + default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ + if (unlikely(!isalpha(*ext))) { + ext_err = true; + break; + } + + if (!isdigit(*isa)) + break; + + while (isdigit(*++isa)) + ; + + if (tolower(*isa) != 'p') + break; + + if (!isdigit(*++isa)) { + --isa; + break; + } + + while (isdigit(*++isa)) + ; + + break; + } + + /* + * The parser expects that at the start of an iteration isa points to the + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". + */ + if (*isa == '_') + ++isa; + +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext == sizeof(name) - 1) && \ + !strncasecmp(ext, name, sizeof(name) - 1) && \ + riscv_isa_extension_check(bit)) \ + set_bit(bit, isainfo->isa); \ + } while (false) \ + + if (unlikely(ext_err)) + continue; + if (!ext_long) { + int nr = tolower(*ext) - 'a'; + + if (riscv_isa_extension_check(nr)) { + *this_hwcap |= isa2hwcap[nr]; + set_bit(nr, isainfo->isa); + } + } else { + for (int i = 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); + } +#undef SET_ISA_EXT_MAP + } +} + +static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) { struct device_node *node; const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; - unsigned long isa2hwcap[26] = {0}; + int rc; struct acpi_table_header *rhct; acpi_status status; unsigned int cpu; - isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; - isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - - elf_hwcap = 0; - - bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - if (!acpi_disabled) { status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); if (ACPI_FAILURE(status)) @@ -234,158 +377,7 @@ void __init riscv_fill_hwcap(void) } } - /* - * For all possible cpus, we have already validated in - * the boot process that they at least contain "rv" and - * whichever of "32"/"64" this kernel supports, and so this - * section can be skipped. - */ - isa += 4; - - while (*isa) { - const char *ext = isa++; - const char *ext_end = isa; - bool ext_long = false, ext_err = false; - - switch (*ext) { - case 's': - /* - * Workaround for invalid single-letter 's' & 'u'(QEMU). - * No need to set the bit in riscv_isa as 's' & 'u' are - * not valid ISA extensions. It works until multi-letter - * extension starting with "Su" appears. - */ - if (ext[-1] != '_' && ext[1] == 'u') { - ++isa; - ext_err = true; - break; - } - fallthrough; - case 'S': - case 'x': - case 'X': - case 'z': - case 'Z': - /* - * Before attempting to parse the extension itself, we find its end. - * As multi-letter extensions must be split from other multi-letter - * extensions with an "_", the end of a multi-letter extension will - * either be the null character or the "_" at the start of the next - * multi-letter extension. - * - * Next, as the extensions version is currently ignored, we - * eliminate that portion. This is done by parsing backwards from - * the end of the extension, removing any numbers. This may be a - * major or minor number however, so the process is repeated if a - * minor number was found. - * - * ext_end is intended to represent the first character *after* the - * name portion of an extension, but will be decremented to the last - * character itself while eliminating the extensions version number. - * A simple re-increment solves this problem. - */ - ext_long = true; - for (; *isa && *isa != '_'; ++isa) - if (unlikely(!isalnum(*isa))) - ext_err = true; - - ext_end = isa; - if (unlikely(ext_err)) - break; - - if (!isdigit(ext_end[-1])) - break; - - while (isdigit(*--ext_end)) - ; - - if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { - ++ext_end; - break; - } - - while (isdigit(*--ext_end)) - ; - - ++ext_end; - break; - default: - /* - * Things are a little easier for single-letter extensions, as they - * are parsed forwards. - * - * After checking that our starting position is valid, we need to - * ensure that, when isa was incremented at the start of the loop, - * that it arrived at the start of the next extension. - * - * If we are already on a non-digit, there is nothing to do. Either - * we have a multi-letter extension's _, or the start of an - * extension. - * - * Otherwise we have found the current extension's major version - * number. Parse past it, and a subsequent p/minor version number - * if present. The `p` extension must not appear immediately after - * a number, so there is no fear of missing it. - * - */ - if (unlikely(!isalpha(*ext))) { - ext_err = true; - break; - } - - if (!isdigit(*isa)) - break; - - while (isdigit(*++isa)) - ; - - if (tolower(*isa) != 'p') - break; - - if (!isdigit(*++isa)) { - --isa; - break; - } - - while (isdigit(*++isa)) - ; - - break; - } - - /* - * The parser expects that at the start of an iteration isa points to the - * first character of the next extension. As we stop parsing an extension - * on meeting a non-alphanumeric character, an extra increment is needed - * where the succeeding extension is a multi-letter prefixed with an "_". - */ - if (*isa == '_') - ++isa; - -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext == sizeof(name) - 1) && \ - !strncasecmp(ext, name, sizeof(name) - 1) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - - if (unlikely(ext_err)) - continue; - if (!ext_long) { - int nr = tolower(*ext) - 'a'; - - if (riscv_isa_extension_check(nr)) { - this_hwcap |= isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); - } -#undef SET_ISA_EXT_MAP - } + riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa); /* * Linux requires the following extensions, so we may as well @@ -422,6 +414,28 @@ void __init riscv_fill_hwcap(void) if (!acpi_disabled && rhct) acpi_put_table((struct acpi_table_header *)rhct); +} + +void __init riscv_fill_hwcap(void) +{ + struct device_node *node; + const char *isa; + char print_str[NUM_ALPHA_EXTS + 1]; + int i, j, rc; + unsigned long isa2hwcap[26] = {0}; + struct acpi_table_header *rhct; + acpi_status status; + unsigned int cpu; + + isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; + isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; + isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; + isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; + isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; + isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; + + riscv_fill_hwcap_from_isa_string(isa2hwcap); /* We don't support systems with F but without D, so mask those out * here. */ From patchwork Mon Jun 26 11:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112882 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7413793vqr; Mon, 26 Jun 2023 04:37:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5tHVev8WCr4ja0ie5Gi0bxVmaHj9E6/+EWOuCHZwzLmX9f8e51c2OaW37QG6mI8HGbK8m7 X-Received: by 2002:a17:906:cc56:b0:991:e24f:b288 with SMTP id mm22-20020a170906cc5600b00991e24fb288mr896947ejb.26.1687779455385; Mon, 26 Jun 2023 04:37:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779455; cv=none; d=google.com; s=arc-20160816; b=gfaL3BSl1Y3qoXfsLsnabBk193frVjvwgLUKQom3nzWfzAy0oZgD/grh1liT9EgVkb 8j/aR/zlh8+RZW1ksIKjzs5O8HLbcF3ZZDZ35CCKBLhJJN38XZFqiXpkjcCOX3qTECR1 HPXFY+NSFW3tzCIwC8Hy8XoRgkQ8BHAQN9pzWHw+gYz94EGBwii0FfBtrUht9ylrish1 RMLOQcj9OBpobMEQCbWGl1756lhHpHGO3rhXs8acaIiRdCf24C2/dN/mTIFFOITQAXRT bi3dQrFKsvdFs6P/caQtUqheuVGvNXN3cNf8bnkoAyWJQxWw39Ki539f2DZ75wzqmdg8 SIHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R+XLmAv0IMdL1XndgOz+rJKNq/66YIU8I3/IIfTS48U=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=BSIyeRcdpojSO9Fdp8gbeJiaA3xngBUchWtwZWfQlX+9XHdFLdPCK7gzDGd7diK9bG Xt0zRQcFaAW7XSoe1Lf+/2B8+IKCeSBwIfVBxZmWQrCV/CsCgbZAV4Fftivvr9Ip7wXh 10/rdUY7cSa2a/hOz27e+9C4PaqgPb0L4kbqMGQ69M+YxztAfI66Kdg5tYaeVX4H88ZB bMvMcyd+A3177Or9RFdapR//HGkqv6iI55RHPBomybjgOcZMNqX1t7OXaGMUBBQtGc4R CnUJtSgj92/vde0TacwDGvBYPOiLdH58Bt35P+BjFPFtYh7sjaHY0iKLZy8tQpoV5+R5 rqTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=YxHCoiA2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q16-20020a170906361000b009889b296070si2641525ejb.261.2023.06.26.04.37.10; Mon, 26 Jun 2023 04:37:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=YxHCoiA2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbjFZLVl (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbjFZLVZ (ORCPT ); Mon, 26 Jun 2023 07:21:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95CF81BE2; Mon, 26 Jun 2023 04:21:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778470; x=1719314470; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ELcThGgPV8TgNeRjLRDN3LuYnlZfadeE3nwnvrWBouo=; b=YxHCoiA2yFc8nqwVIre0LgzqHf+jRKJ7kFYVuPTbkFv1meHfjtWTTy0e +cZMYLEPEcmQm/UGxFNDSfiCJQLQsUwkG7GHKQEXiFpPEb52a2kuhKnxN 3Yh46OuIfw1nvpllQd6RYrPLBsrdUC8o4T32S/U4oLzFcU36jLM1P3uAY QS2CYMAwMfW1il1RrVy24OA+2JmDm4S63b9RoZTlBltBvdT/ezIuHXwre 2MCDFSXyyT/koyw0hyx/hPq9gmLhSeBz8EoRYjv8rXz5a3TdiC6a4CMUZ xe1r5yn35YvZMIJJcL5Vpac1Wl1gPVR1AY/w2n1YtKw1zyWt2OhFaCIRo w==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="158621103" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:21:09 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:21:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:21:04 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 8/9] RISC-V: enable extension detection from new properties Date: Mon, 26 Jun 2023 12:19:46 +0100 Message-ID: <20230626-unfasten-guidance-eac4d71d8876@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4380; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ELcThGgPV8TgNeRjLRDN3LuYnlZfadeE3nwnvrWBouo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzS/x7Us3kvE7JNEeYzVmnHRjy4PLc9x9agm7YP+2f9eoD Q51cRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYy7QPD/1SvndnHp8x8cWg6C1PbiW Nfsy69/CFw3uOOMVNQ/3Pxoh+MDDPXWu7s1JL1fZnX6q348WPrpk3HSoyXpag9TQi1+Vv9lREA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769765029945145300?= X-GMAIL-MSGID: =?utf-8?q?1769765029945145300?= Add support for parsing the new riscv,isa-extensions property in riscv_fill_hwcap(), by means of a new "property" member of the riscv_isa_ext_data struct. For now, this shadows the name of the extension, however this may not be the case for all extensions. For the sake of backwards compatibility, fall back to the old scheme if the new properties are not detected. For now, just inform, rather than warn, when that happens. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- Naming things is hard, didn't know what to call the new function... --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 80 ++++++++++++++++++++++++++++++---- 2 files changed, 72 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6ad896dc4342..e7f235868aa2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -77,6 +77,7 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { const unsigned int id; const char *name; + const char *property; const bool multi_letter; }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 366477ba1eea..72eb757ad871 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ static bool riscv_isa_extension_check(int id) #define __RISCV_ISA_EXT_DATA(_name, _id, _multi) { \ .name = #_name, \ + .property = #_name, \ .id = _id, \ .multi_letter = _multi, \ } @@ -416,16 +417,66 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) acpi_put_table((struct acpi_table_header *)rhct); } +static int __init riscv_fill_hwcap_new(unsigned long *isa2hwcap) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) { + unsigned long this_hwcap = 0; + struct device_node *cpu_node; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + if (!of_property_present(cpu_node, "riscv,isa-extensions")) + continue; + + for (int i = 0; i < riscv_isa_ext_count; i++) { + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + riscv_isa_ext[i].name) < 0) + continue; + + if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) + continue; + + if (!riscv_isa_ext[i].multi_letter) + this_hwcap |= isa2hwcap[riscv_isa_ext[i].id]; + + set_bit(riscv_isa_ext[i].id, this_isa); + } + + of_node_put(cpu_node); + + /* + * All "okay" harts should have same isa. Set HWCAP based on + * common capabilities of every "okay" hart, in case they don't. + */ + if (elf_hwcap) + elf_hwcap &= this_hwcap; + else + elf_hwcap = this_hwcap; + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + else + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + return -ENOENT; + + return 0; +} + void __init riscv_fill_hwcap(void) { - struct device_node *node; - const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; unsigned long isa2hwcap[26] = {0}; - struct acpi_table_header *rhct; - acpi_status status; - unsigned int cpu; + int i, j; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -435,10 +486,21 @@ void __init riscv_fill_hwcap(void) isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; - riscv_fill_hwcap_from_isa_string(isa2hwcap); + if (!acpi_disabled) { + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } else { + int ret = riscv_fill_hwcap_new(isa2hwcap); - /* We don't support systems with F but without D, so mask those out - * here. */ + if (ret) { + pr_info("Falling back to deprecated \"riscv,isa\"\n"); + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } + } + + /* + * We don't support systems with F but without D, so mask those out + * here. + */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { pr_info("This kernel does not support systems with F but not D\n"); elf_hwcap &= ~COMPAT_HWCAP_ISA_F; From patchwork Mon Jun 26 11:19:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 112877 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp7411534vqr; Mon, 26 Jun 2023 04:34:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ68RzscmKyDh0m36Et7esAnEiaRo3e7LNLEHMvd5snblezkle9NJOgb4oheF+4fYr/rivFR X-Received: by 2002:aa7:c94e:0:b0:51b:e9e8:164b with SMTP id h14-20020aa7c94e000000b0051be9e8164bmr7089372edt.35.1687779241142; Mon, 26 Jun 2023 04:34:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687779241; cv=none; d=google.com; s=arc-20160816; b=cncpu+4FShny60tl0zJulmL6V2JL9XpT0yFPDAqtezBOfM68wxwMdxfLomhafm5TOK 55cJsQAwN2EZirmbNoMSIcKdvMHReTMmL4uL/Qb65owhANFrSNo1gT23buHHKRZgNiOQ dsuYUO29xHh6lr8wvbmBlx97mijvLNm7+dOZTzXIqxpOhcugnJRX5qB1RWkVNAr9KRdS xDMdlO9a0zyyp71aZIn358yKIa7ZZOMXt5jEG1NtLsjqrMARvkAK8/Yx3iRF506k+QDc oWCjNPQOtQ1a+X3LJJu/gTWmCnMQ9dfKwCHBURf0ClBcpTrsfamUU9qkO0B6pyaa+QwE Ep0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kqx76pps6NrBCO7058Ll4Qp9ipkyRYk4Gl9gWCsTk6U=; fh=id5NoWTfrmVnmm2w/Ed5X4erHGUuViLdGWw+WL1NNbc=; b=uPritK+VO5qf8nntrICxOP/wg6TDSv+JcgdBHGkKzR6yqJ5EbnKoXEhzhMbRpVpWWZ OxebO1pO/L8EjlOvzD4PvTZ5WigjceJWqXpoAq7S718xIKXA/ZKaLE3CsbJxYxlamVBI /5iMXokb0dTsy5QJogqeBWS+NuAFmel19hFg9jpvY5h/uCL/vCHdBmbfcDMapGx8LXm1 voeLzZYgGlgHnpkYEIdgksJkAuXe0arPxxwrr6RZjoFaqxkLEw4rUzuhtQzMUjJkXf1c iLEKQ9hzIs2PdRCPlICeerUEKSz4/bhyvcL2ZD3QbFiNxEHT2SVBq3qlLsc6zD8m0ENx qGsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2LhukpHJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l10-20020aa7d94a000000b0051d9a97ce11si907523eds.57.2023.06.26.04.33.37; Mon, 26 Jun 2023 04:34:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=2LhukpHJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbjFZLVz (ORCPT + 99 others); Mon, 26 Jun 2023 07:21:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbjFZLVh (ORCPT ); Mon, 26 Jun 2023 07:21:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BF5610D2; Mon, 26 Jun 2023 04:21:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687778475; x=1719314475; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eZGPwaE1m+Pw9q6+drdEFoQWfh6B8MVtcv7cz4C7AWM=; b=2LhukpHJasRWaIHS/suE1gWjUor621djuHskSIQrQl6icJ7QTtZqhSsU zvZlybZ5TS3lGiapEKGJbPCjD1JUKV/FH6WVn0zwDjNZZ2ZpB+zoL9kth nRhJEBTqi18ZsjrIsYR99+C4w2hzUvAyC+m6c9m/Vo0Fde2bP1gSGD1Hu XbmbVEm0D9UfAfnAKhCEevMpkoIC5rHWFX3EmVg4Ivew2WXMB0mnudrIf gYyca7hQ70YL4374Y8nY40a0M4ppJ5FO8mQVec7b3US0c0YLwaLeDzUrh DvBpyxJuIPXolP+2RJOfkKTs7mKpZBPdEpigiJfXyB6uCAAO66KEug3St g==; X-IronPort-AV: E=Sophos;i="6.01,159,1684825200"; d="scan'208";a="158621162" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jun 2023 04:21:14 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 26 Jun 2023 04:21:09 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 26 Jun 2023 04:21:06 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Date: Mon, 26 Jun 2023 12:19:47 +0100 Message-ID: <20230626-ardently-caress-7c5886566ea6@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy> References: <20230626-provable-angrily-81760e8c3cc6@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1532; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=eZGPwaE1m+Pw9q6+drdEFoQWfh6B8MVtcv7cz4C7AWM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkzSwIaJ2btMmdgqZot8WPa/G3PGEPs4r1udXSujdFqnn9/ 14GTHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIa35GhvvsnlwdH+17zPm/9ExMZm n5+La70FFEbOkUKZ1ir5dmlxj+1076fM9XhG3d0c9OmjclNshf3Wa71PXiWp93E2qmir0rZQAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769764805589906343?= X-GMAIL-MSGID: =?utf-8?q?1769764805589906343?= To fully deprecate the kernel's use of "riscv,isa", of_early_processor_hartid() needs to first try using the new properties, before falling back to "riscv,isa". Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 046d9d3dac16..332574f27c95 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -61,8 +61,29 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) + return -ENODEV; + + if (!of_property_present(node, "riscv,isa-extensions")) + return -ENODEV; + + if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) + return -ENODEV; + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; }