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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ox27-20020a170907101b00b00982b276713csi2230077ejb.880.2023.06.25.20.39.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Jun 2023 20:39:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 17E82385800A for ; Mon, 26 Jun 2023 03:39:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id D0CC33858D20 for ; Mon, 26 Jun 2023 03:38:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D0CC33858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1687750714t8f9hjcm Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 26 Jun 2023 11:38:33 +0800 (CST) X-QQ-SSF: 01400000000000G0S000000A0000000 X-QQ-FEAT: jXjag1m6xl4aWdHtoTG/TX7U55ymC/paMJaRpyWmUPlnNx8PSd4bztMUf3FIq Yj26VXokNppApJDDFK16lIpaHHSZWquVZhiaA1cpA8LW5lyTcWqHwoXG9foPpknquN7CJHI 7wtXFqAm908e//z6p+qcngOuQtYGWeAV3C3pSNsJf/6/UtYMQ9LMX3smfDQ1m9vWNNRGp4W sR/lf3N8v/3YhPc1SaT+tFWD4EG9V5X/0KRv4audXNy8kGUZ8bfVChOl/n4rowrgw5DIUwj 1l2AFSlcwzckn6dXJ3tIzqyT/z44+O9Nopuob8HYjllzXwDLVZ2y2jR/1yKEg+gAtWJ6dPW 9vbXCad68cmg2adaX7KSDLGcVzavQOUJpkFGcYGRwlgo4oF1itPpmosZTfPirTe910fN/1+ QAl/9WzpMbx8KUt5u7jPwA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3786566204323828344 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, rguenther@suse.de, Juzhe-Zhong Subject: [PATCH] RISC-V: Remove redundant vcond patterns Date: Mon, 26 Jun 2023 11:38:30 +0800 Message-Id: <20230626033830.6544-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769734944094561604?= X-GMAIL-MSGID: =?utf-8?q?1769734944094561604?= Previously, Richi has suggested that vcond patterns are only needed when target support comparison + select consuming 1 instruction. Now, I do the experiments on removing those "vcond" patterns, it works perfectly. All testcases PASS. Really appreicate Richi helps us recognize such issue. Now remove all "vcond" patterns as Richi suggested. gcc/ChangeLog: * config/riscv/autovec.md (vcond): Remove redundant vcond patterns. (vcondu): Ditto. * config/riscv/riscv-protos.h (expand_vcond): Ditto. * config/riscv/riscv-v.cc (expand_vcond): Ditto. --- gcc/config/riscv/autovec.md | 38 --------------------------------- gcc/config/riscv/riscv-protos.h | 1 - gcc/config/riscv/riscv-v.cc | 22 ------------------- 3 files changed, 61 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 5de43a8d647..19100b5b2cb 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -311,44 +311,6 @@ } ) -;; ------------------------------------------------------------------------- -;; ---- [INT,FP] Compare and select -;; ------------------------------------------------------------------------- -;; The patterns in this section are synthetic. -;; ------------------------------------------------------------------------- - -(define_expand "vcond" - [(set (match_operand:V 0 "register_operand") - (if_then_else:V - (match_operator 3 "comparison_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")]) - (match_operand:V 1 "register_operand") - (match_operand:V 2 "register_operand")))] - "TARGET_VECTOR && known_eq (GET_MODE_NUNITS (mode), - GET_MODE_NUNITS (mode))" - { - riscv_vector::expand_vcond (operands); - DONE; - } -) - -(define_expand "vcondu" - [(set (match_operand:V 0 "register_operand") - (if_then_else:V - (match_operator 3 "comparison_operator" - [(match_operand:VI 4 "register_operand") - (match_operand:VI 5 "register_operand")]) - (match_operand:V 1 "register_operand") - (match_operand:V 2 "register_operand")))] - "TARGET_VECTOR && known_eq (GET_MODE_NUNITS (mode), - GET_MODE_NUNITS (mode))" - { - riscv_vector::expand_vcond (operands); - DONE; - } -) - ;; ------------------------------------------------------------------------- ;; ---- [INT] Sign and zero extension ;; ------------------------------------------------------------------------- diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f686edab3d1..7265b1c8401 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -252,7 +252,6 @@ machine_mode preferred_simd_mode (scalar_mode); opt_machine_mode get_mask_mode (machine_mode); void expand_vec_series (rtx, rtx, rtx); void expand_vec_init (rtx, rtx); -void expand_vcond (rtx *); void expand_vec_perm (rtx, rtx, rtx, rtx); void expand_select_vl (rtx *); void expand_load_store (rtx *, bool); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5518394be1e..f6dd0d8e2a4 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2421,28 +2421,6 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, return false; } -/* Expand an RVV vcond pattern with operands OPS. DATA_MODE is the mode - of the data being merged and CMP_MODE is the mode of the values being - compared. */ - -void -expand_vcond (rtx *ops) -{ - machine_mode cmp_mode = GET_MODE (ops[4]); - machine_mode data_mode = GET_MODE (ops[1]); - machine_mode mask_mode = get_mask_mode (cmp_mode).require (); - rtx mask = gen_reg_rtx (mask_mode); - if (FLOAT_MODE_P (cmp_mode)) - { - if (expand_vec_cmp_float (mask, GET_CODE (ops[3]), ops[4], ops[5], true)) - std::swap (ops[1], ops[2]); - } - else - expand_vec_cmp (mask, GET_CODE (ops[3]), ops[4], ops[5]); - emit_insn ( - gen_vcond_mask (data_mode, data_mode, ops[0], ops[1], ops[2], mask)); -} - /* Implement vec_perm. */ void