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[8.43.85.97]) by mx.google.com with ESMTPS id sb18-20020a1709076d9200b0072b9ca954b2si19190724ejc.1006.2022.07.18.23.08.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jul 2022 23:08:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=cSmyyICr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 61B973857410 for ; Tue, 19 Jul 2022 06:08:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 61B973857410 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1658210913; bh=5tS3u76xxafRjV8k7jhpjP4MbCp66NApyDkF7WhOrT4=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=cSmyyICrnp+mUsMVa2Z+pPy+GuDRji2ZeYaj5OgjdAoD0jiTHqbotKfRvZHb2iyLW kfedm3DLWiqTlvUewDJY1HVHIOn4UHuaVF8WPKHTnFEW8GzXLJVRPtL2lsvfkAYoeI dMI2gkof4JF15MjCaXoyi0+NAHpLqQNVRVjgg2zA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 77F433858428 for ; Tue, 19 Jul 2022 06:07:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 77F433858428 X-IronPort-AV: E=McAfee;i="6400,9594,10412"; a="286418235" X-IronPort-AV: E=Sophos;i="5.92,283,1650956400"; d="scan'208";a="286418235" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jul 2022 23:07:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,283,1650956400"; d="scan'208";a="665298245" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 18 Jul 2022 23:07:38 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9D3F510056A5; Tue, 19 Jul 2022 14:07:37 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH V2] Extend 16/32-bit vector bit_op patterns with (m, 0, i) alternative. Date: Tue, 19 Jul 2022 14:07:36 +0800 Message-Id: <20220719060736.18399-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: References: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1738760168063226588?= X-GMAIL-MSGID: =?utf-8?q?1738760168063226588?= And split it after reload. > You will need ix86_binary_operator_ok insn constraint here with > corresponding expander using ix86_fixup_binary_operands_no_copy to > prepare insn operands. Split define_expand with just register_operand, and allow memory/immediate in define_insn, assume combine/forwprop will do optimization. > Please use if (!register_operand (operands[2], mode)) instead. Changed. Update patch. gcc/ChangeLog: PR target/106038 * config/i386/mmx.md (3): New define_expand, it's original "3". (*3): New define_insn, it's original "3" be extended to handle memory and immediate operand with ix86_binary_operator_ok. Also adjust define_split after it. (mmxinsnmode): New mode attribute. (*mov_imm): Refactor with mmxinsnmode. * config/i386/predicates.md (register_or_x86_64_const_vector_operand): New predicate. gcc/testsuite/ChangeLog: * gcc.target/i386/pr106038-1.c: New test. --- gcc/config/i386/mmx.md | 71 ++++++++++++---------- gcc/config/i386/predicates.md | 4 ++ gcc/testsuite/gcc.target/i386/pr106038-1.c | 27 ++++++++ 3 files changed, 71 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-1.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 3294c1e6274..316b83dd3ac 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -86,6 +86,14 @@ (define_mode_attr mmxvecsize [(V8QI "b") (V4QI "b") (V2QI "b") (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")]) +;; Mapping to same size integral mode. +(define_mode_attr mmxinsnmode + [(V8QI "DI") (V4QI "SI") (V2QI "HI") + (V4HI "DI") (V2HI "SI") + (V2SI "DI") + (V4HF "DI") (V2HF "SI") + (V2SF "DI")]) + (define_mode_attr mmxdoublemode [(V8QI "V8HI") (V4HI "V4SI")]) @@ -350,22 +358,7 @@ (define_insn_and_split "*mov_imm" HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[1], mode); operands[1] = GEN_INT (val); - machine_mode mode; - switch (GET_MODE_SIZE (mode)) - { - case 2: - mode = HImode; - break; - case 4: - mode = SImode; - break; - case 8: - mode = DImode; - break; - default: - gcc_unreachable (); - } - operands[0] = lowpart_subreg (mode, operands[0], mode); + operands[0] = lowpart_subreg (mode, operands[0], mode); }) ;; For TARGET_64BIT we always round up to 8 bytes. @@ -2974,33 +2967,49 @@ (define_insn "*mmx_3" (set_attr "type" "mmxadd,sselog,sselog,sselog") (set_attr "mode" "DI,TI,TI,TI")]) -(define_insn "3" - [(set (match_operand:VI_16_32 0 "register_operand" "=?r,x,x,v") +(define_expand "3" + [(parallel + [(set (match_operand:VI_16_32 0 "register_operand") + (any_logic:VI_16_32 + (match_operand:VI_16_32 1 "register_operand") + (match_operand:VI_16_32 2 "register_operand"))) + (clobber (reg:CC FLAGS_REG))])] + "") + +(define_insn "*3" + [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v") (any_logic:VI_16_32 - (match_operand:VI_16_32 1 "register_operand" "%0,0,x,v") - (match_operand:VI_16_32 2 "register_operand" "r,x,x,v"))) + (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v") + (match_operand:VI_16_32 2 "register_or_x86_64_const_vector_operand" "r,i,x,x,v"))) (clobber (reg:CC FLAGS_REG))] - "" + "ix86_binary_operator_ok (, mode, operands)" "#" - [(set_attr "isa" "*,sse2_noavx,avx,avx512vl") - (set_attr "type" "alu,sselog,sselog,sselog") - (set_attr "mode" "SI,TI,TI,TI")]) + [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl") + (set_attr "type" "alu,alu,sselog,sselog,sselog") + (set_attr "mode" "SI,SI,TI,TI,TI")]) (define_split - [(set (match_operand:VI_16_32 0 "general_reg_operand") + [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand") (any_logic:VI_16_32 - (match_operand:VI_16_32 1 "general_reg_operand") - (match_operand:VI_16_32 2 "general_reg_operand"))) + (match_operand:VI_16_32 1 "nonimmediate_gr_operand") + (match_operand:VI_16_32 2 "register_or_x86_64_const_vector_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) - (any_logic:SI (match_dup 1) (match_dup 2))) + (any_logic: (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] { - operands[2] = lowpart_subreg (SImode, operands[2], mode); - operands[1] = lowpart_subreg (SImode, operands[1], mode); - operands[0] = lowpart_subreg (SImode, operands[0], mode); + if (!register_operand (operands[2], mode)) + { + HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2], + mode); + operands[2] = GEN_INT (val); + } + else + operands[2] = lowpart_subreg (mode, operands[2], mode); + operands[1] = lowpart_subreg (mode, operands[1], mode); + operands[0] = lowpart_subreg (mode, operands[0], mode); }) (define_split diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index c71c453cceb..5f63a7d52f5 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1205,6 +1205,10 @@ (define_predicate "x86_64_const_vector_operand" return trunc_int_for_mode (val, SImode) == val; }) +(define_predicate "register_or_x86_64_const_vector_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "x86_64_const_vector_operand"))) + ;; Return true when OP is nonimmediate or standard SSE constant. (define_predicate "nonimmediate_or_sse_const_operand" (ior (match_operand 0 "nonimmediate_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr106038-1.c b/gcc/testsuite/gcc.target/i386/pr106038-1.c new file mode 100644 index 00000000000..bb52385c8a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106038-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-final { scan-assembler-not "xmm" } } */ + +void +foo3 (char* a, char* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; + a[2] &= 3; + a[3] &= 3; +} + +void +foo4 (char* a, char* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; +} + + +void +foo1 (short* a, short* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; +}