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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 20-20020a17090a1a1400b00250ce1755e9si294974pjk.14.2023.06.23.13.34.05; Fri, 23 Jun 2023 13:34:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=INgjaM0u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231968AbjFWUcJ (ORCPT + 99 others); Fri, 23 Jun 2023 16:32:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231946AbjFWUcD (ORCPT ); Fri, 23 Jun 2023 16:32:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5779C2699; Fri, 23 Jun 2023 13:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552321; x=1719088321; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GsHjTGOIwG51l33j1RwStl2l2LqbNlmB/V7XSwlE9ew=; b=INgjaM0u4Pb6SmPXe7PVzCv6jVf663YsARRPXXfjZjp3hhxiSxn2MqAy 7B+Bvfn2tscDD0tY0HuZrqUj9q3AVC31zo0foGjjVpl6YsQZpC8mZ8qNF HKpBUDj5hUXIqSVQH1oz1YAVs7hAycL5QSg0LH4kR/TTkz524bpWxCP5p mfDFV768KA/H2yYeHfA1/FCG8JFsChticQMD4v8KrJuzdKOntOretczT+ T+7C1NwnDEtvb+59Gtjx82Qs0xByMGnJTMdxk8HiGyXrAfYU5rnyM8M56 8yy8uHOayxwl+5JH0mgHfGnh1jmTlCMffU+P50HQrVxJ57vZHv5mty3A1 w==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="220215600" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:31:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:31:57 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:31:29 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 01/45] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60, sam9x7 compatible Date: Sat, 24 Jun 2023 02:00:12 +0530 Message-ID: <20230623203056.689705-2-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769527005571519973?= X-GMAIL-MSGID: =?utf-8?q?1769527005571519973?= Add sam9x60, sam9x7 compatible string support in the schema file. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index a46411149571..4a008d86085e 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -20,6 +20,8 @@ properties: - atmel,at91rm9200-tcb - atmel,at91sam9x5-tcb - atmel,sama5d2-tcb + - microchip,sam9x60-tcb + - microchip,sam9x7-tcb - const: simple-mfd - const: syscon From patchwork Fri Jun 23 20:30:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6033794vqr; Fri, 23 Jun 2023 13:52:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ57dMuakq/339kN/9NzzLXY+J4d+KpkNM//a910DzeXnOximEU2e2/AhrF86j/RuHLk2/Tj X-Received: by 2002:a05:6a00:158f:b0:667:e17e:85c1 with SMTP id u15-20020a056a00158f00b00667e17e85c1mr15517289pfk.1.1687553578327; Fri, 23 Jun 2023 13:52:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553578; cv=none; d=google.com; s=arc-20160816; b=cfArHK/RdvJwCw9Fr0pUgM3mlLf/iXfp1Z73XynYoOPL4cmz71LDcBIC8wSQKSGeNK 8teiBdkMXD59tAtSouQ4S4sCbIadERgF6cSHBEX3q7llVTK8gH65jRFu3bQWoX2jsYUz NzhChGoLEgCt4P0Z0tIQNZ9lpem9O3jYq8ZvtSC9G8AlkchnylzEhEGwf1l1jTI2UTKu OCqo6dTUmD+OyPpnySga+8cYu7ElzEXZh5AjP47EGclDkdDmLRr/jAzEkLJ0M4crtoo5 RdZMsC3NCrNr/w0MGHkAesBGV2Z0mEKp5rUcLZwWInkXulkXYDVqXHEmJnymAf10Pm79 V8rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FXvU2MnBK8juNTyUJIA9/JVLURzUQL/JusuAgh+P6Es=; b=F2pCuAt4nHr8SPvjrLfheEf192Id4z40cx0UGY0FGz5WcVLUBOGlQE2R1JerRI2Psq diSMt8pjdgKxsL1VFktgSev3saCYy1qbDxwBqPgmFM6YKsr1cQvxawS7rN8szNfFGp2Z j1g5dsM47WpcYFKPgqxzC5lpIccnAU3uclAtL8jAhwzctYuTxwHRA/Ln34z+969QpZ7F orXKnyCoPqA7tmsOy+Bc73eTHWPQYEoj0hAZOc8otw/FFTdmOP8pAtC8wcvvw9PseKyS fRwVDCtb2jJ1ukuowTyC5e7cVE2kfYj57s8bfh4g5hJpxEvxXPIJq7Gv0D3avDGSYU4S xXeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=frpIchLi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 9445764bd8de..7e486cc6cfb8 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -66,6 +66,7 @@ properties: - const: generic-ehci - items: - enum: + - atmel,at91sam9g45-ehci - cavium,octeon-6335-ehci - ibm,usb-ehci-440epx - ibm,usb-ehci-460ex From patchwork Fri Jun 23 20:30:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6029848vqr; Fri, 23 Jun 2023 13:43:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4PTy0sZdeq2BQS5CqZ6rmRSkqRlU1er+tV3ZebGGWtcqm2Wn8Up3eDw+JwYQJp6s2uJwQV X-Received: by 2002:a05:6a21:3401:b0:124:bb55:f244 with SMTP id yn1-20020a056a21340100b00124bb55f244mr6031490pzb.30.1687552996306; Fri, 23 Jun 2023 13:43:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687552996; cv=none; d=google.com; s=arc-20160816; b=U74+PXj/B/8pgY9DwX88ZjtLjXknlaFwFK6fsMvFo9CQkg18aHP3lb8Kc1H7brEgRy 2PMkdh4fYOshSjXVCvvNsYvq688MtlIdSJRwKHKk+c6WnemTxooF0M8DQOtio6H2kb/5 qDjwALvx+grXrQ9VMhB7iq8IcjZ5/Iycptpcct4USwVtSGVtPPrJrLIr0dF1/h4C6+R5 eK5TQ2Wmx0BhZVsDFuovR53siI0IDU2pTY5PxoGcjiv8H+dr7Kk8suGsooqcjOQ5w7Lj WngxzgJi6+ft05yLlgB2i1bBhq5IiV+dRzMvJplZbewfbcOcCH0BeQMwOBJxQLYDn8sM /3qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y9bX9tFQupnVH6enknOsxll6Z3aDED8Ffb8Z5IYc+yg=; b=a/16JaBEo10p6rZiBd4pJEcQcKxHl0tRQ0ngxYwpl4Wolj0+OHy51GR+aInmNI9RhC hlfq2t0rW8DBru7w2XmE5jbAmN/Es5zsg3TTnq9PVU0IWpJfOb42C0jaTmxOQ+4dNj3D OPL9sUiZAF8Fjrz6ijrONAGTT1WgQv78XrKYFwb3danJ9WxIXEgiFMLONyuX75oiI1LY 2oCAa351cpa7Jq8lRx2PtZs9Aya2kgJvQ62TglqsolMwq7hIUB4rohqBAwe6zdC3174v Oj2MbcLerXtvMfD0pAo4AHrRz0sUKNP/QmviLUCHiD5+yHuT4qie+fv7W4dxv5v9+408 4uGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nM2UQCf4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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It fixes the dtbs_check warning, 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 7e486cc6cfb8..542ac26960fc 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -102,6 +102,10 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral + clock-names: + minItems: 1 + maxItems: 4 + power-domains: maxItems: 1 From patchwork Fri Jun 23 20:30:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112265 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6026504vqr; Fri, 23 Jun 2023 13:35:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7uF2VGzVyTMAvCvhxc77s3M4w1R2VAgFTLn3zCbc3fLziuv1fXeo8sdPo/++MU410h2e+6 X-Received: by 2002:a05:6870:4502:b0:1a3:16af:56d8 with SMTP id e2-20020a056870450200b001a316af56d8mr16004828oao.12.1687552507411; Fri, 23 Jun 2023 13:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687552507; cv=none; d=google.com; s=arc-20160816; b=UEanScQnGuNzef0zOUVFQURAYc243dy3CuJYWG6eaRYo6xZMdaVxYgknPX+MhGIQa0 jecmITMiY0ibBLGGDBCF9kuJcL5CQy+djDm90TPFVvk8hVyGDsi6tnd3seGcOHKF9deE 6z2PT1dLhq0NxYe2TsZMcWmgHsJHObRARHUxj9HNgh+3zpWNrS7aFE1wsyaGRrt7Sqoc b5ET4bxI/8Xowh6n9dmO4/GJH/2M99rn20eSor0FzxpAb8DgBaAD/go5WCKnUjdifQA0 13wHh6vGepcjyl6tv/T7cAkaQU8mjAE8b20eM5JF8hPF2tDWxtHOtOpvvJz7pYW7Plwh WgaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ikNMMV33qKx27sjD/6BfyeT2YCdTUUxd67zDmrYYv3U=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=rEMiFj9Z3bVPd1u4uzdWUf3vqTRO8lQG56seetoGOoxtFOHpBF0ncrq+wtcsq7tM4L Zgb9ysSQaHP8xZFzBfsf0VB5lH/bWI/rdxNWrKB7AOgXovT+C1Lo9WISJq3jeoSgILpO jzv1wXtXkrW0XsaagImiw07SCrLyO+inRclKk+EvbFwvP1PBHLnXqzp96vKPKwLM9yEx 7GgB3Ch6cuHYNT6hp1Upv8e0o+4leqD8zm1fB/Rj2FhVkBAoZcdSCgE/6B+FiP0f21Ka sF2grJl3Wsu/FShif4tlQxLLkszOBSZGwDge8ekWUtJZzfNFxWlQ6FHtXJWp1aQd1Pce +TFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=vJ72Xe3N; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index bef5e0f895be..e4f9e9b353e5 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -54,6 +54,7 @@ properties: - cdns,np4-macb # NP4 SoC devices - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + - microchip,sam9x7-gem # Microchip SAM9X7 gigabit ethernet interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - cdns,emac # Generic - cdns,gem # Generic From patchwork Fri Jun 23 20:30:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112268 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6029857vqr; Fri, 23 Jun 2023 13:43:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7PjycC6jvhEgSbonTszjlOM+ecc9+lBYhW8j5U/KktaL6+KOHJDmQ1Kmw6ZKrtMwBAxfRu X-Received: by 2002:a05:6808:1392:b0:3a1:b2d4:5f64 with SMTP id c18-20020a056808139200b003a1b2d45f64mr2178337oiw.54.1687552997509; Fri, 23 Jun 2023 13:43:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687552997; cv=none; d=google.com; s=arc-20160816; b=kLuMzzwxl5G8Tel5wZVHXY9BBKDiCbeKrftB/xeRR/FI4RoLUvr3Up0pwBENxDNChk Ofo7xWqK5zB8z3mQhNLnvBeGD4KcLpthR661awMx/QPQg+KFVzzmCeWozv2OqKpuHiIq VV/JDHnpm0bMatUy+7iShsLwSzctZwA3ym/H0tL2dFVEVGBCiVD/6qk097mqoDPEdjN0 58ckX90soiVJq7IZjck7UkdbWU6aH0Z1EGfDP6hpxXCYK8yGN0VXsd87l+/J8HfAAFOd UGSdlrWY4NmPDmWQMnDalCzgKge4jPRHcV476KflKR1qh/zmiUYDcCy/XCqSbZi6QaBJ KMQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hu3+2Qv9/B+TyAjUrAOhFmPFeLsxClYcg1uIxOBWOOU=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=F5MS3+fxJsiB0JbDIPDCXgfBs+y9OtDs44TgvgPSXoCW96VM6lKSzJemKPddiWtiVh uQyI/au9lw/Wvy9H28fPqodlO39n4/nQUkpTAzPivi38Mb09Fuj7CdBDN3PDsw2VYpye kcwy9okY5V2ioG/YBZtrjussLC9N5Cn36/TQWXnC3WrjCayD/2Pg3KkaQgYeisw36AqQ SAeIFhSqdBuu/fbm/hgaoZ9OW/2T7aQAmHGYhgWAQCpzr6gm7HXdUMlJQYvmQanCM6LW E1azvTOMXax8vbJoR/voUTBM/uZG141pHEuLNqHv33YbtGxmEwqfLv6sePruUMzSnmBN j1NA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="0/CDT82g"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 60dc56d8acfb..43a77ae0c38c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -232,6 +232,17 @@ static const struct of_device_id sama7g5_ws_ids[] = { { /* sentinel */ } }; +static const struct of_device_id sam9x7_ws_ids[] = { + { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, + { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, + { .compatible = "usb-ohci", .data = &ws_info[2] }, + { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, + { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, + { .compatible = "microchip,sam9x7-gem", .data = &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1133,6 +1144,7 @@ static const struct of_device_id gmac_ids[] __initconst = { { .compatible = "atmel,sama5d2-gem" }, { .compatible = "atmel,sama5d29-gem" }, { .compatible = "microchip,sama7g5-gem" }, + { .compatible = "microchip,sam9x7-gem" }, { }, }; @@ -1360,6 +1372,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, + { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] }, { /* sentinel */ }, }; @@ -1497,6 +1510,28 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; } +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; + + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + ret = at91_dt_ramc(false); + if (ret) + return; + + at91_pm_init(NULL); + + soc_pm.ws_ids = sam9x7_ws_ids; + soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; +} + void __init at91sam9_pm_init(void) { int ret; From patchwork Fri Jun 23 20:30:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112270 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6030393vqr; Fri, 23 Jun 2023 13:44:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5uDELPkFwnBmaZSSeaC2aAN5hyRVpOkZ0M44lFnt3M706Nc7q3c0tGZDJKEIi0OPBY61Lj X-Received: by 2002:a05:6a20:9389:b0:121:637e:f0e5 with SMTP id x9-20020a056a20938900b00121637ef0e5mr22422295pzh.5.1687553078000; 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Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o obj-$(CONFIG_SOC_SAMA5) += sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) += sama7.o obj-$(CONFIG_SOC_SAMV7) += samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..d998fb327860 --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x7_pm_init(); +} + +static const char *const sam9x7_dt_board_compat[] __initconst = { + "microchip,sam9x7", + NULL +}; + +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7") + /* Maintainer: Microchip */ + .init_machine = sam9x7_init, + .dt_compat = sam9x7_dt_board_compat, +MACHINE_END From patchwork Fri Jun 23 20:30:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112274 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6030548vqr; Fri, 23 Jun 2023 13:45:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5j3HjD0UiIobEEPLMxkXi+D1zLb3+7ZMeyMt1O0H/zhU29xKhy4yGLmjWOuhHboZb1Mm9l X-Received: by 2002:a05:6a00:9a8:b0:668:7137:ff02 with SMTP id u40-20020a056a0009a800b006687137ff02mr19837088pfg.7.1687553100631; Fri, 23 Jun 2023 13:45:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553100; cv=none; d=google.com; s=arc-20160816; b=kcEpceaTfL9nPbeh6A5N1wcOF/lc6C9MHY+cPhE0ppicgcHU1ALYubVU/m1ZG5aeKY gNIWSK5j+Tox9hjAq4BcutCo+7D0HsPNzf4XsQabVagl20nq1jTK5qaLgop1uGr1EviR xt0YsYVcQ8Oz12IQ0yw8DA3wyBKsk1qC2RPQLhSU6KL+1YJ6PkUZdp7wu09bVG465zYx 0h4G3ogefxhw1f5LU7kjNscPqTKyD5a++fhzMqbHdX3dxDBwtL7cxOnZFVLVZuK1zc8K BI3TEOKT0I1wzlSmXoy1hWOdbhTBZDKHB+GUV8kpUOAHw/FANFh/is8rCnZv2Si0BcGj eyGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oron7AxdJVUbc/DhvvQzbeHcoBkiQnUs0r8P0HSvEBw=; b=d3zKE0c76Wvx+Guql2ygs7Wkn5hT++WVD7DOQOC4bGiWqMyO/i2oY9ZExebk+3/f/Y kNZmK5Q2ENspA8Bf5bhunCXWCRFu2VLDJFXF42fUdvcm9lxhBJuigtbUxh6wORmj7M2m 8vXcF1AoXxBZDvgCjaAiBHuvx05F8SnPPR9oKtmtFFqZi28eqbKk9WS3cM2gXc4uzbOP /5jeASxcD8qcAW27NSOuj7fekhLW1WgDZtp9E+B8KZg6v+tuP/97Cfz7XGSAZF0kNF3W RmYBgfh81QWqXKcK+jyUOa+bNPPnI8A9sDT+D0bv9vqTxz0oUXwNNBHhCkR+udo0Hb7J 5Hsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=FtE6K6XC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..cae3452cbc60 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 1Gb DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 512Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 128Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 2Gb DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..26dd26b4f179 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAMA7G5_CIDR_MATCH 0x00162100 +#define SAM9X7_CIDR_MATCH 0x09750020 #define AT91SAM9M11_EXID_MATCH 0x00000001 #define AT91SAM9M10_EXID_MATCH 0x00000002 @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA7G54_D2G_EXID_MATCH 0x00000020 #define SAMA7G54_D4G_EXID_MATCH 0x00000028 +#define SAM9X75_EXID_MATCH 0x00000000 +#define SAM9X72_EXID_MATCH 0x00000004 +#define SAM9X70_EXID_MATCH 0x00000005 +#define SAM9X75_D1G_EXID_MATCH 0x00000001 +#define SAM9X75_D5M_EXID_MATCH 0x00000002 +#define SAM9X75_D1M_EXID_MATCH 0x00000003 +#define SAM9X75_D2G_EXID_MATCH 0x00000006 + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 From patchwork Fri Jun 23 20:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112271 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6030414vqr; Fri, 23 Jun 2023 13:44:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4jh7BYr9wo4cEY1tNPxvK35z3liuADd+qz2E2KFJWa8qjc1OY2dZgiIsX4GFG7MqlZmn2M X-Received: by 2002:a92:d947:0:b0:345:6ce1:d255 with SMTP id l7-20020a92d947000000b003456ce1d255mr11626ilq.1.1687553082371; Fri, 23 Jun 2023 13:44:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553082; cv=none; d=google.com; s=arc-20160816; b=yR7ykmMah2LioeNANCr/RAilaNdV8L3nydtynnYFM3qSdeDcaP8zybBwc0kok7bTYP cdlNBg4rlt/suI4s2d0fKpwoxgxZjYDUxwuTTeEcW53ZF9DVW1dZyT/nEFVQ9xf+tsSZ sfFsLpwc0oHUfilA3+YFCxt2s/TOueJOCmRKO6WAI6X0alnP1mLOOsfLyVc1f/dyaBl0 TLahuf5u7gTSyuUWRYPFtzr+CrRFERQhZq0L8XM6MhXX1UBm8fqXrVcKDKy5YRZjLg0b 43/aKc2bUvQF211frIj4goryRWrDwFj979FkZj46CKaR2mWLZWFvV/MkdSUaGIIjtZD7 vkOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LULXOQPwrM42B41TJx4tS2wZX8M1vARVm02F7SbueJ8=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=RB485RJct5hkow9OQKsxE7ANxfqPGxbj9YvPS7me+k9q9BketlYX7Fwb5EERMM639e 9OnfNi5AJlga9d2PZ5RkBfCiKMN7/jUjnikSRJLbx/W3vy03L+Md0/Yng7NAjIZTzTOx Qx0UbACej2gzbfdWdg8F3c/dpjknrK3uD6Ft8iaZaRZe1k9A9liPKUPvhPVvbYVlQgS6 GmQ18alAVi/FzIcEwvna6c9ogRdHe2P/aujSvnDfL/N+AKAUaSEXXLkSoXCVFas3mWcx eyouy9WqQAInSuHEY/G3Wo7MhATytlnRYY8K2clMo3HTZmKw8fMi6SMaf9o6SCHsT3wY CvFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LeOqayjx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s33-20020a635261000000b005533a94a2fdsi201060pgl.466.2023.06.23.13.44.28; Fri, 23 Jun 2023 13:44:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=LeOqayjx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232240AbjFWUgb (ORCPT + 99 others); Fri, 23 Jun 2023 16:36:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232066AbjFWUgY (ORCPT ); Fri, 23 Jun 2023 16:36:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EA9B2944; Fri, 23 Jun 2023 13:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552555; x=1719088555; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BjHeEGjJH4FK+Dy2tpLAgiAMGYHda5kF0H68rjaLOR0=; b=LeOqayjxXlyW+efmTb3n9XMeSSb9+gHRx8umPtrvd0GmI9x3CAz0fvVx B8667wAB8QTHMHxt9E1RNZeVV+2hYs4rC5felaHD82sYGw76+ntjbGtpg 68WYWM75p+odOrqaRNG7QxhgTYeWIAQdWD5lu/ADoxPyNEir/OviWdwSw NHbA7THis1HcJ7XOJ01F7hRjFrDonmVvWkIfx9HLhu7ONoj1T9PRVNSxa VAOBf9gwoaSeqwKXaxZik3GQNJlDwzQgPjl0nGES6HOfl6pPREJrDGjw+ m6jnTeG2Ow/2BzYeyUdAf2dvwMaHcYJK/TvKLfJ1iw4uRoTYnVST2wjjZ A==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="220216416" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:35:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:35:25 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:34:56 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 08/45] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Date: Sat, 24 Jun 2023 02:00:19 +0530 Message-ID: <20230623203056.689705-9-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769527660668031938?= X-GMAIL-MSGID: =?utf-8?q?1769527660668031938?= SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 0882ed01d5c2..b3012641214c 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, unsigned long nmul = 0; unsigned long nfrac = 0; - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core, } /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; if (update) { @@ -666,7 +665,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, goto free; } - ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw = ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 1b3ca7dd9b57..3e36dcc464c1 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index ac070db58195..452ad45cf251 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(plla_outputs), .output = plla_outputs, + .core_output = core_outputs, }; static const struct clk_range upll_outputs[] = { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = { .input = { .min = 12000000, .max = 48000000 }, .num_output = ARRAY_SIZE(upll_outputs), .output = upll_outputs, + .core_output = core_outputs, .upll = true, }; diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f135b662f1ff..468a3c5449b5 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -104,11 +104,17 @@ static const struct clk_range pll_outputs[] = { { .min = 2343750, .max = 1200000000 }, }; +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(cpu_pll_outputs), .output = cpu_pll_outputs, + .core_output = core_outputs, }; /* PLL characteristics. */ @@ -116,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = { .input = { .min = 12000000, .max = 50000000 }, .num_output = ARRAY_SIZE(pll_outputs), .output = pll_outputs, + .core_output = core_outputs, }; /* From patchwork Fri Jun 23 20:30:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6031364vqr; Fri, 23 Jun 2023 13:46:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4YtmaeAwgkfOdEAcL21vDOPsSmAn2UsvKSKm6x70fwJclx8y+hCkd1Ro2127gAkqOM2n8p X-Received: by 2002:a05:6830:1d4b:b0:6b4:642b:ae81 with SMTP id p11-20020a0568301d4b00b006b4642bae81mr19755575oth.5.1687553206153; Fri, 23 Jun 2023 13:46:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553206; cv=none; d=google.com; s=arc-20160816; b=qxoHHJjPzENZ3xBlWH1J3L0MmhtZGql2Ct9jn9XLV6jVxKa2ks+odkbIP0pnpltOhe TUrpElOP0IEhH7B+iPzuchm1vqTcEHEIt3FgikGtsbVAVrh3B+HEvzVIjJGj6AIzD0XV MX5I8Emk8m5u757yQrJcaa6z5La45S47rBOON+IR9ZEjfmLVvfpFmZy1hFRodekW9vvg CWMPR5yO1ZUh3kZC74Sg1O74AIT3JxTh8DzguL2CLyfXP9MLlMPuHm25+frd2UxqKsM3 K7cYOlGfyMV0gOXg80XLoacdsr/1Z6i34dGNBlQd4U6/qpJAiIe1zCQlH1RoKzDpdbIC L60A== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s2-20020a6550c2000000b00553d5cc2c8bsi191294pgp.508.2023.06.23.13.46.33; Fri, 23 Jun 2023 13:46:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="sw3K/ej6"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232276AbjFWUhJ (ORCPT + 99 others); Fri, 23 Jun 2023 16:37:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232083AbjFWUhB (ORCPT ); Fri, 23 Jun 2023 16:37:01 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DF47273A; Fri, 23 Jun 2023 13:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552590; x=1719088590; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H6+qeb5lhbTKb0rFTMW89wX0Vd03nImzkY3g4+gHCu0=; b=sw3K/ej633I0E4UwoLLQQw5Up94xZGy9pdLuwUaBLcqDyG2IrICbuPtp VNla8kxzEhXbpukRaz8OpVp+ToKM/hd9m81y5Q6l4JXnOSXg3ZFqENgKG 8pUVSflTDmFtvMIqTvy4UlQKb3VOcMZiTwbEIs88+XrpdTgA2ZUgdZfFu 7CFf85etT22yI82QY5fcATHNWFf7KZQcH+TtJsKop4C4dN42eT/yDI5dH KRbKLQkqQS1/Bg1b0aRvg6/yT4XAipdK8WnGWGQv9qNMz+rqnlf7CCcPa Egb1LShkhigzx9t8nCwrGOCYzerN3j9hYPbM4Y+6lqtibjj+twKylruwL w==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="219550360" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:36:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:35:53 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:35:25 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 09/45] clk: at91: sam9x7: add support for HW PLL freq dividers Date: Sat, 24 Jun 2023 02:00:20 +0530 Message-ID: <20230623203056.689705-10-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769527790370322877?= X-GMAIL-MSGID: =?utf-8?q?1769527790370322877?= Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div = 2 -+--> fpllack | +--> HW Div = 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (Given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++---- drivers/clk/at91/pmc.h | 1 + 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index b3012641214c..76273ea74f8b 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, { struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); + unsigned long freq; - return parent_rate * (frac->mul + 1) + + freq = parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>= 1; + + return freq; } static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = { .restore_context = sam9x60_div_pll_restore_context, }; +static const struct clk_ops sam9x60_fixed_div_pll_ops = { + .prepare = sam9x60_div_pll_prepare, + .unprepare = sam9x60_div_pll_unprepare, + .is_prepared = sam9x60_div_pll_is_prepared, + .recalc_rate = sam9x60_fixed_div_pll_recalc_rate, + .round_rate = sam9x60_div_pll_round_rate, + .save_context = sam9x60_div_pll_save_context, + .restore_context = sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, init.name = name; init.parent_names = &parent_name; init.num_parents = 1; - if (flags & CLK_SET_RATE_GATE) - init.ops = &sam9x60_div_pll_ops; - else - init.ops = &sam9x60_div_pll_ops_chg; + + if (layout->div2) { + init.ops = &sam9x60_fixed_div_pll_ops; + } else { + if (flags & CLK_SET_RATE_GATE) + init.ops = &sam9x60_div_pll_ops; + else + init.ops = &sam9x60_div_pll_ops_chg; + } + init.flags = flags; div->core.id = id; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 3e36dcc464c1..1dd01f30bdee 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -64,6 +64,7 @@ struct clk_pll_layout { u8 frac_shift; u8 div_shift; u8 endiv_shift; + u8 div2; }; extern const struct clk_pll_layout at91rm9200_pll_layout; From patchwork Fri Jun 23 20:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6029654vqr; Fri, 23 Jun 2023 13:42:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ68ZuPnp+QpdBilIhB4RYV/nXd4tT5VbgGKI8fiPodfIKbCMVevl96/6aCE88H583uuMIEK X-Received: by 2002:a05:6a20:1614:b0:116:fd37:c924 with SMTP id l20-20020a056a20161400b00116fd37c924mr27157585pzj.5.1687552967756; Fri, 23 Jun 2023 13:42:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687552967; cv=none; d=google.com; s=arc-20160816; b=d2X95luLuT9AGIt3Eth/n7sPJQ66u4r0tlpOx/z+Kk7QLk+qIoHIBhBpQIHZe7/M0l cRRQDYcM6iG2Efq5Vy92WljJem0TTbLaW3pXWfK/PesBYjAndAWxnOsoWWaUMD3/+xR9 l3qq6YU+wjix5G0IssXD/5NzmqwCxc4AZYJfydmL/1Cl+yQPZ2nYJV/vCCDCVIKcsv2v X5jVTnlBfQX2a/bB2Sdfa1O0pCn41G12gOftp3JledhZqwt8fMVllt9YlkEaZmD0x+Eb duFFlcl2FrY4/uXwbnrzVN2Hq7lniK3Kr9+zC8ToGwk3IDDmBTwdMPKtoffKA2sX84xP Hz1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uKwwsHtQZbeI92VOl5+0qVz0vPFpjMd6jyw2UsGfaOE=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=iSroapeunr8IXOFpyQsm7E8oFzf/yD/9gDBku0NvvkhkGsznIdI/vsNjOjQ7XEsBuM z4b+SWYJCo9uffTEpLnftFOjI1mJGgQ/TUqMcVwZFI1VyslujhH7i412kEh6W88GjD2b IUfDNYEVlXRqBf+NTS4eOYMc/l9ZAA/+1s7XCASeJgpkxO59ISBh3yMJw1OtDJfO+flf KyMdpuQyimPJqb9P1t6bLjPZjz1JkuQH9SO5O+JapPf30ueDYT9MaOYpctkeb53Jf2t5 miSfRcRzXBhzFmngbtdTj2kfG4sGChqKqIn7FDdNFcryininU0mLofWxrUBXxMCvsTQj yJlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=m2lq5uWp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l69-20020a638848000000b0054f9f9c744fsi181358pgd.639.2023.06.23.13.42.33; Fri, 23 Jun 2023 13:42:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=m2lq5uWp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232193AbjFWUhp (ORCPT + 99 others); Fri, 23 Jun 2023 16:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232062AbjFWUhd (ORCPT ); Fri, 23 Jun 2023 16:37:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E144A2965; Fri, 23 Jun 2023 13:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552623; x=1719088623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+NDzjzg+Ni//gNmFZKyOgL7uxanPfC14OsbzNCq8wzw=; b=m2lq5uWpNEOk41B54sKg/a6G8/YVRgwTL7fwyUga75Zx7jb0zYFDCSB0 IXN8qWHHa3KuybazFbu4CvsIvUUXCJRQ7sHrXz64qCjklHwhawph53Kyi HTQaHG2kcIRLtke1aU1/Ck9E5VUvs8zrjpcuNSJy+9MxWAj3v17J5+1HM HtSPQCKI83I7DQR2IA5U8yNtGZ3uWiZlw7OduA8gXePFLLdcLvYrVCC9l g6uDyaifygWZyv9LkmwMng6Bj1IUOr+p1T1eKX5sa5K7WLYBMDrlBG1Hh Si3yzfrXdCBJuNvzu9G0vsI7SZ6RVdW2oYSGtKgxPlxmxxsTqDAuxjklG Q==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="158362094" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:36:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:36:21 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:35:53 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 10/45] clk: at91: sama7g5: move mux table macros to header file Date: Sat, 24 Jun 2023 02:00:21 +0530 Message-ID: <20230623203056.689705-11-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769527540843712275?= X-GMAIL-MSGID: =?utf-8?q?1769527540843712275?= Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/pmc.h | 16 ++++++++++++++++ drivers/clk/at91/sama7g5.c | 35 ++++++++++------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 1dd01f30bdee..f3c23ff0da02 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -121,6 +121,22 @@ struct at91_clk_pms { #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +#define PMC_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i = 0; _i < (_count); _i++) \ + (_table)[_i] = _i; \ + } while (0) + +#define PMC_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i = 0; _i < (_count); _i++) { \ + (_to)[_i] = (_from)[_i]; \ + } \ + } while (0) + struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, unsigned int nperiph, unsigned int ngck, unsigned int npck); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 468a3c5449b5..75011df708cc 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -16,21 +16,6 @@ #include "pmc.h" -#define SAMA7G5_INIT_TABLE(_table, _count) \ - do { \ - u8 _i; \ - for (_i = 0; _i < (_count); _i++) \ - (_table)[_i] = _i; \ - } while (0) - -#define SAMA7G5_FILL_TABLE(_to, _from, _count) \ - do { \ - u8 _i; \ - for (_i = 0; _i < (_count); _i++) { \ - (_to)[_i] = (_from)[_i]; \ - } \ - } while (0) - static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); @@ -1022,11 +1007,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); - SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, - sama7g5_mckx[i].ep_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); + PMC_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, + sama7g5_mckx[i].ep_count); hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, parent_names, mux_table, @@ -1109,11 +1094,11 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (!mux_table) goto err_free; - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); - SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, - sama7g5_gck[i].pp_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, + sama7g5_gck[i].pp_count); hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, From patchwork Fri Jun 23 20:30:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112275 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6031360vqr; Fri, 23 Jun 2023 13:46:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5q/3JyHGVGvW6tSIlydv1+kBOI2pPtRvJhV1xujz0Z/R2aq8RMx/jPXDKgJ4z6sOdDlPdz X-Received: by 2002:a17:90a:bb85:b0:25e:7ead:3c9 with SMTP id v5-20020a17090abb8500b0025e7ead03c9mr21511154pjr.19.1687553205963; Fri, 23 Jun 2023 13:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553205; cv=none; d=google.com; s=arc-20160816; b=FCf/+BIiVDhR3NOp5h5QXW+mra1w9fgKB9sT5j38xCM7vQSp9K0M+4hhkaLxArqPvZ nkFjATdK3N+K0Vcu69tnS8J+it+BJBsEG2KFsHR6DJY04RVvknejd4ahoVGxm1JBWg7v rHBNzT1VnI13UPsJqCY4AgsV773w+jPOeSEfEiFJAJX5DTBIj2uFLmuRO862djaIhCfV z8J/BW1H2x1+2c/vXYF1HO6uVA2m6FrsooRXgX2hXZuCGyeYXXrBy7PtQyu8gYPKseDk y/Z1WKTeaRQJV7Kh7r/vHBfXRLfiKjjVgWmmsQ5w0pd8/CFJR61aR7dbKgSsBDICOz5Q 7eww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tIdN7hjS6UOVR0820x9EdXhPjscrm5Nhd5ss44ZnwSk=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=MwIV1aKcTOQlh5AD4COHKdDZmmloVz1ODWyMeGiHBr9/6l6tewHoJwyAyA9eH3ZEXo tIdsfz/li0HBa//ksYpprvFMplVffYazHPMkJJmhjTN3NDwVq8e0iqOznKfpLAt3QRuV tJMciSFZV3DXAgW7yEkNCjOhyjW4coX5Iteum7Ih3n+MmnD6+q513FJKLxV4BQsdWEGX 1U6z6yEnNi+vO+bbcmkoZClnAed7g73601h5CGUwQAUCti6Gc1qb5OmrYm1xNDkro9/S Nf8joVKJRCOX4T9SEExgIHv1JxA707XGqU+cxtJyLx2tWvwjUKG4lj5ZORQuSxpuPnXF CrBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Rz7OZkAw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/clock/at91-clock.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index 13f45db3b66d..446937fab950 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -10,8 +10,9 @@ Required properties: - compatible : shall be one of the following: "atmel,at91sam9x5-sckc", "atmel,sama5d3-sckc", - "atmel,sama5d4-sckc" or - "microchip,sam9x60-sckc": + "atmel,sama5d4-sckc", + "microchip,sam9x60-sckc" or + "microchip,sam9x7-sckc": at91 SCKC (Slow Clock Controller) - #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. - clocks : shall be the input parent clock phandle for the clock. @@ -32,7 +33,7 @@ Power Management Controller (PMC): Required properties: - compatible : shall be "atmel,-pmc", "syscon" or - "microchip,sam9x60-pmc" + "microchip,sam9x60-pmc" or "microchip,sam9x7-pmc" can be: at91rm9200, at91sam9260, at91sam9261, at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15, at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5, From patchwork Fri Jun 23 20:30:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6031447vqr; Fri, 23 Jun 2023 13:47:01 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5vzl/xN5KylPUhe57SjJF1KNKp4oN9/F3pJlmd6WoWQVntnM8eVtTwv/nDUVHgkC+hVrHb X-Received: by 2002:a17:90b:4c85:b0:260:f29b:4058 with SMTP id my5-20020a17090b4c8500b00260f29b4058mr8236011pjb.20.1687553220664; Fri, 23 Jun 2023 13:47:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553220; cv=none; d=google.com; s=arc-20160816; b=W9VlqDsvBCus4w+OhzBhfGvyOdy5LqkBXLf7B/ItBPVKkaRO7Z9+qkO3x/lVEqEbdZ AxXExFmLiMho4g85xpVzHUnQkUbx5NxoTrYCvJPTRFEz0DbGKKhz1ZBBUhrDJDBo9/T0 KDnPrk2wAB7I6gQMAHi+I4qw2ysZ+fMQiOO5pYzqvn0V31I/Cj17D8Zkd8Q/xUe1oKwx BRZ++NuRi/V+AoFadNcBQbJtTKwlV95CKqTcuawqanacN2XXrtwTd0m8RNXZbZDdrOX5 lXVlKjYF3Q96z7Oh1m2vjSc80dknE5Yx+ME3v5aX4mXtm6WJqx0/lwWGP2ZkqN1p/rKr EnaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GMCDD7VhKfeHg7KxLj3ePa4ATOlUGSE3Wh/pc6TO22c=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=zozp7mLYuH3c+eqM4zaKeYmGS/4Jwji+1MsnX3OlZQXk1LnyRMJhtadxvXHA8zpV2y /n1SpdLwGgHWke+5B6ClY7cNCFsoKJWh8gvXii2EYfj+DyZfD3fIwtLDznSoABD/ViI2 TXpz4T5RXPTrP2uvqrQyBcgnu2yIpULKkLuy4MKMSJNX6DLSegJsJzc3Nsr3Cin06iMt vVpFcHSWTKL4gQt9bxyHZVzwXD7kYEomFvhLfq1RxoMgPm3DhwoHw9zRyYQl3yhUao6d V18C3rI2KHSWbqsfGqPjjOCo92jAFvgHw4t+DGCFLbd7Ij2aHufD8OwTaiBNHQn8pNRu RgMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ANyD+EOT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..593a13c277ab 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -22,6 +22,7 @@ properties: - atmel,at91sam9g45-rstc - atmel,sama5d3-rstc - microchip,sam9x60-rstc + - microchip,sam9x7-rstc - microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc From patchwork Fri Jun 23 20:30:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112269 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6029865vqr; Fri, 23 Jun 2023 13:43:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7eDQmk18qPv0n0SmOQUAIV+36qcPszEVLCSPymtMBKHKBDQwP3bD+VJBXRkwOq8s5wZT4d X-Received: by 2002:a17:902:ce8d:b0:1b7:c167:f267 with SMTP id f13-20020a170902ce8d00b001b7c167f267mr146003plg.54.1687552998053; Fri, 23 Jun 2023 13:43:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687552998; cv=none; d=google.com; s=arc-20160816; b=vGKPi3xVyyF6ycX2ef8KrDEeRxL+Nti9Ym3vfhg3pYRE4NPHEvKJWhoaMWkVHXbeCR Zk7tZZkH+rMZRs5Dsd8yDUzh81LYJTko5yO/xkHLJxsntCFZhtGuAyEdQemDIJnPWrzb bL6SEzs0XsNlbIujsPxKc+ww6gnP2QZ4YdJ7/6QOqSB+lQddJe11BjK43E2Aova0KPSs VjtIiWTVGnG2nCbBYXVY6rEdJcqbokHe7p50KoLxlLdAr14SsvCsGbivPCkF0AvyXSnq dZTiWd7P68BoJ2JERBzeE44h/Sx1AOCRDNCslEb7Ovnp4qFu63+VyGLFZACM4GMxY5vG fYpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=v4pRHAZAYUJZ7gLisNo5CcBHBMzgLSw4z7VH3oj1g7k=; b=ceHKuxfD7GqeDUU8rwfnhRKTFGTltD0cKPEGOBhJEhLzhHevAVs5yhpMByTrz3nwR2 n6fzOXZHWRvhwLu9jmSm+gAr0YCiMGu+jfpwE66MPJarlIDjZj7Xgy0DjmjX1RauNSJ+ hoWvx+eMePIVY5PImcMWttTGKhRSQcjB6m4EUEoVGSr9+Mbp3/mCp1OzGt5QJmVZ2HQT x29U+rXJ4TDKArbYPrAQxA4bVvhlZuVumWBbzQGbVvD/Eq3csuhkWo53J4wGJgUkESjM KGQGu7+42Du3ZG/87hNnBUF7442p1D1rlm1ZEwU9RrV49PWUg3SRUxvTcQuUCMj0wDeC n8vA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RYnhptDs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u2-20020a170902e5c200b0019ccffb3fd3si10275100plf.509.2023.06.23.13.43.06; Fri, 23 Jun 2023 13:43:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RYnhptDs; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbjFWUkR (ORCPT + 99 others); Fri, 23 Jun 2023 16:40:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232413AbjFWUjV (ORCPT ); Fri, 23 Jun 2023 16:39:21 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE3F130C6; Fri, 23 Jun 2023 13:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552728; x=1719088728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gvnR65uyKMk5CUoToEoiuPKzluNwCII060FV6LYqd6M=; b=RYnhptDshMMsZd4/PLsPgGBG4dI8hSWKfH3vdAmNOtKTQZX6P97xH2Fv 3OdbWKaUJyRhzjKgIqsgxQ2i7UkBhoU4HSxQIC9IMMT66yFoxufdWsI6g hL0qgFB0emP+fN/qehLoiJENwHmJ8F/rGnCXAF8jTn30+rS5HR3Z+Nf2H FqV9Zy58aMwqkc+qwVK+Ddys3APAkiV93dywntJUWhbIzHtF9pW5YaH8V K1zDqFPCFO8fvGSEQ0hs8Dd07jBLdMU6CQzlqItdLyrP3hIvcWQ9dzgmn f5+QJffHAERiWurcgktZYgokgEuefLz8FgJrtS+LWQK02QHEn1jwoXw8T Q==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="158362329" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:37:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:37:48 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:37:21 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 13/45] dt-bindings: atmel-sysreg: add bindings for sam9x7 Date: Sat, 24 Jun 2023 02:00:24 +0530 Message-ID: <20230623203056.689705-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769527572576029120?= X-GMAIL-MSGID: =?utf-8?q?1769527572576029120?= Add RAM controller, shutdown controller & SFR DT bindings. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index ab1b352344ae..1e7349987d77 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,7 @@ PIT Timer required properties: shared across all System Controller members. PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or "microchip,sam9x7-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,6 +31,7 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", + "microchip,sam9x7-ddramc", "microchip,sama7g5-uddrc" - reg: Should contain registers location and length @@ -89,7 +90,7 @@ SHDWC SAMA5D2-Compatible Shutdown Controller required properties: - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or - "microchip,sama7g5-shdwc" + "microchip,sama7g5-shdwc" or "microchip,sam9x7-shdwc" - reg: should contain registers location and length - clocks: phandle to input clock. - #address-cells: should be one. The cell is the wake-up input index. @@ -156,7 +157,7 @@ required properties: - compatible: Should be "atmel,-sfr", "syscon" or "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". - It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x60-sfr" or "microchip,sam9x7-sfr", "syscon". - reg: Should contain registers location and length sfr@f0038000 { From patchwork Fri Jun 23 20:30:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6030495vqr; Fri, 23 Jun 2023 13:44:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ50Jy1ERs5KDyZ7ozVvHTQnJ5sogkd4d0f5TWIYxi4YJ1AaneWiZuzFo1TzMYAsR2yLbW8u X-Received: by 2002:a05:6a20:8427:b0:10a:e9ff:808d with SMTP id c39-20020a056a20842700b0010ae9ff808dmr29332416pzd.0.1687553093136; Fri, 23 Jun 2023 13:44:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553093; cv=none; d=google.com; s=arc-20160816; b=Q9OK7PCfVt9E2B+RnzEQBueLcQ0xVvP1Hvpdi3bt4p9cBnUoNxeMI8Iog2RsOvaZwy PssXOeG45foyfnLiFcYBVdmi0UnCXhPIBju967VENzGICdr6lPxMu6Ijf8IhT6eZPRi6 irNBZfZQH3pwMuIlqGWgybg20HbBBK4A058D9Ys3shkgqR3Zpm14BilGCDIr77awvFK9 gg0YxW3SHycXPQuPDq/FAWGwPOohlu6cAkJnwPaY9iDxLvfq2yOZGlqUF0+mO98BVgeQ GbrfqR94KwN7QWUiJVQvt+SrgSLX8lORYu68TaU8LwQl72Ap4SYKL2Nx2bKRjfXpNGRq pKPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=s7TrlOqFNBXjlE1lRIN34SV66dwO4yGHrV4KlmQ/iKg=; b=BvpczqNRg4KG+VSqxkfLERm9oS4EszE5xOba5LlIjscx1z6T98+JH3sDjjVYAetbJX +aC73c09VGAx4ozw0uWHZqX3ytLDrTYLTrN0dp53omTaC6RplybhhnwHs03nzRKACEn/ qolX4Zj5j8Hcmq//1XK0HrB9o+rP8jWNBrDpj5ggp2RQScm+QiO6sLz+dELMXVxVBtz5 S8G22AmhIBsQaEqhbBOH5iXmbZxvXyaRvfc8S1cuGQkabA5UOPKvtgmW2PFW29v5ZMS9 Pov9AY+PEcPMYm+ouTvRgHpBOkFLVTdK17WVscCYFIegbna/JXD8l4b0pgPjhrkrwged DE9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=KZhoCd4w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 0b7383b3106b..f0736696c883 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -12,7 +12,10 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-aes + oneOf: + - items: + - const: atmel,at91sam9g46-aes + - const: microchip,sam9x7-aes reg: maxItems: 1 From patchwork Fri Jun 23 20:30:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112273 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6030535vqr; Fri, 23 Jun 2023 13:44:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4ZCehdueK8q1ezhAExO1ujmvelLefmaCtYuO/3XvBF0TP4/IjmwuccL8lW7ZAZAIqmgMZY X-Received: by 2002:a05:6a20:9143:b0:122:cb38:637a with SMTP id x3-20020a056a20914300b00122cb38637amr10290983pzc.29.1687553097786; Fri, 23 Jun 2023 13:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553097; cv=none; d=google.com; s=arc-20160816; b=xSH8UIICA8gT5PLZwSN5lbukyCPS0gzsNGXByUwKb8X2nOTo2FZp4uJMdaedMhP2Jv m5UW+5ltNX7fDiAuR+CnQnpoAplWhBRC9i76pW45MP30UvSWYAdbthdcWiUy2gcxT7Rq 2cRuUtQaczYAuy8OENgEWCYYBiCQ3XttAWTNzyIv/17gbq6CrYJ1LnL3XE8tGyV7Dlf+ h9N0UviECuWza7NEO3qiWC01yO5TP8BF4dghyyvfvgYeA/VmuUtrS7Ny9+ix1vpRjaxB 9yHCfRiBiRfk3PBVEB36283Tk00r24KmrOJyqgtdXNz5W3Sn+ttwWMbMTlilOUk2lmnj jDFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CNQFYHN4ElT1qrmVuqHW9cIWfmNKRPD8Ea4kRFGrO+E=; b=K7o2Bubo16AKKabm9YLoh9mBNTbFrOpDyGWubIPUy2zJvqLH6lP09oN0Qf0WHxs3aM feC7MNS0H+EzoIVq4yIieHN6Ig71Cnqow7aKwZ/JwrXub0BUQuvsTsD9GlJDpBHnY/Iq buj0HL4apmq/f+JnmAbXV6eaACpgEH3l9uazDGdxcd+gg9G7nYFhycTc9oZNw/R9BMDD l540N2Q6CzeHH43ZBYTDl+xffr2YpNgXkFsaCtmwV2hrSfCKe8H+Mwvd1HIqX4TStnUm iDcYtMb9v3I/PFrFdso1on2l7QvaRPX9PZResAs7lQd1bG9cmXW1BUU+CB33agUpapir 8KZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZzhYQxnA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index ee2ffb034325..6a54cb79b6e2 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -12,7 +12,10 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-sha + oneOf: + - items: + - const: atmel,at91sam9g46-sha + - const: microchip,sam9x7-sha reg: maxItems: 1 From patchwork Fri Jun 23 20:30:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6031561vqr; Fri, 23 Jun 2023 13:47:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6kQ4ZeJwXocx3Xm8owWXqx7p8gdkFuvQuid1unpLzOY3EFxWdAJ+e+Zn6yVuQ2MotUcGn8 X-Received: by 2002:a05:6808:23d0:b0:3a0:b5c2:7c21 with SMTP id bq16-20020a05680823d000b003a0b5c27c21mr5398240oib.48.1687553235796; Fri, 23 Jun 2023 13:47:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553235; cv=none; d=google.com; s=arc-20160816; b=IKTMudkJZzENU3kIgLKK7W6Vg+OZMIpxJQtdrfdapl0htOOKTH37pGZE+Kepm3DCIw mTrLJ7Tl79i1tLa36KN0FD9VhGj4pSvwd6TNJsh2f1daNcUm33FaQbxYy8aCSMACzOFq KW0yAg/hUln4ud6FPNcAceElgOKAHynt22JatgCCA5JCdKVhWGNDuGdLAR/M2CK9k7mV +3ZN0yZHW3UQdhHF7ldBb23EVCoGUV/f4OEFYXHUKGTaA+L1C3RQ6qBneOiAqCL9ZMBG mhKw7MEMpgwbw0hi9fa7pJDVYeWhiC9Xg8Uy0JAxI0VMHSJDnHqw2t8TglmjqTExdg+w 10ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=J/3vBl3m1eFM5Jq5cPXwn9e1Fpr+Ryh934SdmzhlvoY=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=zdakeiHIxfeZ8JmBJH7p36WYhXG3od85vb3Emj3T3Vk1hC8ABgrakJE9ypQl+71AFE kUZyJ8ct5vyflV/CtLn7ZC6axC35dC5Nlw+rJXL2BaFHJCN91dKvEKLQNBBA5IX+i3p8 CMpTIe6MtDlDMXd/v4lvoAXuxRhg72MU1gb4gco7wGBisLKJbkm9RIdXL/V5v2qRdP1B ph84M4qWWIhskgt0A3VquUjJih7QX83qEUN57akUeckmVY2Rg4ks+q2jiXvk2xZCZ3Sl brB0ttLY6aaF1Qa1Ndvdmqgiw82SIoyrE13s0jJDT80tgWGDA8r9AeD3wX6DEruBgCaC rwwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=XfBKK5dW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml index 3d6ed24b1b00..0e71bfd32a1c 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -12,7 +12,10 @@ maintainers: properties: compatible: - const: atmel,at91sam9g46-tdes + oneOf: + - items: + - const: atmel,at91sam9g46-tdes + - const: microchip,sam9x7-tdes reg: maxItems: 1 From patchwork Fri Jun 23 20:30:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112304 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6045042vqr; Fri, 23 Jun 2023 14:16:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4FzPgYPxxErOBz1xwk14wvfbJzYQ7tTlHpN168fo3pfb+ii0UIrJytJ2KMek6LB4obsmxX X-Received: by 2002:a05:6a20:9385:b0:11f:92d2:1442 with SMTP id x5-20020a056a20938500b0011f92d21442mr24056738pzh.29.1687554977700; Fri, 23 Jun 2023 14:16:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554977; cv=none; d=google.com; s=arc-20160816; b=SBBZ4TnzjnAnQaylKFzoxjFafaKVxMfLIEV4eH7e0MXcEh931rBu87SnUKmtAlbVbW TJ8a/HAhYH2DvvrjQqgxOlUKAbI9gT6ChkLCgk/Q5T+3NjGI7y0lNbhpRKw5I58N65tV yyq8PbBKM9VVV8vmt0w8fa00UUuiqPqKNetdt0KovL7fl6Sg14go0nGRUuM4dNAtwfqG qo71mr2UXVNVJWSPZ5sMuar1VYJnQ0sHVyKrweGzCDmroM/9d14OADML1Re6FEkBBm7U drVLbtIHiVIggFf4gHti0KQfLrwMNklFe+D1f005Qb+HmJXcmI7V4TLlsdps/S6RpQ4x U7lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sQ6fmmBmj9XXijfSW4HSXFr8PIdvJz3dmp+t9RnxGXg=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=WlzwMf6dL58jF1oXBj7KrMt6t6Vw/57DzGBM6ukIVzJ4Y147fM7fhVR1VUXYP0Mnuk 76OQE4pCuTtmlSBtJmjwEsr4I3nIYfLLoR4TorkkaHpu0XXYjj4QQfPwCU1JkD7Go1l8 fZoPnZGmiSJmrDTZ/Cy/JyFOvwpmcCnwfBKgUiSqIuadr3MlalAvHDKKIrq8x3BS7jmX xbqiiFNNmPex3iw0AhMDqclijH70mKcH5VjSMncU11IvYt2BvsYJpkPX8/+u0319AyYm NYun2zBzS5GHDqh0Ai309npEKXF5mBC0EZYZL8XpLuwRsMD1n/EhDDaSf3oelTJT6Vsi 5F6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=FL9oJH1z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cm10-20020a056a00338a00b006556984fbf6si1475pfb.290.2023.06.23.14.16.05; Fri, 23 Jun 2023 14:16:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=FL9oJH1z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232806AbjFWVKz (ORCPT + 99 others); Fri, 23 Jun 2023 17:10:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232606AbjFWVKw (ORCPT ); Fri, 23 Jun 2023 17:10:52 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B174426A4; Fri, 23 Jun 2023 14:10:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687554647; x=1719090647; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BdWVxRk/sfsAxZ1mW04Nt1w0W11icyyMsW/XnDjycFE=; b=FL9oJH1zQjVoAEKmdeJhxATSf4dOAAsKYQRzJo8UyoKxhPB2YqQbWX/b t2WP44MhGAdsOkCw6oCn72e1BBVo3igdtxL7hJXOp4LdpOK55xkdoK6Sb 4VjPJYy+S1JV/E1e6l+7t7q3iw+FxcRa9F0FyomViVW09jnP4zKwtRxLe ker9ZUsy2fwl86IcBICc5T9d/xFuLQTWSETrzKOFGI6eJ4MeYj4s4sHJO dST+/5V6GESUcZepC8Oda2u9eUGI8Jp/QaThNHB4tCja0Qy1x8Jr6Ra4H ChD7/ivp3/BgwU81SLQ/8AeFIToJRAoKUyybfGXNy7aRgiyupkdaCH0CA g==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="231894496" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:10:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:39:46 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:39:18 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 17/45] dt-bindings: dmaengine: at_xdmac: add compatible with microchip,sam9x7 Date: Sat, 24 Jun 2023 02:00:28 +0530 Message-ID: <20230623203056.689705-18-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529647871503802?= X-GMAIL-MSGID: =?utf-8?q?1769529647871503802?= Add compatible for sam9x7. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/dma/atmel-xdma.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt index 510b7f25ba24..f672556ea715 100644 --- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt @@ -2,8 +2,8 @@ * XDMA Controller Required properties: -- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or - "microchip,sama7g5-dma". +- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma", + "microchip,sam9x7-dma" or "microchip,sama7g5-dma". - reg: Should contain DMA registers location and length. - interrupts: Should contain DMA interrupt. - #dma-cells: Must be <1>, used to represent the number of integer cells in From patchwork Fri Jun 23 20:30:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6031683vqr; Fri, 23 Jun 2023 13:47:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ70osHL+k/dSq0K4YLrO0FdyqHjZadlF23jhJzd2VvZ/O4hnk0Cd9Xm50mtiVd+wPUaolqV X-Received: by 2002:a62:8283:0:b0:668:8ad5:778f with SMTP id w125-20020a628283000000b006688ad5778fmr15256802pfd.17.1687553254558; Fri, 23 Jun 2023 13:47:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553254; cv=none; d=google.com; s=arc-20160816; b=sKDz1hcFifw1nFILJ+tCZ8wCIelIp6HAZdRu4FfJjiG94dKseg1rbpv1IIXtlmPPhT 9tpOVEZSaBb8pHqpm/ly50/EWFKNVWBV2DqkHxkXtEy8haTrhawG8y2mvt3MagmAPVfz 8R4yL9IcPhRof1SxOyK41Z9v0wTXtxqalOMm7Of+apeXQudcX9aOn7gZVvEj7rU4BYHO ng+ZGFoO0sC3DsSEYRP+2h2Uvjqdcm1d6yymaPjsjj4vyXX5Jnan+4pSPPWPNKTdEJbP UydkyuOe6ygt3hSkwsNOU5nX6WuJdKhJdv2pwJD7MMoOZT8VX4AzBHsy/8Zk5t5slVmU rFJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E3kpT+gm/fptALm56aNRjgyfHckrKCLIMUTTdNxaWWg=; b=MtadfAGCUVBb83hhDzqGF5H2nj78MA2FzQ+HTD8DuxsdM8jTxjGA55atCtzka2yyje 9WghlZepYzlYxQ6mMIuZpR+vNh4Xk/YIgySyTNLDD/a7MfRnEvSP92gy4+23myNOwGKu PL/SSL09b/S/3bnk6f9HrnVg/rjCZfy3YFD1ruWCAalOlF0YalG9FMrkUS1oCG/6Dwh+ zqgT1iLgPTjgXWEV+KRmNRNlj55g49zDqF7PKEK3wzJvbPNLPOUeCb/PZdRV8GZ5VTo/ rfheHxPOefw+pH7KCsjLUOfJfE0iKw3VVjEawKemeMDG+hmk2hPEFM13lEEOoVQRXVm9 qe4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="Ydzav/Ub"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml index 6adedd3ec399..440f890e209f 100644 --- a/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml @@ -24,9 +24,11 @@ properties: - atmel,sama5d4-i2c - atmel,sama5d2-i2c - microchip,sam9x60-i2c + - microchip,sam9x7-i2c - items: - const: microchip,sama7g5-i2c - const: microchip,sam9x60-i2c + - const: microchip,sam9x7-i2c reg: maxItems: 1 @@ -84,6 +86,7 @@ allOf: - atmel,sama5d4-i2c - atmel,sama5d2-i2c - microchip,sam9x60-i2c + - microchip,sam9x7-i2c - microchip,sama7g5-i2c then: properties: From patchwork Fri Jun 23 20:30:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6045377vqr; Fri, 23 Jun 2023 14:17:02 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ51BdBFWdn4vA9LoiYTHekohabhs8+W/NhtXW5IsKhKNBXdi3zkfpWWucx0Kzxd0XjROUEA X-Received: by 2002:a05:6a00:2d82:b0:668:715a:6fcd with SMTP id fb2-20020a056a002d8200b00668715a6fcdmr14761828pfb.5.1687555021718; Fri, 23 Jun 2023 14:17:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687555021; cv=none; d=google.com; s=arc-20160816; b=hXpLIfihdhab/Ys6RgFGWhRLHzh8r2lEMwApYtFVqdzw0OtJFY/+2pznGm5oFMocdX vbTVh0WUP/E0ujDQGcKdSDwnpPh/x96OBqUrMGRZs+JjbdJk2KlSC8CCp5LZIJqOHpXo NHikq00peKHhxBLnf/RUBhdYIA64efsNn6ktdf3ClOXVVY2xa/8PnKO9h3z08Viv2Y4k iLnyMC2skyyr/ysBbmFm0xFYEMRC8HfmDYhbl5jx3bVCKLJ/w+BGamZQOMMZ/E6UZ5BJ NS6Dpv/vi1DSI+tQjYVFmwSoRcsN8LlgdTxTf0PGobdeNrOTpdKmG7eOREHWct9LCf5Y JGIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gdGAGuWG1UpOggsa6kHXgeB1+H77wBixJw5labmkIhE=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=ZsBrT0baUuoYXffFtWUzEqPsXTttK5GG0yvktZ//qcpSoB4jMnfUeOhCy7DC62+VrS urwblObsJy/zqD+Olkk0ll2UfKnwCSwekhJGqa14axeZWPD8h4dWJvkM74bGqxKRNSJn uDWF/dSIkaEvdMABoH3Q5v+xtudw+lf/6X85ME/UAzgLaBGPSG2jyDmdbAsxm+WFBFUR ltmWjPronYjhGjqt9AIAiGa6SJbIkC6X7nhHZvTUngzqPi0ICcESwChrCg2jwnUVc2JW Xbh+QHSxvPQUqp4NAWHY+WWLoP4Omu0odN8OjsnkO3krV8pojkwNa6Dm/oQxhEaDrdTK N7IQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="wuTK3O/R"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v9-20020a056a00148900b0066243798ac3si4417pfu.278.2023.06.23.14.16.46; Fri, 23 Jun 2023 14:17:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="wuTK3O/R"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232810AbjFWVLb (ORCPT + 99 others); Fri, 23 Jun 2023 17:11:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbjFWVLV (ORCPT ); Fri, 23 Jun 2023 17:11:21 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8962940; Fri, 23 Jun 2023 14:11:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687554670; x=1719090670; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hV1FRXb3qLJvqZh1S3u4vHSAls8N5oVFTQpst8jvzkw=; b=wuTK3O/R83uIsLK5w59BvgTtjUwzRTeClwFx3oUMDSR/oZ0RNZQ8zJvZ GrNa6EautS+5Ncuk08RHYGP7NWvfkuO1cB/0q/nLZ/u0xowLNqLR5S9b7 CDDfzxlItMwNy9rX0DHdYgdUxyT/42whhTf2zPp41DtAK0pEByZEmqZH6 e0GiPnetVpT46TJfT6h4kpeB6DqxTbDRdmMqwMzLbKt2UGKpiCaghYkrb PDAEhm+L0bwxvveQrGuy0apNMW4tUTymQsSTeHbSipMbd55EHmg8reAA0 13kgCz/oc3FHJqqXFKaFJ5ZrYOL8rQPyOt67mkwnjEMiNAUt+MfSdhkwz A==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="231894633" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:11:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:40:42 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:40:15 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 19/45] dt-bindings: mfd: at91: Add SAM9X7 compatible string Date: Sat, 24 Jun 2023 02:00:30 +0530 Message-ID: <20230623203056.689705-20-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529694296339823?= X-GMAIL-MSGID: =?utf-8?q?1769529694296339823?= Document sam9x7 DT for flexcom. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mfd/atmel-flexcom.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 9d837535637b..449e0af93a13 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -5,7 +5,7 @@ controller and an USART. Only one function can be used at a time and is chosen at boot time according to the device tree. Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" +- compatible: Should be "atmel,sama5d2-flexcom" or "microchip,sam9x7-flexcom" - reg: Should be the offset/length value for Flexcom dedicated I/O registers (without USART, TWI or SPI registers). - clocks: Should be the Flexcom peripheral clock from PMC. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt index e8c525569f10..2cc39524af8c 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt @@ -6,6 +6,7 @@ Required properties: - compatible: Should be one of the following: "atmel,at91sam9260-gpbr", "syscon" "microchip,sam9x60-gpbr", "syscon" + "microchip,sam9x7-gpbr", "syscon" - reg: contains offset/length value of the GPBR memory region. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mfd/atmel-matrix.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt index 89d05c64fb01..75378839fc7f 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt @@ -14,6 +14,7 @@ Required properties: "atmel,at91sam9x5-matrix", "syscon" "atmel,sama5d3-matrix", "syscon" "microchip,sam9x60-matrix", "syscon" + "microchip,sam9x7-matrix", "syscon" - reg: Contains offset/length value of the Bus Matrix memory region. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mfd/atmel-smc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt index 5696d9fcb5dc..1eb2606820a5 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-smc.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt @@ -10,6 +10,7 @@ Required properties: "atmel,sama5d3-smc", "syscon" "atmel,sama5d2-smc", "syscon" "microchip,sam9x60-smc", "syscon" + "microchip,sam9x7-smc", "syscon" - reg: Contains offset/length value of the SMC memory region. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..67c1227a01bd 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length From patchwork Fri Jun 23 20:30:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112335 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6055450vqr; Fri, 23 Jun 2023 14:42:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4McLVL44o2Rwvlq+A4wJRSlc1+PzEJXhjqCVlyRqBJM7XSWywavpvb/kaSp1bdXRULF9UB X-Received: by 2002:a17:90a:eb18:b0:25e:c876:26e9 with SMTP id j24-20020a17090aeb1800b0025ec87626e9mr28006682pjz.22.1687556544862; Fri, 23 Jun 2023 14:42:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687556544; cv=none; d=google.com; s=arc-20160816; b=gBQkj3xwYjNY4W7T2D4gTkRPU9nnpqciwnEWcsYeoZKF+bHMVA6lrcelSRyhLhcOyq N3X97qFbg2pUniVmhpVt6dwHjYZ0cuyid48eMNoChsl51H40XjlLo+ohF0HWQWQC8CjY AiXVTZ3EX4a1aeL+EBKTKXOICpIR4kZYDRhTPNRrOW11DYSw5TOxbpHWFz5zvXGuzJgn 6ww6WgAGt5cIDFQ41u2B/hWDbUwc07KWOCj6o3I/uGoL5oo79E2VlLGc96RoV9OBenzu v1Gq+Z9bfGG9/jrUNZ+abMt0yLYDwu8tk19A8BCUvmrDOirz4EQBH0LKawHk+cAcvSL/ dwmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RphkbsnotHlTokWDfdbH2uQ6u3n6sinOkmCjsu5ja8E=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=QeiE1ikglPWKejv9vcShEG8ixNwXcPDqrjcHeBvz5MJa9bsUyPyKQvacy9XTJEi0bN ql+28k+R5GjQuUrM2WAYu2vUl+qdKDqfk+gloL/i59lPgHWebWmhQkNgQLosKMflJXlr 3yvOIna0atXg03yefdvdMmwH68R0QhQgQPi+/AFUBejy9jFigwdmb5y3tK0+31DaLtFB XYVmAufHyqki9U2AdMwaN3So0ABY4MWIb0lllzX11Yf1ilwmjrmZJGx9G0wvXBLpkNSH tBUJXux07dAS9NHYBadZVVcdUc3iR9Lj15pwKvbOXHfzzaJKk16WPJ13sLo2beFYL57q CXKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=CxErQ1qJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mmc/sdhci-atmel.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt index 69edfd4d3922..b8df78fbc00f 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-atmel.txt @@ -5,11 +5,13 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the sdhci-of-at91 driver. Required properties: -- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci". +- compatible: Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci" + or "microchip,sam9x7-sdhci" - clocks: Phandlers to the clocks. - clock-names: Must be "hclock", "multclk", "baseclk" for "atmel,sama5d2-sdhci". Must be "hclock", "multclk" for "microchip,sam9x60-sdhci". + Must be "hclock", "multclk" for "microchip,sam9x7-sdhci". Optional properties: - assigned-clocks: The same with "multclk". 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w191-20020a6382c8000000b00540107fc033si210662pgd.282.2023.06.23.13.53.06; Fri, 23 Jun 2023 13:53:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kNfdiMHc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232672AbjFWUqd (ORCPT + 99 others); Fri, 23 Jun 2023 16:46:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232484AbjFWUqN (ORCPT ); Fri, 23 Jun 2023 16:46:13 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AFE930FC; Fri, 23 Jun 2023 13:44:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687553093; x=1719089093; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x1O902oFsQeoK9oVLCWEt+1yrZVqoxGg87zjZmWY034=; b=kNfdiMHcoaAdTn6nH+86LE+oBrGnMseVtLOhFXU6Kji/VqEpY4D+ogIK U4QclNu9U7Q/UfyOjYD28OMp3ceyMtbq4J017Oa7r+XgObdhz6bmyNnQP GnRMvrAN9fQzHdr/W47OAoQ3tJVOX8Mv+2Bz+Ce+cR8VbG3jEPj3H5F27 ZQAg7bGPyRRN8Rt44EBSDp2ftIMyRsi1XQADV8oOqZj8PFGxWeskGyS2d F24abUDrXnCLrvBE604PUJ2Lj84nqtYTyqaiyaF8EAyPnEC36rxnjqoHS UAWSRmZpaJgZgk3MtMRb+3stouwIfSQRR61zP2SJJnq89sI2MLqwIhROa Q==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="217419442" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:43:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:43:37 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:43:08 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 25/45] dt-bindings: atmel-nand: add microchip,sam9x7-pmecc Date: Sat, 24 Jun 2023 02:00:36 +0530 Message-ID: <20230623203056.689705-26-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769528202785828531?= X-GMAIL-MSGID: =?utf-8?q?1769528202785828531?= Add microchip,sam9x7-pmecc to DT bindings documentation. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index 50645828ac20..9c9dfab38fdf 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -56,6 +56,7 @@ Required properties: "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" "microchip,sam9x60-pmecc" + "microchip,sam9x7-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j12-20020a170903024c00b001b3e02ba991si16411plh.242.2023.06.23.13.53.40; Fri, 23 Jun 2023 13:53:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=TigqLGeM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232710AbjFWUrF (ORCPT + 99 others); Fri, 23 Jun 2023 16:47:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232666AbjFWUqc (ORCPT ); Fri, 23 Jun 2023 16:46:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71B4E3AAE; Fri, 23 Jun 2023 13:45:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687553120; x=1719089120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LDWBjvnTTsLcekUwxDRyJLu3Qkm1EGGjQgrSvTcjXhI=; b=TigqLGeMvqaGTQAz6AjR80magC8Z8Ucksi95l8I84ONonbyc1fQ25m1+ 98/Q2yjGbocbgpxs7Id3JQMf805+F17OKi1bdUsOPzPSnzQKGvuuQsBzA Q2pHAgnv86EoFXOzzfWRqG7SUkYY6OMriw7DXS+JEWWGCVdukNp+AboJY arfCFsjnth9RNDdHxkpToCnVOk0cXDcZNL8OlUDPnHIt1WCiMFQ1k7Fg2 7WiGKChasTrR/s8bDalVuCgdHavARxgfOG5PQc88Rt7Q3+/oRBgIhB3xr xadaLba3L4TlQEQX1KJOE++NEfe7E1EAQXdK6b7x35I6WYGdWm6twwiAF A==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="217419517" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:44:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:44:07 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:43:38 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 26/45] dt-bindings: pinctrl: at91: add bindings for SAM9X7 Date: Sat, 24 Jun 2023 02:00:37 +0530 Message-ID: <20230623203056.689705-27-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769528237517486019?= X-GMAIL-MSGID: =?utf-8?q?1769528237517486019?= Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b5d..5a3be10dcbfb 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -119,7 +120,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or - "microchip,sam9x60-gpio" + "microchip,sam9x60-gpio" or "microchip,sam9x7-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller From patchwork Fri Jun 23 20:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112348 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6070652vqr; Fri, 23 Jun 2023 15:18:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7oBWFgMmhpZZvItM+tp+J38Bsgpr3khZMfqERkWGqUYHzkLNyzt2lT981Zn3wrTqqsPmMf X-Received: by 2002:a17:90a:9ae:b0:25e:a643:adeb with SMTP id 43-20020a17090a09ae00b0025ea643adebmr21137285pjo.39.1687558694284; Fri, 23 Jun 2023 15:18:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687558694; cv=none; d=google.com; s=arc-20160816; b=bhPyh2XtXJ2usYGkgLLFWCAn7S2gN9RaUYGSPyRSKhLNvjRSpdU9ZlZ1sUS/+ArSpj yVg83fzxsfxDT7pW1FEzeeU4RBOgds5/h3fvRt5ErAcR1dN4X8gZnvbYTpGZW3riJdYE lb7FUMRbVIlBcc1FyUZLnsG5TA1tqUQ4prmzVAJwxeaEV2iZOAGE//unqqP1zk1jpyqb WP1elCCkHsYo8ay1J+79fh6WDUNOj/itwX4mV4hPmw7JNYjHWd0O5CsJWXGUyMGd8Q6z 1Gyjq6lpoLVDlrUI8nEMcfUrPI8HGwyKaZDUMVu3IxHabMh10bqQ37FhL6VFqH9PKkf+ WqDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dcfo35AadMxl7bBzGyEmWXAW3eOrr2aGjW5NlhyleVE=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=WdE8ZBIPe66r86pM6gF7vM1JJJxT1qV5/t0rMjUaQdqfZHNc68jM4ek6L08b+zuoYh ZnjEjqlrJftvTniWK27bH0mHZtzgEKfHCwbancxER8qzqYwYSLzwS66N4aO4UiZQfynw A9ivO1VziSDMGLEvj6FHg9ZRkiJ11zOU65fvlzvKdrNU42lvduS/of2L+oBgFjpIB1vA 2J+zLG0JGY6fiwaEB56y8xV/ROn3RPKj5P8WWP2eWSWA3gqTIhJ0MuCjA7B2siDioAYc m9kA5wqjwubrCFPzmdbzfnXl4F2uNyA3waCdwc7CwKE9CNtwfH6jFxDrtvkKV+AAtC52 RyZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=rfT4xqto; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml index 3ce45456d867..7e4dbf5e22b4 100644 --- a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +++ b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml @@ -17,6 +17,7 @@ properties: - enum: - atmel,at91sam9g45-trng - microchip,sam9x60-trng + - microchip,sam9x7-trng - items: - enum: - microchip,sama7g5-trng From patchwork Fri Jun 23 20:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6034651vqr; Fri, 23 Jun 2023 13:54:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6CP+B5p1+zWAnfnMsj/2GtxqtB7Ih9aFNNaowxyDpjv4pdUxier2KFqIX6pGwObKYhCkHo X-Received: by 2002:a17:90b:250:b0:25b:f764:580a with SMTP id fz16-20020a17090b025000b0025bf764580amr21399100pjb.12.1687553694037; Fri, 23 Jun 2023 13:54:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553694; cv=none; d=google.com; s=arc-20160816; b=t1SWRtYhaiWFt70ZwIQjc5cAoAv6LROe5x/R82uVwvTx5EzgTBk21WByEyzrL8mmiO FiK4FZZDkK9Qiqqc1qlhfe8KnBwk9XJ+fEdmxWkgfVFiis44UNX3T9mZ7ybqeZHS1tzx 8hfsRArQJ0Y928khhPzdFEMUGMqcCeeTOMhiYezpqOqGqbxKk/ybgmjfg6SeMVkgrY4v Lo2ecQ0+LAjvyWM1C6ZfmUFTCUvzcNDtzosRt7kFFU4RZFabLH/eHULeVImVZmpOOwae w3cFNwcBa4eUUk5xPpqmrtFF+IoKjCHsHPgYkRRR4Y4UVv711Tbd5pBHaXVz1vBZzhdJ TLwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6PcgTBwlqwHFgIv41GfrviJ1jt3WH8p8Df7AtCRjjLM=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=k/GunqcKskbw8nNODu7EYu14rAGOyBfDOvvXq9H7Mys0Iii0ze1Ig/kym6a9gTFMXX yyTAoByDuoXOICem/WHQhVMUjAMHWDF4//SBjMFb0FSYs3PrFofFVfQjKwSJPiSmERsR X9QNqRYgf+jAHyDpwdU7/18Rf+J7T6w0YPNlB2UpYY1nQ/0NCEsz7eP9At/8r7Yc3knS UT3hizzO1uwD+uDfSSDwGKDKf7974fjzmyc3gzoHAOr3dx93ugDccgBgDz/lvo5MfZsQ FCcI4EdN4F8LyclCxV3Wh6e1PrAEcFLDRpBsmZAvIKPjrv5jsePzdmQg6bchxx+C8vlH Rk8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kqyOkM4v; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index 4d2bef15fb7a..e15872bbdd7e 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -20,6 +20,7 @@ properties: - atmel,sama5d4-rtc - atmel,sama5d2-rtc - microchip,sam9x60-rtc + - microchip,sam9x7-rtc - microchip,sama7g5-rtc reg: From patchwork Fri Jun 23 20:30:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6033733vqr; Fri, 23 Jun 2023 13:52:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4wYsLPOqh5Bn2o7xXvfkmRTbKyswN3crzxVRC39yF/w7MQYZ5hqY1cmvT4f+tz2vIO52IR X-Received: by 2002:a05:6a00:198f:b0:662:5146:c77a with SMTP id d15-20020a056a00198f00b006625146c77amr28862439pfl.31.1687553571534; Fri, 23 Jun 2023 13:52:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553571; cv=none; d=google.com; s=arc-20160816; b=zJvYqDqnBZTDh5hrT7rHZAoX1iyIrzQblaTFbjiSuISvmebxC9Hvt5TTkX8JTWRl+k LqmhfIMNIsbRTfdzD2oLXXGzg+Pai74CLrNeaQxvFi7PaPMz7PAjlsB8a7qbIhcymOGM RVTtK3gIVeyzdnL0gmKGepO5lVsQlwJKXI8gjhwj+fh9sI1JLHR+4LIdsVQOxURbxBji vaZ5vTwMBVk1Z52vff+g+MsLozNCUDiHMGufNZ6FVq6m77QWTD86dfU8+fmIG0NbKSwD MqoDvHNfWJfbsAr2D6hxJ0miuesjL+Ax00yvYAZ75hAARH6sUOYUT2WkguxgMlDwJNbP 0kFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kDRyFQI8iCKLe3AtFXiL7ZPEyxMdbdraeoyyWVH4lgo=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=E5ATKoCqcjMWiFwXvD9QwgxNOFCvY++VtFvyYgFH+QYSP9mEeaD2Cf/nMT/EJnLtZn vK4+W4ZFBqV9PeMbRk7YFeINvvKAebS6tzcAKGlPZudZxcMbSUmVE94xFnAgwxy7YxVc dgUJRi/QxiKPeQK2vwkKfySIeg3jzLp2Q3THA2YFp39F9fi4A1zfMx8a75ynLFXJhl6R 8Aw4BVY0roU86pxKIg3n0bZb2iW/GMXdzhP97ftW2dCrhM46hQXHhEl9tz8vQxtKVsuB 8mraxPGsIuCtE/HSXgNq+rjY7FFKJrW9eLL7zIJRw4RTWvs5pwerrlPNea9ZOi9bEEpU R1Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=BWuM9EgO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index b80b85c394ac..2d5cce1c1331 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -20,6 +20,7 @@ properties: - const: atmel,at91sam9260-rtt - items: - const: microchip,sam9x60-rtt + - const: microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt From patchwork Fri Jun 23 20:30:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6033663vqr; Fri, 23 Jun 2023 13:52:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5Dg/UbUhrbMz+AZVfxqP7QFRvmNquG8bVWxBnqgG9OuHAmB46Y4OY/jhqOlwFGP67k2/ak X-Received: by 2002:a05:6870:4396:b0:1a9:b65a:9628 with SMTP id r22-20020a056870439600b001a9b65a9628mr17930854oah.15.1687553561414; Fri, 23 Jun 2023 13:52:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553561; cv=none; d=google.com; s=arc-20160816; b=aLWY/OtVesaIvNsS24ZFLFnB1SfGsCkh7c5y11RoXr6JcNK1i7CXqfdlUWApU8Rhff hDvalNnjkb1RDbb9oC+DOJxryAm3sAw9MksldaNTSGnOAegGLdpI6fNX5Y8JH6FM7QuX j3D4c6PjyTf3z3EPWzPblY2gisrrEj6IMumwP3N/qOQ1lKatu0DsHBHyxrFy/fLMP155 iRISgd31+BYJAJ5ZQOhxlhLKohWU5zu1Oub1sh5tx9GdUUxJQRKDNJIuiGSJErLgZWae ngwXubJIh4AvwzD3CBQwKKt1E6F08ngUCeOHVI4f4o8mQgY0WSrT6mxb4fS49q3bOiSP ZSQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AkFEa2NOEkT0Vk1LJakYqBAPRHnGgQ84BkbLavRxlW4=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=U5lIIkfMqqsgpPlxtWoFVrHdsteheRftzmZltPbxM477IZewH9HIu6/4GIAatISc7K qxM1UjfupYE5zwDefec80fXusIJSLS6feKH/5HcUYKFmzOtgvgzZ962cs1hZcX6DEQBA sb5GW6YK2jRPNEEvMyS770ICXt5o4ODFxEsHcr+E5OKAHGdEAMeWpl6lAKBTmOCQNl4B JFP6XkSDpown38RdH2VO/dryHTmy2btx3TB72f+6lRDZlFI0nn2X0RRjuF7XBFjrM8Tf LsV0l2RLuVeFQ1ga/zpT/FNSk/8vND/3Xu+Jz6jt8r1XkQiD81bU51xBtzgsO+iuFdo4 quug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=uzZ9GPq+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 30b2131b5860..d836224f99c6 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -17,6 +17,7 @@ properties: - atmel,at91rm9200-usart - atmel,at91sam9260-usart - microchip,sam9x60-usart + - microchip,sam9x7-usart - items: - const: atmel,at91rm9200-dbgu - const: atmel,at91rm9200-usart @@ -26,6 +27,8 @@ properties: - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart + - const: microchip,sam9x7-dbgu + - const: microchip,sam9x7-usart - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart From patchwork Fri Jun 23 20:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6033688vqr; Fri, 23 Jun 2023 13:52:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7txtsN4tHGZq83IaAVq2yVxQBoPVAM49RjX64eg1QTgKN4AmD35ATooYDKlRd64rzDQChp X-Received: by 2002:a17:903:2341:b0:1b6:b703:3703 with SMTP id c1-20020a170903234100b001b6b7033703mr198217plh.37.1687553564574; Fri, 23 Jun 2023 13:52:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687553564; cv=none; d=google.com; s=arc-20160816; b=Q8pnWHUo0wEUK1KbroTAnVErmVX72oNrhbFqTeWyNfbC+TeRsXj1LTvrFta6CsmSEI idUlW45JpH469YALZmvHUIZAxsjB4iL2J/XUImn5OUgzkRjwEhZpYfAmchzv7e6x5B6a lXHFae/f9omRxzE4QZR0Gg1jVUsUkwYsPhZz2IYXVGG9FsE8jgyDo+OrdjUzvh+VwSuE NJ100qU/WHZIYsonrFE5d6hj7UxfVJoJyc28NvydZMUtmX3DrEjrEno6wYUYp0/RqQsC vjIOXhYeIk9zmGOyKwye+cmiPyBXP5s6zOEYusv7L/P+OvslbVtPRE9mjo+4RvoXFRgI g/KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dp/7qkmKqDGJ0a01Z6SqS5xe5W70Wp9JaBVBZMfFoKQ=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=mjr6pWzaJZUcc4q8e3xYKdxKoDslOytGp9aAYg7qvgCozX2Zv6Jcby7cmngfFSZ1LV F1XKez+pOaMdJiI6NychGyBFbPsPnqTZT71iZ7xVhWKItZ3n8MnphEn72P3QvQoNVe9t xCcdAyRsqPnNg3CH+lgGKaIIObTFO5sOzXFucwH/7HdS21WzQD1yo5ae+2VR0iIzuI8R kqcuJEWRZHmILCXyhPqr+HatsaAl86RHEsConzev2kjUBz/8O1TQTT0WHt+YoSDsUvSW bN5yGiw3S1M54KwOkVg/BssMFQr/Kj0pDWOYhNbUUEY0hkWZ0Gt2tga+K0NAQ4kg9bYU Os6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hiKJU7fk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/sound/atmel,sama5d2-classd.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml index 43d04702ac2d..d53addbcd41b 100644 --- a/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml +++ b/Documentation/devicetree/bindings/sound/atmel,sama5d2-classd.yaml @@ -18,7 +18,10 @@ description: properties: compatible: - const: atmel,sama5d2-classd + oneOf: + - items: + - const: atmel,sama5d2-classd + - const: microchip,sam9x7-classd reg: maxItems: 1 From patchwork Fri Jun 23 20:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112344 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6058759vqr; Fri, 23 Jun 2023 14:51:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7+B+XQgFOT+OMAYzmRd/GnZDuQcZK2yzbPG8n0yO9VZ/YOdck5Ne9WEwGDU8NVlalVAFTt X-Received: by 2002:a05:6a21:1518:b0:10d:3ff2:452b with SMTP id nq24-20020a056a21151800b0010d3ff2452bmr17595285pzb.18.1687557106129; Fri, 23 Jun 2023 14:51:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687557106; cv=none; d=google.com; s=arc-20160816; b=nLayDHUGnH0G9HtkHsGHsTLxIrbiUnb4ia0SXvj4vdmOU0IvqpjCWjeHqZr81mh9tz tllDzCCd4fKBVT65CR4k3QjEVFtFlaM+0Lp0KGB93YP1iWBZoqHsW2Jn1MdS3JhPZflv RrLQ24o1Cdn559oBTp8V6GdYCHIigG+SoEoWKDewQRTtLMU4aoehgazwgmpAeAyDxsrK wJmHtqEdaugpacvL1KW0GAg8ooW2Gs2ZqApjeZsijmJmu4OGcEA/WTv0keoaXnkZsGbR 8KF6AmSDHTr1pgOxdXwIU/0o+wFRn7Qn9DzQk0N0mwm7+LmWLrzBxkE3/bHLAvq31m3x I54w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WyLmObc+GNSpbgLyLdM+iZiKET47P16EaTyb2ERzSqs=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=rx31YgQsOdcUs7F8QLLHOnB5PpuhbPwNHbkp6lVioX57kVb6AhIC74yuFjS4deLylb d4+ibOO+TnYhlR7rlTTiUiY5vOYcg4QDg82viUVe75C/b4JyaHkPzb8lE37InDsDqvd2 pKDw51JDzT6B8YvuO1XwDp4viBr1CNnxzGWsRRt7k5OKrxfsUrn+P8ZpBfS07QbHP1DV bnbJx3alGvIo+WSKl+zFI40dgoC5Fb7QjkP28+YDRQql5PeIHSNB2PT5nvzFsvxnH8Ql ZJZla9BMqw2mhJ/KRkuKcRp7z5Apin1KcO5pIS1qFyxiVdLeegDFsETQ//jnWUIP2uk1 Zqlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=ZEypV6wv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 6c57dd6c3a36..bdc42eeacba4 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -19,6 +19,7 @@ properties: - const: atmel,at91rm9200-spi - items: - const: microchip,sam9x60-spi + - const: microchip,sam9x7-spi - const: atmel,at91rm9200-spi reg: From patchwork Fri Jun 23 20:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112291 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6036833vqr; Fri, 23 Jun 2023 14:00:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Aa1gDpb1yukuJYBGeNmNwnyNpQ9Ws14PRAn1JeY9Yhux69YfQVyKvG9rMOkNJGqZIhxgj X-Received: by 2002:a17:903:2591:b0:1b3:e6ba:3539 with SMTP id jb17-20020a170903259100b001b3e6ba3539mr160063plb.51.1687554026948; Fri, 23 Jun 2023 14:00:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554026; cv=none; d=google.com; s=arc-20160816; b=LmSZxr0YGaXX9Pbe4IosumhEv/c5MyS/gUpmAgdTYuv++E5KW5VquE1LdLvSyJFp// prHB/OCsDZFfnhLyd8M0/gqmf/q5wwCuFvrVCCHGss0C7Q8xaG6xRFhjvoz9Rrc1fLh4 UwtxdIjGAvZvKFxwRX1KLzU3NOA4i2m/8TggJNblnJKrOLIvcJs1aLbMAI3PbpIa8fnt N5qJNcHqXvwiAD4siy7FWIgDzDvNGqVNuzEgoQjkL5InuUWw5Id+w3eidMFUd41cK7sE Oim59V14xDLL83LrkT71Aogkh6UDVBGnwzKuL4gVO83MNlhT5HXRPooIHbWiP2KtA/LG Hbvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uPmmy6zMOpM5y1qTYPYd1GerWlcZRbijvoVjR16AwsQ=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=rXLvN1fhTwZcy4494BPkycH5mOGQ4m5yg/CTHifdtBSgQ/KV3O15G/R9gwhT53nRqP KCyilNr0d9qCP1l3DlbiRV8H91NgjgbDHK0CyCeCAamYWzReOOil3qpLGa58X/TO7BmT GcdeMYyzDn0msedWbl/hBXNVQFDBT1ZjbjC3LgfIkXOVkRXkYeYfUsWjtIqg7RaJ6b5H AbPt+2BcP2OCy6V67np+aK12UPHgP9QBkdiIyB1yYoAOxhsS9H1SMIgUv2ke8skxpch/ 8P1yYg0wtbGc3ed3BA5Q4Ft3gN80UGSBegZtY7iPnz/9AZhGUk+guOq9PFelvwBB8mz9 3zQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=c52N0ZPz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/atmel-usb.txt | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 12183ef47ee4..6359af0123bf 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -3,8 +3,8 @@ Atmel SOC USB controllers OHCI Required properties: - - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers - used in host mode. + - compatible: Should be "atmel,at91rm9200-ohci" or "microchip,sam9x7-ohci" + for USB controllers used in host mode. - reg: Address and length of the register set for the device - interrupts: Should contain ohci interrupt - clocks: Should reference the peripheral, host and system clocks @@ -30,8 +30,8 @@ usb0: ohci@500000 { EHCI Required properties: - - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers - used in host mode. + - compatible: Should be "atmel,at91sam9g45-ehci" or "microchip,sam9x7-ehci" + for USB controllers used in host mode. - reg: Address and length of the register set for the device - interrupts: Should contain ehci interrupt - clocks: Should reference the peripheral and the UTMI clocks @@ -87,6 +87,7 @@ Required properties: "atmel,at91sam9g45-udc" "atmel,sama5d3-udc" "microchip,sam9x60-udc" + "microchip,sam9x7-udc" "microchip,lan9662-udc" For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc" is required. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml index 816f85ee2c77..216e64dfddb2 100644 --- a/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml @@ -17,6 +17,7 @@ properties: enum: - atmel,sama5d4-wdt - microchip,sam9x60-wdt + - microchip,sam9x7-wdt - microchip,sama7g5-wdt reg: From patchwork Fri Jun 23 20:30:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6065018vqr; Fri, 23 Jun 2023 15:05:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7RM/P+1ahnWRMF3QxKlBry2Mk6lO8I3g51M1zDHzkEoqjqEySgGLxC90OG8+Q0K2LfuQNd X-Received: by 2002:a17:90a:fe0d:b0:256:4217:b955 with SMTP id ck13-20020a17090afe0d00b002564217b955mr20120353pjb.35.1687557951415; Fri, 23 Jun 2023 15:05:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687557951; cv=none; d=google.com; s=arc-20160816; b=ZYWeazjrsLT3m05G73H+H5N09JWJkUb0+//4+oenT4saxw/qT91GFXly0isQJgUAdN 7HydrSdbnjxB7VNNz7spzoRfbU+QKpB450KBlTsS7AJPD+Fv7pA8tE5iP14E/LTGIVzI c0NDTvI8EUYDpIWf6tA8Y3XLEryfhgiFKtWtFS76sT65ZjP9/D7j55m0Lo87sjSps1he nfWvSF2GTFURjnN7C/wyqUQ/AXBzT0q7StK92d5uGM54VD35nCcQvPmGojvG/m05Xkwh yPH8pYKEjLojamu+Lygj8uCzApWTjo1wRuBwqXL3zKSPOrTPEYB3hTCq2rGt8RiH+vLP XVrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6P6LjpHEU046FzAwDyga8EzjOfOF+1JAPWb0PCf2YLE=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=j2VZv6hj8Fi5PcdIlJfFTC4QPpgg2krQL80s5uQ/C1EVYPoWXdbnFJU90wulik/yNV n3u3QRzW/LGx2NACmQaiClDHdJ/DMns4Rg4QKtLg3O9Nxw5Vt+j5uhGGakzL6iaOa9bI zokasQ2Du2xhi7QoEods5A0wlr6CiKcmYktzdur9wMh5rSXxZ9tu4epchoHI+wRRMNUO oXWaIfl7RhKIzxvjz9p9Q24cnRYSzNMK0xKeGu3Fi8xu3fiEHS/1xicZLsWxOVm9HTxK siRdf5zRPjiuIRaW2Z2Q/RylHr7c8VtPRQvdHXiE/JCCVJb+nmDhLN3ZrwMfVJDvB0vu CxJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=aWsEtirV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 7079d44bf3ba..2c267a66a3ea 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60", "sam9x7" - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It should be 3. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n4-20020a170903110400b001b046acc853si32869plh.589.2023.06.23.14.31.07; Fri, 23 Jun 2023 14:31:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nziMo7j8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232976AbjFWVV3 (ORCPT + 99 others); Fri, 23 Jun 2023 17:21:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232970AbjFWVVM (ORCPT ); Fri, 23 Jun 2023 17:21:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB922941; Fri, 23 Jun 2023 14:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687555191; x=1719091191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PHxen6A+fLf2h8M4bobBHyCXVt66GtrAftr+1jn49qI=; b=nziMo7j8GiHnUprTs3EvEY7Uk8xrQqlDunhb9o/T0DHWyJjxqnLwk5Wx 98Xc+Eh/tHzuA/vx6ApmDeZmwQdAsyCUVtOxMoms4JQL8f2yx928SbbIW hRrCQlh/FyRmANOSSSw7q/9IKPbf5nEuxLFiLSGCEgH/W/gTHWNdHAqix 8bmLAvxX/RpxGTZ788w9/qrU6wxBttZr8SFcTK9R4zykzasNZKIAR3x/+ O666u+3+wAu+GmOX7xMRNERMBGOcg67gR5lWBCycc0z6z2OiajDgU6Ntu nO+1VtWP5a2EFDINQBPqcrWe7CRIalSh97Lbj6PPDF7ZkTC40ssSMEBGM g==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221706414" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:19:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:49:00 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:48:30 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 36/45] clk: at91: sam9x7: add sam9x7 pmc driver Date: Sat, 24 Jun 2023 02:00:47 +0530 Message-ID: <20230623203056.689705-37-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769530600374454388?= X-GMAIL-MSGID: =?utf-8?q?1769530600374454388?= Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 942 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 943 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..292ae51be568 --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,942 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 32000000, .max = 266666667 }, + .divisors = { 1, 2, 4, 3, 5}, + .have_div3_pres = 1, +}; + +static const struct clk_master_layout sam9x7_master_layout = { + .mask = 0x373, + .pres_shift = 4, + .offset = 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] = { + { .min = 375000000, .max = 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] = { + { .min = 400000000, .max = 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] = { + { .min = 400000000, .max = 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] = { + { .min = 375000000, .max = 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] = { + { .min = 732421, .max = 800000000 }, +}; + +static const struct clk_range upll_outputs[] = { + { .min = 300000000, .max = 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] = { + { .min = 10000000, .max = 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] = { + { .min = 10000000, .max = 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] = { + { .min = 366210, .max = 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(plla_outputs), + .output = plla_outputs, + .core_output = plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(upll_outputs), + .output = upll_outputs, + .core_output = upll_core_outputs, + .upll = true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(lvdspll_outputs), + .output = lvdspll_outputs, + .core_output = lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(audiopll_outputs), + .output = audiopll_outputs, + .core_output = audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics = { + .input = { .min = 20000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(plladiv2_outputs), + .output = plladiv2_outputs, + .core_output = plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, + .div2 = 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, + .div2 = 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout = { + .div_mask = GENMASK(19, 12), + .endiv_mask = BIT(30), + .div_shift = 12, + .endiv_shift = 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: true if clock is critical and cannot be disabled + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][PLL_ID_MAX] = { + [PLL_ID_PLLA] = { + { + .n = "plla_fracck", + .p = "mainck", + .l = &plla_frac_layout, + .t = PLL_TYPE_FRAC, + /* + * This feeds plla_divpmcck which feeds CPU. It should + * not be disabled. + */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c = &plla_characteristics, + }, + + { + .n = "plla_divpmcck", + .p = "plla_fracck", + .l = &pll_divpmc_layout, + .t = PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid = PMC_PLLACK, + .c = &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] = { + { + .n = "upll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .t = PLL_TYPE_FRAC, + .f = CLK_SET_RATE_GATE, + .c = &upll_characteristics, + }, + + { + .n = "upll_divpmcck", + .p = "upll_fracck", + .l = &pll_divpmc_layout, + .t = PLL_TYPE_DIV, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid = PMC_UTMI, + .c = &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] = { + { + .n = "audiopll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .f = CLK_SET_RATE_GATE, + .c = &audiopll_characteristics, + .t = PLL_TYPE_FRAC, + }, + + { + .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_divpmc_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &audiopll_characteristics, + .t = PLL_TYPE_DIV, + }, + + { + .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_divio_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &audiopll_characteristics, + .t = PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] = { + { + .n = "lvdspll_fracck", + .p = "main_osc", + .l = &pll_frac_layout, + .f = CLK_SET_RATE_GATE, + .c = &lvdspll_characteristics, + .t = PLL_TYPE_FRAC, + }, + + { + .n = "lvdspll_divpmcck", + .p = "lvdspll_fracck", + .l = &pll_divpmc_layout, + .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c = &lvdspll_characteristics, + .t = PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] = { + { + .n = "plla_div2pmcck", + .p = "plla_fracck", + .l = &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c = &plladiv2_characteristics, + .t = PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] = { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: true if clock is critical and cannot be disabled + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] = { + { .n = "pioA_clk", .id = 2, }, + { .n = "pioB_clk", .id = 3, }, + { .n = "pioC_clk", .id = 4, }, + { .n = "flex0_clk", .id = 5, }, + { .n = "flex1_clk", .id = 6, }, + { .n = "flex2_clk", .id = 7, }, + { .n = "flex3_clk", .id = 8, }, + { .n = "flex6_clk", .id = 9, }, + { .n = "flex7_clk", .id = 10, }, + { .n = "flex8_clk", .id = 11, }, + { .n = "sdmmc0_clk", .id = 12, }, + { .n = "flex4_clk", .id = 13, }, + { .n = "flex5_clk", .id = 14, }, + { .n = "flex9_clk", .id = 15, }, + { .n = "flex10_clk", .id = 16, }, + { .n = "tcb0_clk", .id = 17, }, + { .n = "pwm_clk", .id = 18, }, + { .n = "adc_clk", .id = 19, }, + { .n = "dma0_clk", .id = 20, }, + { .n = "uhphs_clk", .id = 22, }, + { .n = "udphs_clk", .id = 23, }, + { .n = "macb0_clk", .id = 24, }, + { .n = "lcd_clk", .id = 25, }, + { .n = "sdmmc1_clk", .id = 26, }, + { .n = "ssc_clk", .id = 28, }, + { .n = "can0_clk", .id = 29, }, + { .n = "can1_clk", .id = 30, }, + { .n = "flex11_clk", .id = 32, }, + { .n = "flex12_clk", .id = 33, }, + { .n = "i2s_clk", .id = 34, }, + { .n = "qspi_clk", .id = 35, }, + { .n = "gfx2d_clk", .id = 36, }, + { .n = "pit64b0_clk", .id = 37, }, + { .n = "trng_clk", .id = 38, }, + { .n = "aes_clk", .id = 39, }, + { .n = "tdes_clk", .id = 40, }, + { .n = "sha_clk", .id = 41, }, + { .n = "classd_clk", .id = 42, }, + { .n = "isi_clk", .id = 43, }, + { .n = "pioD_clk", .id = 44, }, + { .n = "tcb1_clk", .id = 45, }, + { .n = "dbgu_clk", .id = 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n = "mpddr_clk", .id = 49, .f = CLK_IS_CRITICAL }, + { .n = "csi2dc_clk", .id = 52, }, + { .n = "csi4l_clk", .id = 53, }, + { .n = "dsi4l_clk", .id = 54, }, + { .n = "lvdsc_clk", .id = 56, }, + { .n = "pit64b1_clk", .id = 58, }, + { .n = "puf_clk", .id = 59, }, + { .n = "gmactsu_clk", .id = 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] = { + { + .n = "flex0_gclk", + .id = 5, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex1_gclk", + .id = 6, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex2_gclk", + .id = 7, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex3_gclk", + .id = 8, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex6_gclk", + .id = 9, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex7_gclk", + .id = 10, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex8_gclk", + .id = 11, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "sdmmc0_gclk", + .id = 12, + .r = { .max = 105000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex4_gclk", + .id = 13, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex5_gclk", + .id = 14, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex9_gclk", + .id = 15, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex10_gclk", + .id = 16, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "tcb0_gclk", + .id = 17, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "adc_gclk", + .id = 19, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "lcd_gclk", + .id = 25, + .r = { .max = 75000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "sdmmc1_gclk", + .id = 26, + .r = { .max = 105000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mcan0_gclk", + .id = 29, + .r = { .max = 80000000 }, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mcan1_gclk", + .id = 30, + .r = { .max = 80000000 }, + .pp = { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 5, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex11_gclk", + .id = 32, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "flex12_gclk", + .id = 33, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "i2s_gclk", + .id = 34, + .r = { .max = 100000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "qspi_gclk", + .id = 35, + .r = { .max = 20000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "pit64b0_gclk", + .id = 37, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "classd_gclk", + .id = 42, + .r = { .max = 100000000 }, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "tcb1_gclk", + .id = 45, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, + + { + .n = "dbgu_gclk", + .id = 47, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "mipiphy_gclk", + .id = 55, + .r = { .max = 27000000 }, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "pit64b1_gclk", + .id = 58, + .pp = { "plla_div2pmcck", }, + .pp_mux_table = { 8, }, + .pp_count = 1, + .pp_chg_id = INT_MIN, + }, + + { + .n = "gmac_gclk", + .id = 67, + .pp = { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table = { 6, 8, }, + .pp_count = 2, + .pp_chg_id = INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range = CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **alloc_mem = NULL; + int alloc_mem_size = 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i = of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc = pmc_data_allocate(PMC_PLLACK + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + alloc_mem = kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!alloc_mem) + goto err_free; + + hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw = hw; + + parent_names[0] = "main_rc_osc"; + parent_names[1] = "main_osc"; + hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] = hw; + + for (i = 0; i < PLL_ID_MAX; i++) { + for (j = 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw = sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw = main_osc_hw; + else + parent_hw = __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw = sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw = sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw; + } + } + + parent_names[0] = md_slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plla_divpmcck"; + parent_names[3] = "upll_divpmcck"; + hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw = at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] = hw; + + parent_names[0] = "plla_divpmcck"; + parent_names[1] = "upll_divpmcck"; + parent_names[2] = "main_osc"; + hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; + parent_names[3] = "masterck_div"; + parent_names[4] = "plla_divpmcck"; + parent_names[5] = "upll_divpmcck"; + parent_names[6] = "audiopll_divpmcck"; + for (i = 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw; + } + + for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw; + } + + parent_names[0] = md_slck_name; + parent_names[1] = td_slck_name; + parent_names[2] = "mainck"; + parent_names[3] = "masterck_div"; + for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents = 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table = kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + PMC_INIT_TABLE(mux_table, 4); + PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw; + alloc_mem[alloc_mem_size++] = mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + kfree(alloc_mem); + + return; + +err_free: + if (alloc_mem) { + for (i = 0; i < alloc_mem_size; i++) + kfree(alloc_mem[i]); + kfree(alloc_mem); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); From patchwork Fri Jun 23 20:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112299 Return-Path: Delivered-To: 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a6-20020a170902900600b001b3d5fdd1c3si52755plp.188.2023.06.23.14.11.45; Fri, 23 Jun 2023 14:11:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hQBFs0q6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232761AbjFWUw1 (ORCPT + 99 others); Fri, 23 Jun 2023 16:52:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232606AbjFWUwK (ORCPT ); Fri, 23 Jun 2023 16:52:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C84B43ABC; Fri, 23 Jun 2023 13:50:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687553415; x=1719089415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xbMFJDkuvSAVzLORTJHW0ZL04qI1N0hFjbaAsJ5qgb0=; b=hQBFs0q6Mb9rdN21VmnlcynVtG6IY00PoOPl2jCM9fUTTOWJungJwrWU URIy29AdKxI7mbJDy913gqkO+mMvCf54iG43lRBWHU4JBjX3TUTz8U4jo X2C0wdaRiVbxowQdN0E0jCTRNkdgIL/7ojuqZ4KYZzUvehBkvZFEvMRjx aooaAxTNJUPYvSwN4A3u6zPwAlfBrr1h5/G74/fLrvxlskA/QfmtDXOt5 oUlxL4VHVG2dpZ9xa6QqX9VUhdODBvjxuv5xtqBkXSU+PToFPanYGPokG fIR2mZAkLFSjj/PjVqhqlOhp+su6nQIPPGBZtbhbPWVvPP32HQsMi7iTr g==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221703169" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:49:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:49:30 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:49:01 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 37/45] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sat, 24 Jun 2023 02:00:48 +0530 Message-ID: <20230623203056.689705-38-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529376925981406?= X-GMAIL-MSGID: =?utf-8?q?1769529376925981406?= From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran --- drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 145535bd7560..bab11900f3ef 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = { { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup }, + { .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; @@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_node *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init); From patchwork Fri Jun 23 20:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6039508vqr; Fri, 23 Jun 2023 14:04:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5TnUfQcM+uboCY6x/uUYoLVPo/41BS17OqF85q+E5wGdXX+inKjl8q1ZvARe8kt00ijSZk X-Received: by 2002:a05:6a20:4299:b0:121:d74e:8b46 with SMTP id o25-20020a056a20429900b00121d74e8b46mr13196048pzj.55.1687554287397; Fri, 23 Jun 2023 14:04:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554287; cv=none; d=google.com; s=arc-20160816; b=Xm6MD1Nf1wkGazJFUCXk9xg+HaZNvIi1I/iS2GLnJBhpr7iS9taRiq0mTMKx2zlmFS 0Ub+YLm7yfLedN3duJh/KHku9r2EW+0i1ROKpz4thI8uiSH50elwhwXus+wl8+bR17No yDynL+PdnBLGlIVlPdKVEE9ebbqRv6DYN6lcoy1EfANLaID2JgcMqKB6E4tTMYxSWEWX miHS7HD9QPWf7geXH8DUdgKoS8O43PxZ5i9Su6S1ZbmmhDW7ZvLqzQ4f9X1dqvxuUTt/ incq+cp/IYk08pvT9L6EAGBvNnjhd4pnUMz6qGyy1DoQp9q7DwqhSh52mtSGIDn9CdZs 6LFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xs/iqBBEHUNhN8oykbtnYWMaHPlfLJfOSBaLVA+C47w=; b=P76WtSZPkevn52bhcSgLkwQ2zAhgnx0M3/PgoeIpLeJRxoizxKDOcoTI44ZxYSDOsO 7OH7EIdCCrV1eoGat9Phqfh8pzTKFi4UAETuGlR9Q2JI3ZBhRUp6iJxCWXn7aDBQXL89 paI9436Nt7GVuppoLrh5fgrEUyNf1jHgshcexsXZxdpAWGeWa6RhtEadssiYvZxxmg4V kv9R4BnMtvShxpPgUYlKNuJnx8s32tYL5CMCsaEK/k9Ba8BvKocist19K8vA5Op4MTFv 9B2FJWN84A/Cb6Wm6SUMr8eI7onnxEucs6iE3e19SgjFOwUgv+tIdcz7Uz9h5KuNQMSI YPHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kCeYn25t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index d8ecffe72f16..d0f29b99f25e 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, { .compatible = "microchip,sama7g5-pmc" }, + { .compatible = "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; From patchwork Fri Jun 23 20:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112301 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6044257vqr; Fri, 23 Jun 2023 14:14:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Z6uE0jycIU1Cgzh4pWDLWWrcfrvnnNLgQc+h9t8SWiCCGX1brbJ+TbDDcjqpycMh6XT/r X-Received: by 2002:a17:90a:c087:b0:25e:91ef:8b24 with SMTP id o7-20020a17090ac08700b0025e91ef8b24mr15738984pjs.24.1687554873148; Fri, 23 Jun 2023 14:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554873; cv=none; d=google.com; s=arc-20160816; b=qChv1BZD3LZ6F4IKq2WOZkxnBkG+WBBUeUXXOjnqhO/uMj7OnJi3vwnlwZhG2DvFoY r9ayZcu6vyZiYKBuAQir2O8v32MJEWp3m793ahJ03cagIlT73QcEQdA2ssqgjUjyd2EZ HYodyysSwvhPANmDP8HRTF2E6zfwcdm8b4WbPAFQ1//Dez13k5pllmJ81oW3cQbKYePD fEiTE7xfbv0LULN/bYPMjTKY+Ph5IF2gIvWpzQ6l03XaBCvMGfSH/oSiwSbrSLhStsC6 ArVfcGB5HxT9lFuVmw1sFdikLC3ytsmR0meKrMUG8fZ54TEVX5qResS12rOv4GahHLmN whYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rnq2r/6DSqRH+C69/kWAsqSNPfzZXNoB0ZDfUQrcaH8=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=JD0x2wpwS9IJIZbqY5yALFMPvXfG0Icejjuz4rFAfS4RhoYimTPfEXhS58TxPNtlra UOnP4KaEUt39fAxN2VPsJniOJqRJxW1z4uwjdwRmgxKt1n7SYUzTfosiJ/0WiX15ZAQE o6+/Lix9GK/kV4kHm+37F3Z6+E8DwfDJFb88B036R/YiM+elPp4g/kJoFtrB+S9DDP3m lUNdUXt9PRUknBbsPFonNyduKz/mEu5jL7m4g4B+QuRaRVAoddW2BbrpDkou8J86zMMh /t8AS1v+s83BOvqiBiP16N/5GzsCo6yacASTcqTrHAGLZnoMO5LDT6YMDuBC5KLncZYL Gv0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=rxS1NLZu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ot15-20020a17090b3b4f00b0025b7628c24csi3002406pjb.106.2023.06.23.14.14.20; Fri, 23 Jun 2023 14:14:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=rxS1NLZu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbjFWVGe (ORCPT + 99 others); Fri, 23 Jun 2023 17:06:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232302AbjFWVG3 (ORCPT ); Fri, 23 Jun 2023 17:06:29 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69D59269A; Fri, 23 Jun 2023 14:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687554387; x=1719090387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lqDl2qv8oW6JjrVycxP7PCqyNjHBaQIvP6CwSvpsy4A=; b=rxS1NLZuSx9JMor5CmNHza3GA+kxyPJBKKvxcKlf6jgkDZc3oErPjufq clGWTLKlLVCDhCQTIwyKwl3P1JsOdtBh+rhgXKNE5dGqqW/RxT7umEkf5 08PXgXomgbbP1GAm7c1AHd/w21d4bwnrcYAluduBh7LOyoyYFxJfAs/WE vlzSJitSyrmLsVYRDlyTth9rsbUG07HQ+vS1dq1iqopg3e11z1xmp8foE AzMYCdh5v72FrbsipM8mwMnakOom9gMDdl8YEI6McI9DqTW79vCTYP75P Q+yO9j4iIDemboLPim0dRgUQzLD0T+Js+3tGnRwiDzm/DRog0cqQ4g3BI g==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221704946" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:06:25 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:50:27 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:49:59 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 39/45] power: reset: at91-reset: add reset support for sam9x7 SoC Date: Sat, 24 Jun 2023 02:00:50 +0530 Message-ID: <20230623203056.689705-40-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529538764588829?= X-GMAIL-MSGID: =?utf-8?q?1769529538764588829?= Add power reset support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8c87eeda0fec..6c4ad81a0059 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs From patchwork Fri Jun 23 20:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112303 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6044922vqr; Fri, 23 Jun 2023 14:15:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5VvfWXYKigxWphVnFLcPuZKKEOObcTJWvyzbKZj+Se4S28u2Vl+VsmGZSweCUSo7mhVzkP X-Received: by 2002:a05:6a20:9390:b0:11d:8a8f:655d with SMTP id x16-20020a056a20939000b0011d8a8f655dmr28659771pzh.4.1687554956107; Fri, 23 Jun 2023 14:15:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554956; cv=none; d=google.com; s=arc-20160816; b=wj1eOzJGwazm+PG0/KN5YojPTrnGi/teLGEbUyZ/P3hcxwNHd7yXftHB9Nb67zMsUt MqmxJLsWa8QWuWM17N3BWqbzJpi9wOHoOtHq/t+sS0oPMLGTTdCCHSJUZu8b3Pkou86B rVZC2hY8C+yj1uGzsGOiVI6jW1KwuNWDU80lvCnhsjI57YAtGsOQpkpixe0irbmi52V9 5lFt7Boh+1WmI06YVNzz7gx3/716mW78nOLepKX0v6ygfZJ+ynYPHjxMMMUNvTPld2A1 lfWabXydChs3IWw5Q/cb4w4VmVHSObCCP76xPynhx3R8Pyt/gkkez/d4vrWPkMJ/hQ6a uWuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NhW9PJJU20aWXaXOYdI5zSy4VwIB+xDPaV0FtHWOlEU=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=X26mfDdmmBjizU4039a8vlqiQ4yt0RM1iL8ScgcomSRMfQVw5VPB7Kll+CKb414FBt DVNP4amfK6X7YConLVdb38Rc/4hiGwZeVEFmk1AYWVEuWMFplNGkur+tTNTpL5803dPj CsUQZ1QGJHHgnFxrrbrhVR2Zm4+JlXKZBk5koDY9N0zINzdXNnFEwuaOkJMUnBmBAmEB MBmJvFjec8F8XduZRaxFcVv/Io0+sL6jo7yl1fOvPFvqCAI7q85wAQey7y3VzpKs2jkf eezo7C02e1FxZoPiu0hdG+S10FlSkFMqev6Y+P2lvNKtj5UVwPae1GTD99nlgfDnhiQZ LQng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=DCIURaEa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 6c4ad81a0059..59459f5abbed 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. 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Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Kconfig | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3dd9e718661b..4e9cb30f5091 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -143,11 +143,28 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -157,7 +174,7 @@ config ATMEL_CLOCKSOURCE_PIT config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -168,7 +185,7 @@ config ATMEL_CLOCKSOURCE_TCB config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or From patchwork Fri Jun 23 20:30:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112294 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6041227vqr; Fri, 23 Jun 2023 14:08:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ449v9Z7tuxe4pCHgCX0QrUcKyXPY4D8yba4GtjAOPFdwDlqN/RzXrMKBVzGtCTndeocnkP X-Received: by 2002:a05:6e02:541:b0:340:b85c:3c99 with SMTP id i1-20020a056e02054100b00340b85c3c99mr20187959ils.4.1687554492677; Fri, 23 Jun 2023 14:08:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554492; cv=none; d=google.com; s=arc-20160816; b=sTFSKNI+HgxOUKteS9K9WCw59uG3Vcmu1AZ0dcPSdRkbIdHW7bN4HcvS5mKBBxtTH1 wK3TEaGqcZM0gb706nqJBXJpqt9evtehZPdg3EK2zDxTC0tdz0dvz/6/f2Ci/iumJHEU 0Z/j8lH/CEp43JufZs8HcDJYVsIGBaaOpvbSYeM+E01TwYMGAy5/+eSeLkrjV+ngBCNb Zd3IN8rWg9oj+1hvBU/4xf+BXgvkmO4cGOjIzLvuahLy5sLWVWhg63+0Y06TI7yQw5a6 S2cjbFO0DTGgUc5jn5lulb7OAZKj+rGxjftWsc5G2U5ank1lWqQEgtuvsxTOgoNzr2CG Bf9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E40Qu2p6GhTM/8NoVQfFszyd2HhWzYD013QK5KlUS/c=; b=dNmXwzhhRi3OHdLu+2xVoAKMgNTI6MaDrpNSnvnQPUn3Z1juXxL9NPcFA6qoGooMGe JBms7T+PRebqGnz/9vgNfUWgPEkRZNapV7SCw5TJRaBPx1ETk8w3tqhzDLnAe1ozooq6 nhmeZRM1S/bLdu7RpgUL94p0Ra9QXJc+4iYrDQlrmqAJ/xK8vKEEfczW0NchqaU8C4W6 OqNwifoSCg4Hpzt0uOF2zx0/TyB+xowm383oXFu6Y/wQHvxhthTieSmLPjiRS5Jbsn1h XyeKeHgRzjgbCP0ByAcIYESX8zaZ0yZ2xYySudX/r5KaAuPj4pGDB75dujtK1to5bgyC K8cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=MD4aIlYb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p2-20020aa79e82000000b006667a4ebfa8si9687669pfq.336.2023.06.23.14.08.00; Fri, 23 Jun 2023 14:08:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=MD4aIlYb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232425AbjFWVH1 (ORCPT + 99 others); Fri, 23 Jun 2023 17:07:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbjFWVHY (ORCPT ); Fri, 23 Jun 2023 17:07:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50ACF2114; Fri, 23 Jun 2023 14:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687554443; x=1719090443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VSgJEaXGE5mC5+J5yXqmr6+eX6G4aP7h1/R3eyDsTQg=; b=MD4aIlYbYeMZGw43NDgORvAaJr5F7xOrQbJLHfxY9Az/viOTQ9cmN4kV iCS3JbEmt8NQlyuOFGiVuJmZjWiqV7CFDkWbXOiIF1dsxTJSHg6m4qAFe ZYWKopSk1NGhk/anLiubEK/EOAAEs55wQ0q8ptsIoYpU6QALJ9nqmXvVb eLvKd1qsGIZ9cUSUecpfA/q5xzva99D+yHmfyuutsuIZ7WCV1tKhF4QUf wbQMhYXlns88XR3bw3dibpx60QMjcurhSO/b5mDeYawy8wQOtSbRqBXjP 4s4pwuWKBS6qy9AdFopU2GDTDiq4ZDybhFynDn6KPVO8ttgznumz5OHxq Q==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221705070" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:07:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:51:56 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:51:26 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 42/45] ARM: configs: at91: enable config flags for sam9x7 SoC family Date: Sat, 24 Jun 2023 02:00:53 +0530 Message-ID: <20230623203056.689705-43-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529139877101526?= X-GMAIL-MSGID: =?utf-8?q?1769529139877101526?= Enable config flags for SAM9X7 SoC for the sam9x7 SoC family. Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 82bcf4dc7f54..6266a000736b 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_AT91RM9200=y CONFIG_SOC_AT91SAM9=y CONFIG_SOC_SAM9X60=y +CONFIG_SOC_SAM9X7=y # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=y CONFIG_UACCESS_WITH_MEMCPY=y From patchwork Fri Jun 23 20:30:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112296 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6041843vqr; Fri, 23 Jun 2023 14:09:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4vOT7qlb//w+3c/WKg0ZIubANnSSqCP3bHQUoFcrsE96+AbCVl1ggSWxwbNlZoaBeQREUW X-Received: by 2002:a05:6a20:1603:b0:125:bf44:a939 with SMTP id l3-20020a056a20160300b00125bf44a939mr2723007pzj.47.1687554564146; Fri, 23 Jun 2023 14:09:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687554564; cv=none; d=google.com; s=arc-20160816; b=BhbK+QDwACCHMw3Wx44fDPyTw5dXnAr2iDaMRlyv3rMb7M0eYGxhLLC2BxCbgKpGlT 83/YaLoCW44S0r92nmyDt8birMnu0S04McB65xq8HONW+pnxcp+yId43ycGRWiH0Oo+5 o9/vMv4rDgF1eJTrafhC4Dwmrt02AK8AEh55yk510fbIKqzIWFYvSLKFRpNgqOSMusdY oiENZAtf0ZSkpckHNYFM6rWUi7Sv7tHKZ99085Pj6Hgsou2dpgJfKHa2DfAb4pkXuyaj z3tYedgnLtn8XEo4T30ZMqwUwSFEkZKP6osQNAd/w9uZGCknJ69ZxJMpHQ/o+ABN0GBT Ph9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LyYUcskAagXUZtYkk6v//ClyGN3ouRMO1m/oxUMLoxQ=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=vGXHjMf/oolmVoDmA7NMQlp+O6gkJC4zpNtG9AdyY5SkM5z5aQxmDFCF57fV9v2Fss /ZzgcepkwU2NYgRJ7Xvnpy05HXTdWOl9YgX0NLFSrYeCPOtyXvWXBIMy5LVUweruWwFC 9Bkc+wVrMiKWcJUt3Uz5f5e0KqWkF5JZJU+kaVe4tTVXuPrFkxFvNrcK2pf/2+TPpH7y tDjOC3KNlIXs0nv1Dxpi1DYK5K/kycTY9l18e18DQjv+o6YjxXdsNw+VCbiVzxxFeVne PRZbBqKq2ZolrK/HG4irGoJQ0M3OJKb6gEGEecqpQfoJjDIdL6HaosZontuOj4B5JbsO gpbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Dh6i567a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j35-20020a63fc23000000b005538c82b70fsi243214pgi.166.2023.06.23.14.09.08; Fri, 23 Jun 2023 14:09:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Dh6i567a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232555AbjFWVIh (ORCPT + 99 others); Fri, 23 Jun 2023 17:08:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232404AbjFWVId (ORCPT ); Fri, 23 Jun 2023 17:08:33 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17931186; Fri, 23 Jun 2023 14:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687554508; x=1719090508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G3nX5kwmg5LS1k+6Kh3/u8XFKk+t1Xv+dOMktsPj8FU=; b=Dh6i567aMaQPgfuNHW5N+0XV5aLylurUHbEn5umMhJ6Qm3y2Q84g2P0W nhcRcezZ94/AJdOitqE+VV27NhWpEbBkxErhGcLBqJtNrlHSFn3wG44bS T4mGpF7ETYuKQbfJlkyWSgDnORcH153YWJwTBgm3n/MbRW7iDpjMv9j0a MOxDUqUSQ1RS8MIZ7j5TiVmuPQuYxmQtxZLaiNlx1hI4ASUo+9UBOmKob 2Qc6wNQNwesX5ke1OHiwUDFrP0oYOsevMZJo1o0l1mle6ZDLsPNAx3Quk AnBV2zSCz1V4ZnijnWEH3eAgT0EbSJNGThQdrwZaNYsAqL0b3K3xD/wVg w==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221705299" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 14:08:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:52:28 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:51:59 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 43/45] ARM: dts: at91: sam9x7: add device tree for SoC Date: Sat, 24 Jun 2023 02:00:54 +0530 Message-ID: <20230623203056.689705-44-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769529214612844961?= X-GMAIL-MSGID: =?utf-8?q?1769529214612844961?= Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/sam9x7.dtsi | 1237 +++++++++++++++++++++++++++++++++ 1 file changed, 1237 insertions(+) create mode 100644 arch/arm/boot/dts/sam9x7.dtsi diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi new file mode 100644 index 000000000000..535a55f13dd0 --- /dev/null +++ b/arch/arm/boot/dts/sam9x7.dtsi @@ -0,0 +1,1237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Microchip SAM9X7 SoC"; + compatible = "microchip,sam9x7"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300000 0x10000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: gadget@500000 { + compatible = "microchip,sam9x7-udc", "microchip,sam9x60-udc"; + reg = <0x500000 0x100000>, + <0xf803c000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names = "pclk", "hclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + ohci0: usb@600000 { + compatible = "microchip,sam9x7-ohci", "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x600000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + ehci0: usb@700000 { + compatible = "microchip,sam9x7-ehci", "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x700000 0x100000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + + sdmmc0: sdio-host@80000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x80000000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc1: sdio-host@90000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx4: flexcom@f0000000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0000000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0000000 0x800>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0004000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0004000 0x800>; + status = "disabled"; + + uart5: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible = "microchip,sam9x7-dma", "microchip,sam9x60-dma", "atmel,sama5d4-dma"; + reg = <0xf0008000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + ssc: ssc@f0010000 { + compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + status = "disabled"; + }; + + i2s: i2s@f001c000 { + compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg = <0xf001c000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0020000 0x800>; + status = "disabled"; + + uart11: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c11: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf0024000 0x800>; + status = "disabled"; + + uart12: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c12: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg = <0xf002c000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "sha_clk"; + }; + + trng: rng@f0030000 { + compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg = <0xf0030000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + status = "disabled"; + }; + + aes: crypto@f0034000 { + compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg = <0xf0034000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "aes_clk"; + }; + + tdes: crypto@f0038000 { + compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xf0038000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "tdes_clk"; + }; + + classd: classd@f003c000 { + compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg = <0xf003c000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names = "tx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names = "pclk", "gclk"; + status = "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0040000 0x100>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible = "bosch,m_can"; + reg = <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0 + 68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "bosch,m_can"; + reg = <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0 + 69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + tcb: timer@f8008000 { + compatible = "microchip,sam9x7-tcb","microchip,sam9x60-tcb", "simple-mfd", "syscon"; + reg = <0xf8008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; + clock-names = "t0_clk", "slow_clk"; + status = "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8010000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8010000 0x800>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8014000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8014000 0x800>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8018000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8018000 0x800>; + status = "disabled"; + + uart8: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c8: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf801c000 0x800>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8020000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8020000 0x800>; + status = "disabled"; + + uart1: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8024000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8024000 0x800>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8028000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8028000 0x800>; + status = "disabled"; + + uart3: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,sam9x7-spi", "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem" ; + reg = <0xf802c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 60 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 61 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 2 */ + 62 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 3 */ + 63 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 4 */ + 64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "hclk", "pclk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 67>; + status = "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8040000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8040000 0x800>; + status = "disabled"; + + uart9: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c9: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8044000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8044000 0x800>; + status = "disabled"; + + uart10: serial@200 { + compatible = "microchip,sam9x7-usart", "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c10: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + sfr: sfr@f8050000 { + compatible = "microchip,sam9x7-sfr, microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible = "microchip,sam9x7-matrix", "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x7-pmecc", "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible = "microchip,sam9x7-ddramc", "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x7-smc", "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x7-aic"; + reg = <0xfffff100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "microchip,sam9x7-dbgu", "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names = "usart"; + status = "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-mfd"; + ranges = <0xfffff400 0xfffff400 0x800>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: pmc@fffffc00 { + compatible = "microchip,sam9x7-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: rstc@fffffe00 { + compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k 0>; + }; + + shutdown_controller: shdwc@fffffe10 { + compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg = <0xfffffe10 0x10>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible = "microchip,sam9x7-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + clk32k: sckc@fffffe50 { + compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: syscon@fffffe60 { + compatible = "microchip,sam9x7-gbpr", "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg = <0xfffffea8 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + status = "disabled"; + }; + }; + }; +}; From patchwork Fri Jun 23 20:30:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112302 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6044748vqr; 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Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index dfb8fd089197..15b11feae46a 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -99,6 +99,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 From patchwork Fri Jun 23 20:30:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 112332 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp6054641vqr; Fri, 23 Jun 2023 14:40:15 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7YodnjEFUvd1nmit7I1tgxIT9anMO1WhI5jd3fCzb+5g4nPp0tITt3Bqwf5KHjaGZ4r6Ke X-Received: by 2002:a05:6359:62a:b0:12f:91d6:3234 with SMTP id eh42-20020a056359062a00b0012f91d63234mr13972975rwb.14.1687556415117; Fri, 23 Jun 2023 14:40:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687556415; cv=none; d=google.com; s=arc-20160816; b=pa8PoRmQncwvlcKMQwlr0sOKxxjIah/+c/LmMoUjJxYvDb8fKq6ypDjN+Ho8St1Emy UyIjilYvvUVBpj1mpqymd7uQIhargd0CWov/i3WlQoDs8QxOUfiXLSp7r6ZyiR24IQ7o xBQ/pPxl9CGCUWhwhYm25nUawPxP3dyCtuLn4Vjvv149coj7hrtvW392Y0eSUvMsLo+b AEzlZ0/yyR36FU8rvOzLzKN4TXFX0EcWwm0UiQy7hznDrpbOtnjIYpMZavnL38nmnOfo z1u+VRqIgE793zILyp8saey38rUP1JWHre1krRQEkal7oW1Auaoua2HwZevivtd4M43H HiAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6vNjBwxHPpFCxTZQ4BQlGa9cMzDjnQ5bkZi3LanANLE=; fh=gvF0Lmh3we7l1N050eW0NXEfX6fwK1w/g3y1gvYPqdE=; b=kFefR1+jCJs+oYb6ScYFBdhi7eB1ymTz1jxBsr83S2M+AqBDW8NayhH6G9kL2gE0q7 qHfyd0ferxkeg4SwIHYz90oGpBnmW6kUTvJ1uB85YJp6IsKuuZkiJ5hwqK84SgHiwKRl jis3aOtRXKhoWlHDq7CcTooCxUZzXxKW8wn/99hmTyzBmJ8YOCgTBK7orzPaylcNoUhJ Z4aER7wgEXyX17Tv3noz4/E/oYkT8k22qmWw/NTkhZiJHK9B3/sdnO5QIHpJHg++nzZb 8QtkGu8gB2tgEYP/UFR3A2wvN4j7uf9ZeHi+0ScE7YFF3vf8WaRAQEOYh7rWr2USdjUn 6p3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=i1hCY247; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/at91-sam9x75_curiosity.dts | 336 +++++++++++++++++++ 2 files changed, 338 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc90315..31f357f8e947 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -53,6 +53,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) += \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..56d3af549201 --- /dev/null +++ b/arch/arm/boot/dts/at91-sam9x75_curiosity.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model = "Microchip SAM9X75 Curiosity"; + compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c6; + i2c1 = &i2c7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + clock-slowxtal { + clock-frequency = <32768>; + }; + + clock-mainxtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + status = "okay"; + + button-user { + label = "USER"; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; + + led-0 { + label = "red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "green"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "blue"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x10000000>; + }; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1283000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1210000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; + }; +}; + +&flx7 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c7: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + }; +}; + +&ohci0 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioC 27 GPIO_ACTIVE_HIGH + &pioB 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&pinctrl { + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6_twi { + atmel,pins = + ; + }; + + pinctrl_flx7_default: flx7_twi { + atmel,pins = + ; + }; + }; + + gpio_keys { + pinctrl_key_gpio_default: pinctrl_key_gpio { + atmel,pins = ; + }; + }; + + leds { + pinctrl_led_gpio_default: pinctrl_led_gpio { + atmel,pins = ; + }; + }; + + ohci0 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins = + ; /* PA5 DAT3 periph A with pullup */ + }; + }; + + usb0 { + pinctrl_usba_vbus: usba_vbus { + atmel,pins = ; + }; + }; +}; /* pinctrl */ + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&shutdown_controller { + atmel,shdwc-debouncer = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&trng { + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioC 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +};