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Thu, 22 Jun 2023 08:18:53 -0500 From: Yazen Ghannam To: CC: , , , Yazen Ghannam Subject: [PATCH 1/2] x86/mce: Disable preemption for CPER decoding Date: Thu, 22 Jun 2023 08:18:40 -0500 Message-ID: <20230622131841.3153672-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622131841.3153672-1-yazen.ghannam@amd.com> References: <20230622131841.3153672-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|LV8PR12MB9081:EE_ X-MS-Office365-Filtering-Correlation-Id: e4939043-1299-49f5-0a02-08db73233a9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lqk8tB0rvuM/VmSA+Y5OEJ5GjRL3UqHKxkh0hOC0gQdS5uVbMpi8qMPlvZ4Ndtne98aPhPhaSPitrBE1YFcfxotYXkWjI733TkkTBL7tniZ3QOdpTCbgPuPilWvzRnEa/MfI7LUU2wenhkI6P8ESvCJnggE9uLXwWGUz665wP2mzyRmnAGWTRLvwU8F6rwoxOykxQ0+gRMKxDS4ozSoD8Qch27n5WSy3mr6ucCzUJeGDCZjMVPWVued4vq8F48TsWdC3hse9PDvsgped1eYF9oavNffDRXgXpCdofHgL2n1jOCaDlsv69xdVCaVWAEjI20Wa39Qh6LEYsDqNq12Ev8BRgugCkLIXeF/g00Kmsr9i9hl/40fzzHT4oDGublDAtAnKCf2KpAAvA6+RBhvxNLBjGrmFgYYoE2cQ1eHLIx0+xkgFXL4MC5367JeN1XlAyknvirtOLEIqzsIJfWNQpygRzQ9CyqZ7wqCfHCREtnMXWv4W+j4xOdiZimyBacaotPsBWRE6Bhh/+O7smPNfZJ03oQqCA3SiqYPXvb8ZImbb/QBExGuacS1GqVaVxZ6muWwYKtIh/AOIdnLU/n3kjYmKI1PKz42GrUs1GX/LxzA8JTDLkzrl0MYI9Pl77EWQXZn9bJz8QzK/BZ1XjbHXMHu1ke2V0L7vR9OoTONV/yW3utIKfenI2lSSCz+GHHNr7fKNSPRQSuYt5l9y2sSm/mqFpdcUn1fDj24wUJcweL5htRjZTpTOg9OuMDfbIuULbd177Pg8KF96qb0nad9yaw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199021)(36840700001)(46966006)(40470700004)(70206006)(70586007)(4326008)(316002)(8676002)(8936002)(6916009)(16526019)(41300700001)(26005)(186003)(2616005)(1076003)(54906003)(40460700003)(6666004)(426003)(336012)(7696005)(82310400005)(2906002)(5660300002)(478600001)(40480700001)(44832011)(81166007)(356005)(82740400003)(47076005)(36860700001)(83380400001)(36756003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 13:18:54.6917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4939043-1299-49f5-0a02-08db73233a9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9081 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769409704788433170?= X-GMAIL-MSGID: =?utf-8?q?1769409704788433170?= Scalable MCA systems may report errors found during boot-time polling through the ACPI Boot Error Record Table (BERT). The errors are logged in an "x86 Processor" Common Platform Error Record (CPER). The format of the x86 CPER does not include a logical CPU number, but it does provide the logical APIC ID for the logical CPU. Also, it does not explicitly provide MCA error information, but it can share this information using an "MSR Context" defined in the CPER format. The MCA error information is parsed by 1) Checking that the context matches the Scalable MCA register space. 2) Finding the logical CPU that matches the logical APIC ID from the CPER. 3) Filling in struct mce with the relevant data and logging it. All the above is done when the BERT is processed during late init. This can be scheduled on any CPU, and it may be preemptible. This results in two issues. 1) mce_setup() includes a call to smp_processor_id(). This will throw a warning if preemption is enabled. 2) mce_setup() will pull info from the executing CPU, so some info in struct mce may be incorrect for the CPU with the error. For example, in a dual-socket system, an error logged in socket 1 CPU but processed by a socket 0 CPU will save the PPIN of the socket 0 CPU. Fix the first issue by locally disabling preemption before calling mce_setup(). Fixes: 4a24d80b8c3e ("x86/mce, cper: Pass x86 CPER through the MCA handling chain") Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/mce/apei.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 8ed341714686..2a7a51ca2995 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -97,7 +97,9 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; + get_cpu(); mce_setup(&m); + put_cpu(); m.extcpu = -1; m.socketid = -1; From patchwork Thu Jun 22 13:18:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 111672 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp5074304vqr; Thu, 22 Jun 2023 06:35:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ48OmULX9TIlvUI9NBiNqJWejrjZBEG38sb1Aw59LPe+LL2l6WsHZ40ezEjP68Q2heJEcXL X-Received: by 2002:a17:90b:3684:b0:260:b83e:89d4 with SMTP id mj4-20020a17090b368400b00260b83e89d4mr12661659pjb.15.1687440947431; Thu, 22 Jun 2023 06:35:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1687440947; cv=pass; d=google.com; s=arc-20160816; b=i8GvDsSlfAXpfm8l/cfb7Mnnfw32kUspVCKGLS7b9nl7Lt1AoVcK502tvW/IAdSvMp t1Rlg9iRzFdqtdA0tS26ncvPwnlWQ0Qhm6VYmqygUea/vqxnthiNEVjJgaFs6wBbfN23 OaKPBjBU0FJAYFG3AwVU0IrgGig9IAjPJJiTBhE6Klsmig5h10DQ2AYDj3mQ4bWYPeJx KAVcFotEax+3FglHwSDJ4g7CxzaRKTvCO/x4fc6ERWNzzNxL9fDWzvgtnuPLr5hrjzPi iCuGIBsgmL0FsX/9ma5YBT63iEJB9rrBMMaZs8mItadIY8TySxSij0QF6Whld0clb0hO lhXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sRWB/4kf1oZTznE/Bfp3f7eaqvkTVSds9z5xT02HmdM=; b=piM0H/xWqPYYhQA0gm/TmNsJFOx8bXL7kwfhAasFLpe7HOoA7pmGTz0zKEUxKPaP0u CVQa9qRHJF34sy/GCXEngNbVk/qXJq4oD3xqve3o5fFoLDAb54i1CLH56cZSBOXpYZ49 +0GdQMNLpK5g6ameyOhwazxDUGEao0AGKih4LJGB34Hl70fOXvYB7XP6yiNBhI+PLGKf thpExGR0uW7F6zfIqBv0xO1836NJub2cVkmzsQEoV8R83nl+G37o6RtSvoatGUCqDrgx Qr3ypk8PdEMUFIFys2HSNKrH7LO25cAh3ztRgisb66+T6LH8c3GtVnUQhVWJTaSkNLVp RlGg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=bne8DJYM; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Thu, 22 Jun 2023 08:18:53 -0500 From: Yazen Ghannam To: CC: , , , Yazen Ghannam Subject: [PATCH 2/2] x86/mce: Set correct PPIN for CPER decoding Date: Thu, 22 Jun 2023 08:18:41 -0500 Message-ID: <20230622131841.3153672-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622131841.3153672-1-yazen.ghannam@amd.com> References: <20230622131841.3153672-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|SA0PR12MB4446:EE_ X-MS-Office365-Filtering-Correlation-Id: abfb3bc5-c35d-4d96-a35b-08db73233af8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uX97pphwtIRCnQ42yLp/LqB2a0isyP3KrTskwLz+N/vY1/HpKO2aM9wLUbEgHfNe+PdXZfxNkj+zPXG56CeITw8Y5zHogsVMywd9uqa4dCbLwagPts35fdtVnLQ2jB+HZVyeeplL0z5dZdLL67QTkLgOqLEwwrB+JMLugeOJR+Zo+fIFiZGOZzVxmqA+/A+HtjooTpZjI7HeoyE4icAxz096w83a7SyaBeOoLPDxcAZNQYtz8MlmvqexJL3tLgDOKepvZO4nanRIaQRa9vkDl3RkgOvTk5BQuLnvglscuzC9glNNBgsWx0+ossl10EwWRVlAvCwsEUC2zQN4oumHupF5ERoVtuZ3CFcSV+vpIvdL3ptoxU0FmayX8IINLPOMN8dsEY20YKIih1lveS0owcx7j6SWrWhu6P7/F+kMaICyQvsk9zc3pd/PL9ljROSVGfJ3xb2CF813ndGIGCxRNjdf80e5iEWlR/q2oz8BJN1OyL61xda2sEldd/YdGKs0DnrX7w4z54SmyvaRzGvGX3QvJmrQ6SZ5MoRMrHCmQXnKoZXvzV2K/4nKgkx5ClGR4Q1FgKHttVjTsiWCNGekWxyk5HZpcv7PGwLj1T8JmSpbDCBQ8gguI7RhDyJhE5UEaHPodNrsm6N5rXDPZqLtwGMHoEH2P6j2JqFK+Qc7J9DB2vTBpxQlbzlHSpcewli/jJeWKkTjrOI5xBfmVHaYG7QcZsbpxWzetd9cq38emuC0fwwoalHn5OxtK6kzLUj0mp+omhU0kadLWWCJZFVFDA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(186003)(26005)(16526019)(1076003)(40460700003)(478600001)(2906002)(44832011)(40480700001)(81166007)(86362001)(41300700001)(36860700001)(8936002)(8676002)(356005)(47076005)(2616005)(426003)(336012)(36756003)(82310400005)(54906003)(316002)(82740400003)(4326008)(6916009)(6666004)(7696005)(5660300002)(70586007)(70206006)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 13:18:55.2855 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abfb3bc5-c35d-4d96-a35b-08db73233af8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4446 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769410078893673765?= X-GMAIL-MSGID: =?utf-8?q?1769410078893673765?= Scalable MCA systems may report errors found during boot-time polling through the ACPI Boot Error Record Table (BERT). The errors are logged in an "x86 Processor" Common Platform Error Record (CPER). The format of the x86 CPER does not include a logical CPU number, but it does provide the logical APIC ID for the logical CPU. Also, it does not explicitly provide MCA error information, but it can share this information using an "MSR Context" defined in the CPER format. The MCA error information is parsed by 1) Checking that the context matches the Scalable MCA register space. 2) Finding the logical CPU that matches the logical APIC ID from the CPER. 3) Filling in struct mce with the relevant data and logging it. All the above is done when the BERT is processed during late init. This can be scheduled on any CPU, and it may be preemptible. This results in two issues. 1) mce_setup() includes a call to smp_processor_id(). This will throw a warning if preemption is enabled. 2) mce_setup() will pull info from the executing CPU, so some info in struct mce may be incorrect for the CPU with the error. For example, in a dual-socket system, an error logged in socket 1 CPU but processed by a socket 0 CPU will save the PPIN of the socket 0 CPU. Fix the second issue by using the PPIN value cached during CPU init. Fixes: 4a24d80b8c3e ("x86/mce, cper: Pass x86 CPER through the MCA handling chain") Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/mce/apei.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 2a7a51ca2995..db16dc3c7b03 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -103,11 +103,13 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) m.extcpu = -1; m.socketid = -1; + m.ppin = 0; for_each_possible_cpu(cpu) { if (cpu_data(cpu).initial_apicid == lapic_id) { m.extcpu = cpu; m.socketid = cpu_data(m.extcpu).phys_proc_id; + m.ppin = cpu_data(m.extcpu).ppin; break; } }