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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id f20-20020a7bcd14000000b003f7f2a1484csm4192394wmj.5.2023.06.21.00.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 00:22:37 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2 1/3] Documentation: arm: Add bootargs to the table of added DT parameters Date: Wed, 21 Jun 2023 09:22:32 +0200 Message-Id: <20230621072234.9900-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769299112989319263?= X-GMAIL-MSGID: =?utf-8?q?1769299112989319263?= The bootargs node is also added by the EFI stub in the function update_fdt(), so add it to the table. Signed-off-by: Alexandre Ghiti --- Documentation/arm/uefi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arm/uefi.rst b/Documentation/arm/uefi.rst index baebe688a006..2b7ad9bd7cd2 100644 --- a/Documentation/arm/uefi.rst +++ b/Documentation/arm/uefi.rst @@ -50,7 +50,7 @@ The stub populates the FDT /chosen node with (and the kernel scans for) the following parameters: ========================== ====== =========================================== -Name Size Description +Name Type Description ========================== ====== =========================================== linux,uefi-system-table 64-bit Physical address of the UEFI System Table. @@ -67,4 +67,6 @@ linux,uefi-mmap-desc-ver 32-bit Version of the mmap descriptor format. kaslr-seed 64-bit Entropy used to randomize the kernel image base address location. + +bootargs String Kernel command line ========================== ====== =========================================== From patchwork Wed Jun 21 07:22:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 110840 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp4186095vqr; Wed, 21 Jun 2023 00:37:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ62roeCzN2d1//zoDCi+gYybiMqLgcDdn1c00cT9Bk0foIEjuGA1ebfpgaz2KIr6rgaxH6M X-Received: by 2002:a05:620a:2195:b0:762:3ecb:ed1a with SMTP id g21-20020a05620a219500b007623ecbed1amr13855118qka.18.1687333078449; Wed, 21 Jun 2023 00:37:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687333078; cv=none; d=google.com; s=arc-20160816; b=IBz1RbiodSJhzsqQtSheJ3Avt2QfDFFdUmrbhKuPc2kwsUB8VbtVfXa98Rc4w9yH1w k3ohptlKjzGdbpb+9u0fYJSPDHKzpvI2yWT089IAhX7yHHnYqINUmJQGq8Fg+S5Tk7wD aaY1uLj08HEcgWGSssx4zgsgJBrkyzZj5zi1GfR5pI+BxvGxSK03rg03Plvp2hBvVdsn kCVjGaLyRMh9OlR7imy/Q378l+wKf2ULH95xhmRr3STl+e6kakiR+aXQb6wwKrcWqlw1 7+koWhxttgPqSy6wWb2n9T3YclwZtVu8Bc1gt5d3yS0oXqKk6nma6c8akXSbARbL2rU7 PQjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fnyPv31F45M86yIwQlrstisnBOJBnjKhbMY/p4sY5eQ=; b=MfgFsY+AbnV8MgDeYlfIFY0kLoqTNr2H6xN/Z19+kq2SVHsRiMHeOBG2pvDi4Nuvja EbF+vQ14wnHJu1uQxYtcxtX012KVve+f9ZxWiXxWvxrQ0peHB6mriHNPOjO/qCDwbYAy rGrQfDsHFok2iqX6a1b+lXvZEp4daG4xDIxsKRRspwakHr7FaYVmTsZQYrxki27o9yX1 spkX2j5SHNOUZ8KrmWHZIcu3cZhLFUt67OMKUDTOQB95NIQuMWbRRpLQlpX14+TRKWp3 vzEI1D7Jy/dvJt4Tz9TOyxZzWpB7viswCYHOzzsgAEqOsrklZGLo0i9mikhb0FKjynVz Uzbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=TkxKBo7s; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id l5-20020a1ced05000000b003f70a7b4537sm15214394wmh.36.2023.06.21.00.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 00:23:38 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= Subject: [PATCH v2 2/3] Documentation: riscv: Add early boot document Date: Wed, 21 Jun 2023 09:22:33 +0200 Message-Id: <20230621072234.9900-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230621072234.9900-1-alexghiti@rivosinc.com> References: <20230621072234.9900-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769296969925160527?= X-GMAIL-MSGID: =?utf-8?q?1769296969925160527?= This document describes the constraints and requirements of the early boot process in a RISC-V kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Björn Töpel Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Andrew Jones --- Documentation/riscv/boot-image-header.rst | 3 - Documentation/riscv/boot.rst | 170 ++++++++++++++++++++++ Documentation/riscv/index.rst | 1 + 3 files changed, 171 insertions(+), 3 deletions(-) create mode 100644 Documentation/riscv/boot.rst diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index d7752533865f..a4a45310c4c4 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -7,9 +7,6 @@ Boot image header in RISC-V Linux This document only describes the boot image header details for RISC-V Linux. -TODO: - Write a complete booting guide. - The following 64-byte header is present in decompressed Linux kernel image:: u32 code0; /* Executable code */ diff --git a/Documentation/riscv/boot.rst b/Documentation/riscv/boot.rst new file mode 100644 index 000000000000..019ee818686d --- /dev/null +++ b/Documentation/riscv/boot.rst @@ -0,0 +1,170 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +RISC-V Kernel Boot Requirements and Constraints +=============================================== + +:Author: Alexandre Ghiti +:Date: 23 May 2023 + +This document describes what the RISC-V kernel expects from bootloaders and +firmware, but also the constraints that any developer must have in mind when +touching the early boot process. For the purposes of this document, the +'early boot process' refers to any code that runs before the final virtual +mapping is set up. + +Pre-kernel Requirements and Constraints +======================================= + +The RISC-V kernel expects the following of bootloaders and platform firmware: + +Register state +-------------- + +The RISC-V kernel expects: + + * `$a0` to contain the hartid of the current core. + * `$a1` to contain the address of the devicetree in memory. + +CSR state +--------- + +The RISC-V kernel expects: + + * `$satp = 0`: the MMU, if present, must be disabled. + +Reserved memory for resident firmware +------------------------------------- + +The RISC-V kernel must not map any resident memory, or memory protected with +PMPs, in the direct mapping, so the firmware must correctly mark those regions +as per the devicetree specification and/or the UEFI specification. + +Kernel location +--------------- + +The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64 +and 4MB aligned for rv32). Note that the EFI stub will physically relocate the +kernel if that's not the case. + +Hardware description +-------------------- + +The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel. + +The devicetree is either passed directly to the kernel from the previous stage +using the `$a1` register, or when booting with UEFI, it can be passed using the +EFI configuration table. + +The ACPI tables are passed to the kernel using the EFI configuration table. In +this case, a tiny devicetree is still created by the EFI stub. Please refer to +"EFI stub and devicetree" tree section below for details about this devicetree. + +Kernel entrance +--------------- + +On SMP systems, there are 2 methods to enter the kernel: + +- `RISCV_BOOT_SPINWAIT`: the firmware releases all harts in the kernel, one hart + wins a lottery and executes the early boot code while the other harts are + parked waiting for the initialization to finish. This method is mostly used to + support older firmwares without SBI HSM extension and M-mode RISC-V kernel. +- `Ordered booting`: the firmware releases only one hart that will execute the + initialization phase and then will start all other harts using the SBI HSM + extension. The ordered booting method is the preferred booting method for + booting the RISC-V kernel because it can support cpu hotplug and kexec. + +UEFI +---- + +UEFI memory map +~~~~~~~~~~~~~~~ + +When booting with UEFI, the RISC-V kernel will use only the EFI memory map to +populate the system memory. + +The UEFI firmware must parse the subnodes of the `/reserved-memory` devicetree +node and abide by the devicetree specification to convert the attributes of +those subnodes (`no-map` and `reusable`) into their correct EFI equivalent +(refer to section "3.5.4 /reserved-memory and UEFI" of the devicetree +specification v0.4-rc1). + +RISCV_EFI_BOOT_PROTOCOL +~~~~~~~~~~~~~~~~~~~~~~~ + +When booting with UEFI, the EFI stub requires the boot hartid in order to pass +it to the RISC-V kernel in `$a1`. The EFI stub retrieves the boot hartid using +one of the following methods: + +- `RISCV_EFI_BOOT_PROTOCOL` (**preferred**). +- `boot-hartid` devicetree subnode (**deprecated**). + +Any new firmware must implement `RISCV_EFI_BOOT_PROTOCOL` as the devicetree +based approach is deprecated now. + +Early Boot Requirements and Constraints +======================================= + +The RISC-V kernel's early boot process operates under the following constraints: + +EFI stub and devicetree +----------------------- + +When booting with UEFI, the devicetree is supplemented (or created) by the EFI +stub with the same parameters as arm64 which are described at the paragraph +"UEFI kernel support on ARM" in Documentation/arm/uefi.rst. + +Virtual mapping installation +---------------------------- + +The installation of the virtual mapping is done in 2 steps in the RISC-V kernel: + +1. :c:func:`setup_vm` installs a temporary kernel mapping in + :c:var:`early_pg_dir` which allows discovery of the system memory. Only the + kernel text/data are mapped at this point. When establishing this mapping, no + allocation can be done (since the system memory is not known yet), so + :c:var:`early_pg_dir` page table is statically allocated (using only one + table for each level). + +2. :c:func:`setup_vm_final` creates the final kernel mapping in + :c:var:`swapper_pg_dir` and takes advantage of the discovered system memory + to create the linear mapping. When establishing this mapping, the kernel + can allocate memory but cannot access it directly (since the direct mapping + is not present yet), so it uses temporary mappings in the fixmap region to + be able to access the newly allocated page table levels. + +For :c:func:`virt_to_phys` and :c:func:`phys_to_virt` to be able to correctly +convert direct mapping addresses to physical addresses, they need to know the +start of the DRAM. This happens after step 1, right before step 2 installs the +direct mapping (see :c:func:`setup_bootmem` function in arch/riscv/mm/init.c). +Any usage of those macros before the final virtual mapping is installed must +be carefully examined. + +Device-tree mapping via fixmap +------------------------------ + +The RISC-V kernel uses the fixmap region to map the devicetree because the +devicetree virtual mapping must remain the same between :c:func:`setup_vm` and +:c:func:`setup_vm_final` calls since the :c:var:`reserved_mem` array is +initialized with virtual addresses established by :c:func:`setup_vm` and used +with the mapping established by :c:func:`setup_vm_final`. + +Pre-MMU execution +----------------- + +A few pieces of code need to run before even the first virtual mapping is +established. These are the installation of the first virtual mapping itself, +patching of early alternatives and the early parsing of the kernel command line. +That code must be very carefully compiled as: + +- `-fno-pie`: This is needed for relocatable kernels which use `-fPIE`, since + otherwise, any access to a global symbol would go through the GOT which is + only relocated virtually. +- `-mcmodel=medany`: Any access to a global symbol must be PC-relative to avoid + any relocations to happen before the MMU is setup. +- *all* instrumentation must also be disabled (that includes KASAN, ftrace and + others). + +As using a symbol from a different compilation unit requires this unit to be +compiled with those flags, we advise, as much as possible, not to use external +symbols. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 175a91db0200..1f66062def6d 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -5,6 +5,7 @@ RISC-V architecture .. toctree:: :maxdepth: 1 + boot boot-image-header vm-layout hwprobe From patchwork Wed Jun 21 07:22:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 110849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp4197970vqr; Wed, 21 Jun 2023 01:06:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Dx1WVhwakJYZl60EG7kPqqGzG4KM/10VBAxH7rfdE0lcQ86SMbPN0sjVPMow91JdDBgaO X-Received: by 2002:ac8:7fd6:0:b0:3f6:bffe:3c02 with SMTP id b22-20020ac87fd6000000b003f6bffe3c02mr8993228qtk.45.1687334782896; Wed, 21 Jun 2023 01:06:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687334782; cv=none; d=google.com; s=arc-20160816; b=S58+0UJV2UWf3Mj4/jWiPcmmiwXrG0iyQ7QZi3MD7g6cXD+U7AAtAdBTIjlKscB8j/ jY3IZ7F1L4t/u3ZcVJjZ4KZES0YzlaseEittc/ADgBqguSfiyrZFnWWfpJaEPFxIRxFx 3fIAoINSHQRYD6ZbnxTU7GyMcRKh0vo9T7SPUmVQyIMgLYKSv5ubFwKWYlPqByBPs5Q/ gDTpMKGycrgxjXBccPTVjEki3/bikHzZvXuowxUs4sx9YRB8DQBhJXCUgwjWh1v2NceS SQiYRDKiV8SswkxOrylsOh3b2g5Gis/3cleKFDjRk6zMVogk14N9kgX1SwdYNOjmSL/l M+Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YQDRIqOL25lhh2vW3phUacbtXDC/Hgmm9aSu83e6n78=; b=ySvr2FnUdjx0n7JYfqk/NJvrOAKZZwOuSFdQO8dizNWwKCe7eIsIgje1Ar90e7kuXL 0qe7l0GppBoE8Ksf/UFs0cH6mAgEnNW3t6+IE4rG8++9pXk67DaguiSBTW6qrnglnTrF Ce6tHlZBLc+bCePyeRHQp0V66wCuH4Hn448iBUgodBp2pxzzDYZulNk9H1sxBjBee/wI Kkdsp12H4h6NC5a7VdLyuymixp7kOZQhKHMxIKhG7iQVw8H12G7tS9e+L6Ys65zqmW5B GnLetVgdS8ANe2C+0nEzEAWBGUduwFrhB0S6ur44zQfNGL5EuoFAz6taHSdD4wqRNJBI CJaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=x1xZiuSc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c210f00b003f18b942338sm4181118wml.3.2023.06.21.00.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 00:24:39 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra Subject: [PATCH v2 3/3] Documentation: riscv: Update boot image header since EFI stub is supported Date: Wed, 21 Jun 2023 09:22:34 +0200 Message-Id: <20230621072234.9900-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230621072234.9900-1-alexghiti@rivosinc.com> References: <20230621072234.9900-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769298757350276488?= X-GMAIL-MSGID: =?utf-8?q?1769298757350276488?= The EFI stub is supported on RISC-V so update the documentation that explains how the boot image header was reused to support it. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- Documentation/riscv/boot-image-header.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index a4a45310c4c4..df2ffc173e80 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -28,11 +28,11 @@ header in future. Notes ===== -- This header can also be reused to support EFI stub for RISC-V in future. EFI - specification needs PE/COFF image header in the beginning of the kernel image - in order to load it as an EFI application. In order to support EFI stub, - code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should - point to the rest of the PE/COFF header. +- This header is also reused to support EFI stub for RISC-V. EFI specification + needs PE/COFF image header in the beginning of the kernel image in order to + load it as an EFI application. In order to support EFI stub, code0 is replaced + with "MZ" magic string and res3(at offset 0x3c) points to the rest of the + PE/COFF header. - version field indicate header version number