From patchwork Wed Jun 21 06:08:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 110786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp4150649vqr; Tue, 20 Jun 2023 23:09:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6y92/Nyu8Z5A8WAj+gAq4DFU6qG9Od79x9xlP39H2akq1b1BiRtvwu5QIvFa7lUYBDV5C4 X-Received: by 2002:a05:6402:5241:b0:51a:4d22:dadc with SMTP id t1-20020a056402524100b0051a4d22dadcmr8988357edd.12.1687327794163; Tue, 20 Jun 2023 23:09:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687327794; cv=none; d=google.com; s=arc-20160816; b=IveITIkJ2IjO43nbh44SCu47vyBDziriwN9Xklxl3NcJzdWJwu8dahq2uGzTUMKHu5 J94VGwUI8N9UCXhGSs60Uh3ffRMrg/rUbYOqTgVj2GxnZalfLIIHrVp++44AxmMVKQrr QMZmKyI5EnkFN+fhzIPDbsZDetydo7pI1Y0ee6cC3NE0d10l7XdGj8bsBkrAAvpt6l17 LwnJM60diJIUstKH8zI88ZABo1r7sK9hzkgi2P4cr4eqXevFC1+TU1UETj52O9/FTPK9 brkt2psENQoAbbPVadwQBQUG5OaOrP/gCVXxpqzE/n2niy4qVceFvXuzp12ZX1BsGoG/ PfKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=ZXQiK6FqeK4PxmHPlvnAHD8Xo1eXXHbOmzCz0VGp15o=; b=Y0F5ndMFC0z09Od3ti4mgJQSdYjHzQSZwKlYu9OUkXAhBPb5y4PEy1yuUQLhNRzd2g btVjYu+IcqRWr3q/H/6VW7rBiAFxb/ReV9RpgIAezM/TUS9YI32KpCRRt4fAQ6X2VzNp InshEcjEuztIbeigtvHGxYrxmeNODMC+KfS+QxhQzHcIIDmuQx6RiVSdAypfdHIVBXq7 RXrLvcGz/SxRZ0bTY+ueYbtGOC0RnJcAifzelmtuSY+F1sbMX0Y9VOZYsqVOXP9OfHfS fvMc1ezml0GLJpDEwHJPgTRAu+wkYVeCJXUF8LsGhabn79W4lHjwATEK0fhKzJSu7pF3 29Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=g2SvO8Qw; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id r16-20020a056402035000b00518286f5834si1881751edw.29.2023.06.20.23.09.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 23:09:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=g2SvO8Qw; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C50403858C5E for ; Wed, 21 Jun 2023 06:09:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C50403858C5E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687327792; bh=ZXQiK6FqeK4PxmHPlvnAHD8Xo1eXXHbOmzCz0VGp15o=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=g2SvO8Qwnta55qPi4nRqV9pWS/s+eVLSbhJ1ZBfoelx5v7VNbV0InXL6LHAk/aYju KvmWQKdinlk7R4LhVv96dMYISOX8laZRxjrmCM24eT1Z1V2tihuAZVXRVLymqnEi5J G2cwv4aSC+qc3+ae7+XWSdtoCYFgmB16a8KrSuLQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 449083858D1E for ; Wed, 21 Jun 2023 06:09:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 449083858D1E X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="362620405" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="362620405" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 23:09:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="717501461" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="717501461" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 20 Jun 2023 23:09:04 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.159.126]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 3A2961006F14; Wed, 21 Jun 2023 14:09:04 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg. Date: Wed, 21 Jun 2023 14:08:42 +0800 Message-Id: <20230621060842.189680-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769291428931932555?= X-GMAIL-MSGID: =?utf-8?q?1769291428931932555?= From: Yanzhang Wang This patch will optimize the below mulh example, vint32m1_t shortcut_for_riscv_vmulh_case_0(vint32m1_t v1, size_t vl) { return __riscv_vmulh_vx_i32m1(v1, 0, vl); } from mulh pattern vsetvli zero, a2, e32, m1, ta, ma vmulh.vx v24, v24, zero vs1r.v v24, 0(a0) to below vmv. vsetvli zero,a2,e32,m1,ta,ma vmv.v.i v1,0 vs1r.v v1,0(a0) It will elimate the mul with const 0 instruction to the simple mov instruction. Signed-off-by: Yanzhang Wang gcc/ChangeLog: * config/riscv/autovec-opt.md: Add a split pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: The mul with 0 will be simplified to vmv.v.i. * gcc.target/riscv/rvv/autovec/vmulh-with-zero.cc: New test. Signed-off-by: Yanzhang Wang Signed-off-by: Yanzhang Wang --- gcc/config/riscv/autovec-opt.md | 30 +++++++++++++++++++ .../riscv/rvv/autovec/vmulh-with-zero.cc | 19 ++++++++++++ .../riscv/rvv/base/binop_vx_constraint-121.c | 3 +- 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmulh-with-zero.cc diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 28040805b23..9c14be964b5 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -405,3 +405,33 @@ "vmv.x.s\t%0,%1" [(set_attr "type" "vimovvx") (set_attr "mode" "")]) + +;; Simplify VMULH (V, 0) Instructions to vmv.v.i. +(define_split + [(set (match_operand:VI_QHS 0 "register_operand") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_all_trues_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (unspec:VI_QHS + [(vec_duplicate:VI_QHS + (match_operand: 4 "reg_or_0_operand")) + (match_operand:VI_QHS 3 "register_operand")] VMULH) + (match_operand:VI_QHS 2 "vector_merge_operand")))] + "TARGET_VECTOR + && rtx_equal_p (operands[4], CONST0_RTX (GET_MODE (operands[4])))" + [(const_int 0)] + { + machine_mode mask_mode = riscv_vector::get_mask_mode (mode) + .require (); + emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mask_mode), + RVV_VUNDEF (mode), CONST0_RTX (GET_MODE (operands[0])), + operands[5], operands[6], operands[7], operands[8])); + DONE; + } +) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmulh-with-zero.cc b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmulh-with-zero.cc new file mode 100644 index 00000000000..6e4a3d62bc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmulh-with-zero.cc @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +#define VMULH_WITH_LMUL(X) \ + vint32m##X##_t shortcut_for_riscv_vmulh_case_##X (vint32m##X##_t v1,\ + size_t vl) { \ + return __riscv_vmulh_vx_i32m ##X (v1, 0, vl); \ + } + + +VMULH_WITH_LMUL (1) +VMULH_WITH_LMUL (2) +VMULH_WITH_LMUL (4) +VMULH_WITH_LMUL (8) +VMULH_WITH_LMUL (f2) + +/* { dg-final { scan-assembler-times {vmv\.v\.i\sv[0-9]+,0} 5} */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c index 4d2de91bc14..d1473274137 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c @@ -50,6 +50,7 @@ void f6 (void * in, void *out, int32_t x) __riscv_vse64_v_i64m1 (out, v3, 4); } -/* { dg-final { scan-assembler-times {vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */ +/* { dg-final { scan-assembler-times {vmv\.v\.i\sv[0-9]+,0} 1 } } */ +/* { dg-final { scan-assembler-times {vmulh\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 1 } } */ /* { dg-final { scan-assembler-times {vdiv\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */ /* { dg-final { scan-assembler-times {vrem\.vx\s+v[0-9]+,\s*v[0-9]+,zero} 2 } } */