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[83.9.3.193]) by smtp.gmail.com with ESMTPSA id h19-20020a2eb0f3000000b002b3318c8d6fsm414433ljl.28.2023.06.20.06.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 06:18:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 20 Jun 2023 15:17:45 +0200 Subject: [PATCH 1/4] arm64: dts: qcom: sm6115: Add GPU nodes MIME-Version: 1.0 Message-Id: <20230620-topic-gpu_tablet_disp-v1-1-7bb02bec8dc0@linaro.org> References: <20230620-topic-gpu_tablet_disp-v1-0-7bb02bec8dc0@linaro.org> In-Reply-To: <20230620-topic-gpu_tablet_disp-v1-0-7bb02bec8dc0@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687267079; l=3562; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OuC7SSa/ZEBZmoqvHBeP3pcU5FY1FG2fXFlfgiPFlho=; b=htlJk1t63qgqq/6MtJEq+KWGc04BXOj0dhpuTkCrY3w+/byr4yplGaYTj9OA9K1UVTdl7c0j2 HSMdO8a4HxMDsdA8XeB5RHpwfulMUNFZjMMImsX61Fuq0Hp86+4oPIN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769227915289228188?= X-GMAIL-MSGID: =?utf-8?q?1769227915289228188?= Introduce nodes for the A610 GPU and its GMU wrapper along with the speedbin fuse entry in QFPROM. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 103 +++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 55118577bf92..424b4f3c909b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -865,6 +865,11 @@ qusb2_hstx_trim: hstx-trim@25b { reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@6006 { + reg = <0x6006 0x2>; + bits = <5 8>; + }; }; rng: rng@1b53000 { @@ -1316,6 +1321,104 @@ usb_dwc3: usb@4e00000 { }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-610.0", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interrupts = ; + + iommus = <&adreno_smmu 0 1>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-supported-hw = <0x1f>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xf>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0x7>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0x7>; + }; + + /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x4>; + }; + + opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x3>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; + gpucc: clock-controller@5990000 { compatible = "qcom,sm6115-gpucc"; reg = <0x0 0x05990000 0x0 0x9000>; From patchwork Tue Jun 20 13:17:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 110499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3672630vqr; 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Do note that there exists a second SKU with a different panel+touch combo, but due to insufficient information, that will need to be handled separately. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 57 +++++++++++++++++++++-- 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 81fdcaf48926..a10ce676bd44 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -65,9 +65,41 @@ ramoops@ffc00000 { }; }; -&dispcc { - /* HACK: disable until a panel driver is ready to retain simplefb */ - status = "disabled"; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm6125_l18>; + status = "okay"; + + panel: panel@0 { + compatible = "lenovo,j606f-boe-nt36523w", "novatek,nt36523w"; + reg = <0>; + + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + vddio-supply = <&pm6125_l9>; + + pinctrl-names = "default"; + pinctrl-0 = <&te_active &sde_dsi_active>; + + rotation = <180>; /* Yep, it's mounted upside down! */ + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm6125_gpios { @@ -212,8 +244,9 @@ pm6125_l17: l17 { }; pm6125_l18: l18 { - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1312000>; + /* 1.104V-1.312V fixed @ 1.232V for DSIPHY */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; }; pm6125_l19: l19 { @@ -282,6 +315,20 @@ sdc2_gate_pin: sdc2-gate-state { bias-pull-up; output-high; }; + + te_active: te-active-state { + pins = "gpio81"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_dsi_active: te-active-state { + pins = "gpio82"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; &ufs_mem_hc { From patchwork Tue Jun 20 13:17:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 110501 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3673832vqr; Tue, 20 Jun 2023 06:42:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6aOGGZU7sfs9tV141t565SA21z2w8mYh+m8cj+O4uXYbMFJzhBXO3gRh0/EElXwr4my5QB X-Received: by 2002:a05:6808:152a:b0:39b:5968:deb9 with SMTP id u42-20020a056808152a00b0039b5968deb9mr14573792oiw.39.1687268534223; Tue, 20 Jun 2023 06:42:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687268534; cv=none; d=google.com; s=arc-20160816; b=kmq5m1edom1YcNMMAPA4zZOP2f+T/X/scLj23N0KTR/J41/6VOqbA5LJiWr0Iq12rE 7163b3L5EOkhFw6A984ivQ3FUDVwVm5WsyxdOF9LTUTQMXOotPnh2YNJKOfNJpsxIZJW dqfuqdRZubyCgWo4BAqm3BpCyzwydNnZ0zFeus+ia9NpOtqsqzbuFuEPhlLfo4YcEwxd UhlOH6Gv1hTQE2EP2Mlzt6pENeK/bL+UyZCy7iX3SDBtf7HCFhEDL+4U23X5IkzwbdTS JHPLHlW9ADuP1AO+3oAXyJoWyFUVUNAjgHbxFPrKXFvm312YO8Sf9QnqCsfMhSXKvya5 SPqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=RPPnIKrExyggPEKNdXPVOY3qQ/GVfzx50WZpVsmSHmQ=; b=J0m2ULTR0JUHZWDeaceD7rOXPChqbElF1YuLdcGWUCnlSUhZDf+nHFFltW+hKYXO7+ vqsdJtnNkMx8TYdKJJI6zdPWJyxc0PV5dB/MY1SkUoXW/ku+1mljAegDjBXkidHG6JsT hkXOTmZDnNEK25D2PbWHvfSFAcCH7wiR3/+OSf9lw8kCWULGQeZZyBeFsojimbcIcZUA Vew05TQzawDgBplwtg+iSnAXVkWtYc+7B6rtBq3EnwaDdFzuthK2WXKuwQaipEGR9jK8 T6XtYYHn9OVOXweI3Q3SeTPrGS6+jdLvWDhNXbsjDMYJHPZwqilRTFieFrXnXgYODHOH fNlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hlweeu0G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index a10ce676bd44..ed745678fadd 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -65,6 +65,14 @@ ramoops@ffc00000 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; + }; +}; + &mdss { status = "okay"; }; From patchwork Tue Jun 20 13:17:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 110493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3671918vqr; Tue, 20 Jun 2023 06:38:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ62cVZYO1dSIxlreyUYJ5+F+8/OWrY8Kig3ZwhQbzWC/7cZCPtyhttvRvuONyFMm32XDg/X X-Received: by 2002:a05:6a20:8403:b0:11d:9249:170e with SMTP id c3-20020a056a20840300b0011d9249170emr18021510pzd.12.1687268334787; Tue, 20 Jun 2023 06:38:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687268334; cv=none; d=google.com; s=arc-20160816; b=Dww/jU7INOUNKfJB6a5SQWWKsLb7OA2bnHMvPL/7+7TSaP1ZUiMkzCKvA8a0v/E7lo 8SNH/WXmXZX7kQTEveHuskZUV4pISzPtys9n6k8mHhnvXlI3aa6k3Kp4V8PLL+1w36dQ Q/RWUW8qdmqs7P+TD41RRY87EOHVnTSXJKfBBEFc39ldO0NlB+0okHCh8aaajoT5nrBh Y+ghKG+G9/Aw6gyByH/IOLrLHdseRAlXElheG+ma7Ew/Vaa3RpAkav1FbXxiegQqaq81 yfuIMmK+qparkKA+N1KYhtYatKrbJGl7I3ANM3e9Lpsk4/bYNzlG9GJI5qemIMvphUPd RluA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=KFA5rv0lr1oloQt1B0KnKq65YwKUj3TfUmZ2SAZq8Ag=; b=RR9zZ88sAyHf8qTanAhoCg0PiNIpr2FzdiyGhaobkRiYzFi/BxCCPRu7OkDko+T4gc It6+VOxpGn23xIzElZC9qaoOp4cerOgC+ZhyfS+lcU/ORUP/MhFGibh1bBuX0BOOlakM smJDTSAzOJIQbzLK8q94PzB2FPLN1TavBssj9TfdVnNLl6E6V+3v7aSvN3QAPTVBf3aH NfN3WcsZJZbl/Aojs+P3QWQCQjJqUKqHI5spj/5e5J/Bebu5sOUl3LUd9cTUAubD5iwY FDJhFg6BGaW4sWDFFtetIrhCht8nR+f94fg9fjK4eA/++JOvt1TylW/q90inNQTI9FBV PYyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RON1O4AV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index e23a0406eacc..a7278a9472ed 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -179,6 +179,14 @@ &gpi_dma0 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qrb4210/a610_zap.mbn"; + }; +}; + &i2c2 { clock-frequency = <400000>; status = "okay";