From patchwork Tue Jun 20 12:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Dapp X-Patchwork-Id: 110459 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3637620vqr; Tue, 20 Jun 2023 05:48:32 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7qqIOvX7JmCnKYo+/gTK+VkoI69d1vPmvk7nFYLsjooDUCGfXJ4+rnBw9agS+cfhhOUDHn X-Received: by 2002:a05:6402:164c:b0:51a:4452:ae0c with SMTP id s12-20020a056402164c00b0051a4452ae0cmr6296503edx.35.1687265312735; Tue, 20 Jun 2023 05:48:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265312; cv=none; d=google.com; s=arc-20160816; b=v4xWLQZkOvqzEBHsm7SjURrPJONiKhwSqzetZPXHSK7BFelhPfigwEFVgbsfKMTA2Y u0IgkE7IVJ0oT+NeFMdCHu7nGj7TFNRoK0CkEH4vdzDFXn/Sb4QuM1r8tutHDqmfcbyp kIw+9t4f82FRJcmW7GCwnjCvCrDt/cx72GnoviWK0qj4F4emagIFBKGP/bqrsEsOOhBx WJN4rlBYXDYbYsMp+8GtV3t95xnsN4E0OoFtW4xQC9zOZgrV6ra5d5EpAq9v4YURmY/L 3ZRbPxtFJ6NqIqTYp5yjvfcXIg7EJv6P8NyQ2UnYIAuHSWXmBk0OTPn+paqpw7VoYsOw Ro+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:subject:to:content-language:cc:user-agent :mime-version:date:message-id:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=jC4T4AAB6x9PWbV8EC8kG1dkufeYmg5i8PAP1ysoTHQ=; b=YJSkTzBH8M4qF86uekndVFu+qhOC7LVCGIviFhZLvE9ElVoqiQlQFtSUFRDZLuixMU CXge+NRwVE4wMAXl7Qnq1vVueyyj7j3Cp2dB9DCfxzPvzGVnhKwkc7z/zCmLVmJOUg/K zCkqIhSCSmL3vIBptuGMUbKdPMYyKYKr3rfdH1mXRMDplQiNoZqX2V6kx3CkNnid/axF QRkL8iYl7BscGrr2Fci2GnZ5nGBMJTh3voG1XaGMKD1NKdp/8CJDS5eW1qo8K2GD1Zbb pkWaRbO1/GXL+UPun+dyXakQVEjL9WIldS8BrVKzk+PHbpmn9TaQEYaKPbzXIJ25l1qq mY+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=of9sfZl+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id r15-20020aa7d58f000000b0051a4f26507bsi1111094edq.45.2023.06.20.05.48.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 05:48:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=of9sfZl+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4342B385841C for ; Tue, 20 Jun 2023 12:48:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4342B385841C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687265311; bh=jC4T4AAB6x9PWbV8EC8kG1dkufeYmg5i8PAP1ysoTHQ=; h=Date:Cc:To:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=of9sfZl+gOZaYZGvknaOfAklnHV0dkqo5B81YpqJobqytVqU4LIndLcaE5hMzOkOj d1vpUfm5/IPbUTG3RAznjOExJjvlLjLjPaPKLpEWV0APOG/A3ekwyqDJ8hh0D0xRGu FxxQdYFnN10cO01q8HL0VW3wwExkeP7NKP6CBrIA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by sourceware.org (Postfix) with ESMTPS id 3F6733858D1E for ; Tue, 20 Jun 2023 12:47:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3F6733858D1E Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f97e08b012so27202185e9.3 for ; Tue, 20 Jun 2023 05:47:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687265266; x=1689857266; h=content-transfer-encoding:subject:from:to:content-language:cc :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=jC4T4AAB6x9PWbV8EC8kG1dkufeYmg5i8PAP1ysoTHQ=; b=CBW9Vrr13CyI/r4/9adYIj3B4gEtpBzqU7kdU9HldBQ827FXevYXJg75RoyGlRU/bY FcPU2dtd8rkXWzHCM0j+Kp1EMvuE/LJukuEzM5O5r1Et7fMioJBwq4WlWDPeDN6nfYcj Iqj1zMZnutj6obLRWiLlwwrtg+Oxx0EFZ4+b489QisGbquNAilTeH9Q94VN6rcbo98kv da7xNgZyUflk2DbBo0WEo3hzxP5J1z4PxzVV+p1VQw0uHCF6jEv4P+exRoU+cHHnmwHT Rbi7vhSzSid9TsLOJhbbmlexU3dkRK2agGohvq4O2f7sKM3/g2ytRH/eugpr//0QoH/s aBKw== X-Gm-Message-State: AC+VfDzycS45ogjXxFj8AR+A13KyeQPxdTPhyRvy6gxkIXq3U9kYloL2 eJC/PuFrlKOJtWKFKIX+bD1SoRT1SMw= X-Received: by 2002:a5d:4a45:0:b0:30f:b9a2:92c5 with SMTP id v5-20020a5d4a45000000b0030fb9a292c5mr10645141wrs.49.1687265265266; Tue, 20 Jun 2023 05:47:45 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id r15-20020a5d52cf000000b0030af72bca98sm1906036wrv.103.2023.06.20.05.47.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Jun 2023 05:47:44 -0700 (PDT) Message-ID: <8ea7c935-ee31-db3d-9672-14833b63d3b0@gmail.com> Date: Tue, 20 Jun 2023 14:47:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , jeffreyalaw Subject: [PATCH] RISC-V: Implement autovec copysign. X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769225912425116352?= X-GMAIL-MSGID: =?utf-8?q?1769225912425116352?= Hi, this adds vector copysign, ncopysign and xorsign as well as the accompanying tests. In order to easily match the ncopysign patterns I changed the builtin implementation slightly. Juzhe might want to comment on that. For now I kept the attribute's name even though it doesn't emit an "n" anymore. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (copysign3): Add expander. (xorsign3): Dito. * config/riscv/riscv-vector-builtins-bases.cc (class vfsgnjn): New class. * config/riscv/vector-iterators.md (copysign): Remove ncopysign. (xorsign): Dito. (n): Dito. (x): Dito. * config/riscv/vector.md (@pred_ncopysign): Split off. (@pred_ncopysign_scalar): Dito. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: New test. * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: New test. * gcc.target/riscv/rvv/autovec/binop/copysign-template.h: New test. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: New test. --- gcc/config/riscv/autovec.md | 43 +++++++++ .../riscv/riscv-vector-builtins-bases.cc | 18 +++- gcc/config/riscv/vector-iterators.md | 9 +- gcc/config/riscv/vector.md | 43 +++++++++ .../riscv/rvv/autovec/binop/copysign-run.c | 89 +++++++++++++++++++ .../rvv/autovec/binop/copysign-rv32gcv.c | 8 ++ .../rvv/autovec/binop/copysign-rv64gcv.c | 8 ++ .../rvv/autovec/binop/copysign-template.h | 78 ++++++++++++++++ .../rvv/autovec/binop/copysign-zvfh-run.c | 83 +++++++++++++++++ 9 files changed, 371 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f1641d7e1ea..f2e69aaf102 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -804,3 +804,46 @@ (define_expand "3" riscv_vector::RVV_BINOP, operands); DONE; }) + +;; ------------------------------------------------------------------------------- +;; ---- [FP] Sign copying +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfsgnj.vv/vfsgnjn.vv +;; - vfsgnj.vf/vfsgnjn.vf +;; ------------------------------------------------------------------------------- + +;; Leave the pattern like this as to still allow combine to match +;; a negated copysign (see vector.md) before adding the UNSPEC_VPREDICATE later. +(define_insn_and_split "copysign3" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (unspec:VF + [(match_operand:VF 1 "register_operand" " vr, vr, vr, vr") + (match_operand:VF 2 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] +{ + riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, mode), + riscv_vector::RVV_BINOP, operands); + DONE; +} + [(set_attr "type" "vfsgnj") + (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------------- +;; Includes: +;; - vfsgnjx.vv +;; - vfsgnjx.vf +;; ------------------------------------------------------------------------------- +(define_expand "xorsign3" + [(match_operand:VF_AUTO 0 "register_operand") + (match_operand:VF_AUTO 1 "register_operand") + (match_operand:VF_AUTO 2 "register_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, mode), + riscv_vector::RVV_BINOP, operands); + DONE; +}) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index c6c53dc13a5..0313986f6b9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -1212,7 +1212,7 @@ public: } }; -/* Implements vfsqrt7/vfrec7/vfclass/vfsgnj/vfsgnjn/vfsgnjx. */ +/* Implements vfsqrt7/vfrec7/vfclass/vfsgnj/vfsgnjx. */ template class float_misc : public function_base { @@ -1227,6 +1227,20 @@ public: } }; +/* Implements vfsgnjn. */ +class vfsgnjn : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_exact_insn (code_for_pred_ncopysign_scalar (e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_exact_insn (code_for_pred_ncopysign (e.vector_mode ())); + gcc_unreachable (); + } +}; + /* Implements vmfeq/vmfne/vmflt/vmfgt/vmfle/vmfge. */ template class fcmp : public function_base @@ -2031,7 +2045,7 @@ static CONSTEXPR const float_misc vfrec7_obj; static CONSTEXPR const binop vfmin_obj; static CONSTEXPR const binop vfmax_obj; static CONSTEXPR const float_misc vfsgnj_obj; -static CONSTEXPR const float_misc vfsgnjn_obj; +static CONSTEXPR const vfsgnjn vfsgnjn_obj; static CONSTEXPR const float_misc vfsgnjx_obj; static CONSTEXPR const unop vfneg_obj; static CONSTEXPR const unop vfabs_obj; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 6ca1c54c709..318e70faef9 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -1480,14 +1480,11 @@ (define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif") (UNSPEC_VMSO (define_int_attr float_insn_type [(UNSPEC_VFRSQRT7 "vfsqrt") (UNSPEC_VFREC7 "vfrecp")]) -(define_int_iterator VCOPYSIGNS [UNSPEC_VCOPYSIGN UNSPEC_VNCOPYSIGN UNSPEC_VXORSIGN]) +(define_int_iterator VCOPYSIGNS [UNSPEC_VCOPYSIGN UNSPEC_VXORSIGN]) -(define_int_attr copysign [(UNSPEC_VCOPYSIGN "copysign") - (UNSPEC_VNCOPYSIGN "ncopysign") - (UNSPEC_VXORSIGN "xorsign")]) +(define_int_attr copysign [(UNSPEC_VCOPYSIGN "copysign") (UNSPEC_VXORSIGN "xorsign")]) -(define_int_attr nx [(UNSPEC_VCOPYSIGN "") (UNSPEC_VNCOPYSIGN "n") - (UNSPEC_VXORSIGN "x")]) +(define_int_attr nx [(UNSPEC_VCOPYSIGN "") (UNSPEC_VXORSIGN "x")]) (define_int_attr ud [(UNSPEC_VSLIDEUP "up") (UNSPEC_VSLIDEDOWN "down") (UNSPEC_VSLIDE1UP "1up") (UNSPEC_VSLIDE1DOWN "1down") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 884e7435cc2..aa81b9023d8 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5820,6 +5820,27 @@ (define_insn "@pred_" [(set_attr "type" "vfsgnj") (set_attr "mode" "")]) +(define_insn "@pred_ncopysign" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (neg:VF + (unspec:VF + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN)) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vfsgnjn.vv\t%0,%3,%4%p1" + [(set_attr "type" "vfsgnj") + (set_attr "mode" "")]) + (define_insn "@pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") (if_then_else:VF @@ -5841,6 +5862,28 @@ (define_insn "@pred__scalar" [(set_attr "type" "vfsgnj") (set_attr "mode" "")]) +(define_insn "@pred_ncopysign_scalar" + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:VF + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (neg:VF + (unspec:VF + [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") + (vec_duplicate:VF + (match_operand: 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN)) + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + "TARGET_VECTOR" + "vfsgnjn.vf\t%0,%3,%4%p1" + [(set_attr "type" "vfsgnj") + (set_attr "mode" "")]) + ;; ------------------------------------------------------------------------------- ;; ---- Predicated floating-point ternary operations ;; ------------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c new file mode 100644 index 00000000000..7a6d429c9a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c @@ -0,0 +1,89 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "copysign-template.h" + +#include + +#define SZ 512 + +#define EPS 1e-6 + +#define RUN(TYPE,VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i; \ + b##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + copysign_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a##TYPE[i] - ((i & 1) ? i : -i)) < EPS); \ + +#define RUN2(TYPE,VAL) \ + TYPE a2##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a2##TYPE[i] = i; \ + copysigns_##TYPE (a2##TYPE, a2##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a2##TYPE[i] + i) < EPS); \ + +#define RUN3(TYPE,VAL) \ + TYPE a3##TYPE[SZ]; \ + TYPE b3##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a3##TYPE[i] = (i & 1) ? -i : i; \ + b3##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + xorsign_##TYPE (a3##TYPE, a3##TYPE, b3##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a3##TYPE[i] + i) < EPS); \ + +#define RUN4(TYPE,VAL) \ + TYPE a4##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a4##TYPE[i] = -i; \ + xorsigns_##TYPE (a4##TYPE, a4##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a4##TYPE[i] - i) < EPS); \ + +#define RUN5(TYPE,VAL) \ + TYPE a5##TYPE[SZ]; \ + TYPE b5##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a5##TYPE[i] = i; \ + b5##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + ncopysign_##TYPE (a5##TYPE, a5##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (-a5##TYPE[i] - ((i & 1) ? i : -i)) < EPS); \ + +#define RUN6(TYPE,VAL) \ + TYPE a6##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a6##TYPE[i] = i; \ + ncopysigns_##TYPE (a6##TYPE, a6##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (-a6##TYPE[i] + i) < EPS); \ + +#define RUN_ALL() \ + RUN(float, 5) \ + RUN(double, 6) \ + RUN2(float, 11) \ + RUN2(double, 12) \ + RUN3(float, 16) \ + RUN3(double, 18) \ + RUN4(float, 17) \ + RUN4(double, 19) \ + RUN5(float, 123) \ + RUN5(double, 523) \ + RUN6(float, 777) \ + RUN6(double, 877) \ + +int main () +{ + RUN_ALL() +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c new file mode 100644 index 00000000000..ab675aee208 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "copysign-template.h" + +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c new file mode 100644 index 00000000000..b252ddfe59f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "copysign-template.h" + +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-template.h new file mode 100644 index 00000000000..df2274fd3ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-template.h @@ -0,0 +1,78 @@ +#include + +#define TEST_TYPE(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void copysign_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE *restrict b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_copysign##SUFFIX (a[i], b[i]); \ + } + +#define TEST_TYPE2(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void copysigns_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = __builtin_copysign##SUFFIX (a[i], b); \ + } + +#define TEST_TYPE3(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void xorsign_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE *restrict b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * __builtin_copysign##SUFFIX (1.0, b[i]); \ + } + +#define TEST_TYPE4(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void xorsigns_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * __builtin_copysign##SUFFIX (1.0, b); \ + } + +#define TEST_TYPE5(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void ncopysign_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE *restrict b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -__builtin_copysign##SUFFIX (a[i], b[i]); \ + } + +#define TEST_TYPE6(TYPE, SUFFIX) \ + __attribute__((noipa)) \ + void ncopysigns_##TYPE (TYPE *restrict dst, TYPE *restrict a, \ + TYPE b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = -__builtin_copysign##SUFFIX (a[i], b); \ + } + + +#define TEST_ALL() \ + TEST_TYPE(_Float16,f16) \ + TEST_TYPE(float,f) \ + TEST_TYPE(double,) \ + TEST_TYPE2(_Float16,f16) \ + TEST_TYPE2(float,f) \ + TEST_TYPE2(double,) \ + TEST_TYPE3(_Float16,f16) \ + TEST_TYPE3(float,f) \ + TEST_TYPE3(double,) \ + TEST_TYPE4(_Float16,f16) \ + TEST_TYPE4(float,f) \ + TEST_TYPE4(double,) \ + TEST_TYPE5(_Float16,f16) \ + TEST_TYPE5(float,f) \ + TEST_TYPE5(double,) \ + TEST_TYPE6(_Float16,f16) \ + TEST_TYPE6(float,f) \ + TEST_TYPE6(double,) \ + +TEST_ALL() diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c new file mode 100644 index 00000000000..7aaac9794f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c @@ -0,0 +1,83 @@ +/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ + +#include "copysign-template.h" + +#include + +#define SZ 512 + +#define EPS 1e-6 + +#define RUN(TYPE,VAL) \ + TYPE a##TYPE[SZ]; \ + TYPE b##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a##TYPE[i] = i; \ + b##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + copysign_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a##TYPE[i] - ((i & 1) ? i : -i)) < EPS); \ + +#define RUN2(TYPE,VAL) \ + TYPE a2##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a2##TYPE[i] = i; \ + copysigns_##TYPE (a2##TYPE, a2##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a2##TYPE[i] + i) < EPS); \ + +#define RUN3(TYPE,VAL) \ + TYPE a3##TYPE[SZ]; \ + TYPE b3##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a3##TYPE[i] = (i & 1) ? -i : i; \ + b3##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + xorsign_##TYPE (a3##TYPE, a3##TYPE, b3##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a3##TYPE[i] + i) < EPS); \ + +#define RUN4(TYPE,VAL) \ + TYPE a4##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a4##TYPE[i] = -i; \ + xorsigns_##TYPE (a4##TYPE, a4##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (a4##TYPE[i] - i) < EPS); \ + +#define RUN5(TYPE,VAL) \ + TYPE a5##TYPE[SZ]; \ + TYPE b5##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + { \ + a5##TYPE[i] = i; \ + b5##TYPE[i] = (i & 1) ? VAL : -VAL; \ + } \ + ncopysign_##TYPE (a5##TYPE, a5##TYPE, b##TYPE, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (-a5##TYPE[i] - ((i & 1) ? i : -i)) < EPS); \ + +#define RUN6(TYPE,VAL) \ + TYPE a6##TYPE[SZ]; \ + for (int i = 0; i < SZ; i++) \ + a6##TYPE[i] = i; \ + ncopysigns_##TYPE (a6##TYPE, a6##TYPE, -VAL, SZ); \ + for (int i = 0; i < SZ; i++) \ + assert (__builtin_fabs (-a6##TYPE[i] + i) < EPS); \ + +#define RUN_ALL() \ + RUN(_Float16, 5) \ + RUN2(_Float16, 11) \ + RUN3(_Float16, 16) \ + RUN4(_Float16, 17) \ + RUN5(_Float16, 123) \ + RUN6(_Float16, 777) \ + +int main () +{ + RUN_ALL() +}