From patchwork Tue Jun 20 08:49:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: HAO CHEN GUI X-Patchwork-Id: 110347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp3518701vqr; Tue, 20 Jun 2023 01:50:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4ZPvIsuF+zdug7qRHsu3VX3/k/7vn6iK896l88cOV4xE+hoSvk17WMkjzmKPyZDsiJyq1Y X-Received: by 2002:a50:fb8a:0:b0:51a:5ec4:ade6 with SMTP id e10-20020a50fb8a000000b0051a5ec4ade6mr2545804edq.12.1687251009641; Tue, 20 Jun 2023 01:50:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687251009; cv=none; d=google.com; s=arc-20160816; b=J5UBA/ewLoJgDKtMbIe4v/6bJA5IXqnWZNTid2kCzHpeDsgWSn/Lsa4gMV6hXeljpq rlj4j3+KDS/iuKpdwbaf44Rdrc3+//S+12WGKRtfOUEE0Iez1a9fxomWv8cSx90ebsDg AFhX/6/ag1ChgCT74kVJXxXfyjWoWABq041axMGXIwm1vs/X4YnRSaGcODewmhGGSZFh jaTkM8JhnAUXrV5ByEu0V9Bnm7caEhy87sGjLfAPm86evJ8cvNu7m2X2Dqo71eSgHQGI SZvAxFili1s4KR8d1ETwSSm939v4BKykML8/6v1WHo9hUU7T2n+hfVwlJ26F1pBTs/Jz G0oQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:subject:cc:to:content-language:user-agent :mime-version:date:message-id:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=h4zm9/0t2gGUt5jU2saMNBP2W88J0XPDoBpfJk9FIg0=; b=sIqp3SLQYwZuYZXJeudSWIMcZdkXEyvN/Eko76wFi6k77vNlLCaqIjtDCXYHp96Ofc T9CjJoON0aQclmQjAsF5jMxiRRjyhsHPVIk+lywHNPqYiKDnLaKxID+3pNCqVJSQJAvu sRyNMWBR7LEdg1nr9//MVXMrTAkxhoJR6dYfWRxhPzBEPG4uwumHFUTr8cFthRE5aut+ PRAIgrikjr7TUIHQddZkCX9bRaH6dakucTBxp+h4+vom+lFqQ+YG39CVaunDYfPzJLOM 28bWl4XhHPRgdmhjzL1tm3DdZtN2ea8gGfccxBLCOwh19ENTEqxGt/wAZ+jjKChv79m9 I4SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Hz51n5ff; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w11-20020a056402070b00b005169ffc81acsi924262edx.111.2023.06.20.01.50.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 01:50:09 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Hz51n5ff; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1B2C1385843E for ; Tue, 20 Jun 2023 08:50:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1B2C1385843E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687251008; bh=h4zm9/0t2gGUt5jU2saMNBP2W88J0XPDoBpfJk9FIg0=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Hz51n5ffVlUuWwmkeaG6OPEs0SzpaxakSqYlLVPX/wi8wTXY9GBYSTaGSJBPKBCJb 74JQf23uZlDMpbUgzJrlv5gqzDtpHgIgo7E83/v6vR2oMn4uqSJQ7Rhcaw3btqsXPd cllmQNOKViWVZEX4wgQGlrzVY3O1u+PmnskI2A9A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id F14D13858D1E for ; Tue, 20 Jun 2023 08:49:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F14D13858D1E Received: from pps.filterd (m0353726.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35K8l7tf015512; Tue, 20 Jun 2023 08:49:15 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rb8wgg0wv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 08:49:15 +0000 Received: from m0353726.ppops.net (m0353726.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 35K8mGeI018373; Tue, 20 Jun 2023 08:49:15 GMT Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3rb8wgg0w2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 08:49:14 +0000 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 35K4qedC005345; Tue, 20 Jun 2023 08:49:11 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma02fra.de.ibm.com (PPS) with ESMTPS id 3r94f59fd9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Jun 2023 08:49:10 +0000 Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35K8n7C532047544 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 20 Jun 2023 08:49:07 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 34BC120043; Tue, 20 Jun 2023 08:49:07 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ADC3D2004E; Tue, 20 Jun 2023 08:49:05 +0000 (GMT) Received: from [9.200.144.106] (unknown [9.200.144.106]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 20 Jun 2023 08:49:05 +0000 (GMT) Message-ID: Date: Tue, 20 Jun 2023 16:49:04 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner Subject: [PATCHv4, rs6000] Add two peephole2 patterns for mr. insn X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: xIf4D71rY0KHPqUpTOzx_SuPNTSgNBf2 X-Proofpoint-GUID: 5HB369HirbaCRSZ9xE7x4sJlbIaVEjIJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-20_05,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306200076 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768462578540339885?= X-GMAIL-MSGID: =?utf-8?q?1769210914831475362?= Hi, This patch adds two peephole2 patterns which help convert certain insn sequences to "mr." instruction. These insn sequences can't be combined in combine pass. Compared to last version, the empty constraint is removed and test cases run only on powerpc Linux as AIX doesn't support "-mregnames" option. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Thanks Gui Haochen ChangeLog rs6000: Add two peephole patterns for "mr." insn When investigating the issue mentioned in PR87871#c30 - if compare and move pattern benefits before RA, I checked the assembly generated for SPEC2017 and found that certain insn sequences aren't converted to "mr." instructions. Following two sequence are never to be combined to "mr." pattern as there is no register link between them. This patch adds two peephole2 patterns to convert them to "mr." instructions. cmp 0,3,0 mr 4,3 mr 4,3 cmp 0,3,0 The patch also creates a new mode iterator which decided by TARGET_POWERPC64. This mode iterator is used in "mr." and its split pattern. The original P iterator is wrong when -m32/-mpowerpc64 is set. In this situation, the "mr." should compares the whole 64-bit register with 0 other than the low 32-bit one. gcc/ * config/rs6000/rs6000.md (peephole2 for compare_and_move): New. (peephole2 for move_and_compare): New. (mode_iterator WORD): New. Set the mode to SI/DImode by TARGET_POWERPC64. (*mov_internal2): Change the mode iterator from P to WORD. (split pattern for compare_and_move): Likewise. gcc/testsuite/ * gcc.dg/rtl/powerpc/move_compare_peephole_32.c: New. * gcc.dg/rtl/powerpc/move_compare_peephole_64.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b0db8ae508d..2ab1e8d4c80 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -491,6 +491,7 @@ (define_mode_iterator SDI [SI DI]) ; The size of a pointer. Also, the size of the value that a record-condition ; (one with a '.') will compare; and the size used for arithmetic carries. (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) +(define_mode_iterator WORD [(SI "!TARGET_POWERPC64") (DI "TARGET_POWERPC64")]) ; Iterator to add PTImode along with TImode (TImode can go in VSX registers, ; PTImode is GPR only) @@ -7879,9 +7880,9 @@ (define_split (define_insn "*mov_internal2" [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") - (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") + (compare:CC (match_operand:WORD 1 "gpc_reg_operand" "0,r,r") (const_int 0))) - (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] + (set (match_operand:WORD 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] "" "@ cmpi %2,%0,0 @@ -7891,11 +7892,41 @@ (define_insn "*mov_internal2" (set_attr "dot" "yes") (set_attr "length" "4,4,8")]) +(define_peephole2 + [(set (match_operand:CC 2 "cc_reg_operand") + (compare:CC (match_operand:WORD 1 "int_reg_operand") + (const_int 0))) + (set (match_operand:WORD 0 "int_reg_operand") + (match_dup 1))] + "!cc_reg_not_cr0_operand (operands[2], CCmode)" + [(parallel [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:WORD 1 "int_reg_operand" "r") + (const_int 0))) + (set (match_operand:WORD 0 "int_reg_operand" "=r") + (match_dup 1))])] + "" +) + +(define_peephole2 + [(set (match_operand:WORD 0 "int_reg_operand") + (match_operand:WORD 1 "int_reg_operand")) + (set (match_operand:CC 2 "cc_reg_operand") + (compare:CC (match_dup 1) + (const_int 0)))] + "!cc_reg_not_cr0_operand (operands[2], CCmode)" + [(parallel [(set (match_operand:CC 2 "cc_reg_operand" "=x") + (compare:CC (match_operand:GPR 1 "int_reg_operand" "r") + (const_int 0))) + (set (match_operand:WORD 0 "int_reg_operand" "=r") + (match_dup 1))])] + "" +) + (define_split [(set (match_operand:CC 2 "cc_reg_not_cr0_operand") - (compare:CC (match_operand:P 1 "gpc_reg_operand") + (compare:CC (match_operand:WORD 1 "gpc_reg_operand") (const_int 0))) - (set (match_operand:P 0 "gpc_reg_operand") (match_dup 1))] + (set (match_operand:WORD 0 "gpc_reg_operand") (match_dup 1))] "reload_completed" [(set (match_dup 0) (match_dup 1)) (set (match_dup 2) diff --git a/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c new file mode 100644 index 00000000000..571a3112a74 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_32.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-skip-if "" { has_arch_ppc64 } } */ +/* { dg-options "-O2 -mregnames" } */ + +/* Following instruction sequence is found in assembly of + Perl_block_start, which is a function of op.c in SPEC2017 + perlbench. It can be never combined to a move and compare + instruction in combine pass. A peephole pattern is needed to + converted the sequence to a "mr." instruction. + + cmpdi 0,9,0 + mr 12,9 + + This test case is an analogue of the source code and verifies + if the peephole2 patterns work. +*/ + +int __RTL (startwith ("peephole2")) compare_move_peephole () +{ +(function "compare_move_peephole" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 8 (set (reg:CC %cr0) + (compare:CC (reg:SI %r3) + (const_int 0)))) + (cinsn 2 (set (reg:SI %r4) + (reg:SI %r3))) + ;; Extra insn to avoid the above being deleted by DCE. + (cinsn 18 (use (reg:SI %r4))) + (cinsn 19 (use (reg:CC %cr0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain +) ;; function "main" +} + +int __RTL (startwith ("peephole2")) move_compare_peephole () +{ +(function "move_compare_peephole" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg:SI %r4) + (reg:SI %r3))) + (cinsn 8 (set (reg:CC %cr0) + (compare:CC (reg:SI %r3) + (const_int 0)))) + ;; Extra insn to avoid the above being deleted by DCE. + (cinsn 18 (use (reg:SI %r4))) + (cinsn 19 (use (reg:CC %cr0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain +) ;; function "main" +} + +/* { dg-final { scan-assembler-times {\mmr\.} 2 } } */ diff --git a/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c new file mode 100644 index 00000000000..e25d655fb29 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/powerpc/move_compare_peephole_64.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-O2 -mregnames" } */ +/* { dg-require-effective-target has_arch_ppc64 } */ + +/* Following instruction sequence is found in assembly of + Perl_block_start, which is a function of op.c in SPEC2017 + perlbench. It can be never combined to a move and compare + instruction in combine pass. A peephole pattern is needed to + converted the sequence to a "mr." instruction. + + cmpdi 0,9,0 + mr 12,9 + + This test case is an analogue of the source code and verifies + if the peephole2 patterns work. +*/ + +int __RTL (startwith ("peephole2")) compare_move_peephole () +{ +(function "compare_move_peephole" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 8 (set (reg:CC %cr0) + (compare:CC (reg:DI %r3) + (const_int 0)))) + (cinsn 2 (set (reg:DI %r4) + (reg:DI %r3))) + ;; Extra insn to avoid the above being deleted by DCE. + (cinsn 18 (use (reg:DI %r4))) + (cinsn 19 (use (reg:CC %cr0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain +) ;; function "main" +} + +int __RTL (startwith ("peephole2")) move_compare_peephole () +{ +(function "move_compare_peephole" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (cinsn 2 (set (reg:DI %r4) + (reg:DI %r3))) + (cinsn 8 (set (reg:CC %cr0) + (compare:CC (reg:DI %r3) + (const_int 0)))) + ;; Extra insn to avoid the above being deleted by DCE. + (cinsn 18 (use (reg:DI %r4))) + (cinsn 19 (use (reg:CC %cr0))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain +) ;; function "main" +} + +/* { dg-final { scan-assembler-times {\mmr\.} 2 } } */